Lecture 13: Datapath Functional Units
Transcript of Lecture 13: Datapath Functional Units
Lecture 13: DatapathFunctionalUnits
CMOS VLSI DesignCMOS VLSI Design 4th Ed.18: Datapath Functional Units 2
Outlineq Comparatorsq Shiftersq Multi-input Addersq Multipliers
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Comparatorsq 0�s detector: A = 00…000q 1�s detector: A = 11…111q Equality comparator: A = Bq Magnitude comparator: A < B
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1�s & 0�s Detectorsq 1�s detector: N-input AND gateq 0�s detector: NOTs + 1�s detector (N-input NOR)
A0A1
A2A3
A4A5
A6A7
allones
A0A1
A2A3
allzeros
allones
A1
A2A3
A4A5
A6A7
A0
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Equality Comparatorq Check if each bit is equal (XNOR, aka equality gate)q 1�s detect on bitwise equality
A[0]B[0]
A = B
A[1]B[1]A[2]B[2]A[3]B[3]
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Magnitude Comparatorq Compute B – A and look at signq B – A = B + ~A + 1q For unsigned numbers, carry out is sign bit
A0
B0
A1
B1
A2
B2
A3
B3
A = BZ
C
A B£
N A B³
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Signed vs. Unsignedq For signed numbers, comparison is harder
– C: carry out– Z: zero (all bits of A – B are 0)– N: negative (MSB of result)– V: overflow (inputs had different signs, output sign ≠ B)– S: N xor V (sign of result)
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Shiftersq Logical Shift:
– Shifts number left or right and fills with 0�s• 1011 LSR 1 = 0101 1011 LSL1 = 0110
q Arithmetic Shift:– Shifts number left or right. Rt shift sign extends
• 1011 ASR1 = 1101 1011 ASL1 = 0110q Rotate:
– Shifts number left or right and fills with lost bits• 1011 ROR1 = 1101 1011 ROL1 = 0111
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Funnel Shifterq A funnel shifter can do all six types of shiftsq Selects N-bit field Y from 2N–1-bit input
– Shift by k bits (0 ≤ k < N)– Logically involves N N:1 multiplexers
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Funnel Source Generator
Rotate RightLogical Right
Arithmetic Right
Rotate LeftLogical/Arithmetic Left
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Array Funnel Shifterq N N-input multiplexers
– Use 1-of-N hot select signals for shift amount– nMOS pass transistor design (Vt drops!)
k[1:0]
s0s1s2s3Y3
Y2
Y1
Y0
Z0Z1Z2Z3Z4
Z5
Z6
left Inverters & Decoder
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Logarithmic Funnel Shifterq Log N stages of 2-input muxes
– No select decoding needed
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32-bit Logarithmic Funnelq Wider multiplexers reduce delay and powerq Operands > 32 bits introduce datapath irregularity
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Barrel Shifterq Barrel shifters perform right rotations using wrap-
around wires.q Left rotations are right rotations by N – k = k + 1 bits.q Shifts are rotations with the end bits masked off.
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Logarithmic Barrel Shifter
Right shift only
Right/Left shift Right/Left Shift & Rotate
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32-bit Logarithmic Barrelq Datapath never wider than 32 bitsq First stage preshifts by 1 to handle left shifts
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Multi-input Addersq Suppose we want to add k N-bit words
– Ex: 0001 + 0111 + 1101 + 0010 = 10111q Straightforward solution: k-1 N-input CPAs
– Large and slow
+
+
0001 0111
+
1101 0010
10101
10111
1000
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Carry Save Additionq A full adder sums 3 inputs and produces 2 outputs
– Carry output has twice weight of sum outputq N full adders in parallel are called carry save adder
– Produce N sums and N carry outsZ4Y4X4
S4C4
Z3Y3X3
S3C3
Z2Y2X2
S2C2
Z1Y1X1
S1C1
XN...1 YN...1 ZN...1
SN...1CN...1
n-bit CSA
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CSA Applicationq Use k-2 stages of CSAs
– Keep result in carry-save redundant formq Final CPA computes actual result
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
10110101_
01010_ 00011
0001 0111+1101 10110101_
XYZSC
0101_ 1011 +0010 0001101010_
XYZSC
01010_+ 00011 10111
ABS
10111
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Multiplicationq Example:
q M x N-bit multiplication– Produce N M-bit partial products– Sum these to produce M+N-bit product
1100 : 1210 0101 : 510 1100 0000 1100 000000111100 : 6010
multipliermultiplicand
partialproducts
product
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General Formq Multiplicand: Y = (yM-1, yM-2, …, y1, y0)q Multiplier: X = (xN-1, xN-2, …, x1, x0)
q Product:1 1 1 1
0 0 0 0
2 2 2M N N M
j i i jj i i j
j i i j
P y x x y- - - -
+
= = = =
æ öæ ö= =ç ÷ç ÷è øè ø
å å åå
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
y5 y4 y3 y2 y1 y0x5 x4 x3 x2 x1 x0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0x2y5 x2y4 x2y3 x2y2 x2y1 x2y0
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0p0p1p2p3p4p5p6p7p8p9p10p11
multipliermultiplicand
partialproducts
product
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Dot Diagramq Each dot represents a bit
partial products
multiplier x
x0
x15
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Array Multipliery0y1y2y3
x0
x1
x2
x3
p0p1p2p3p4p5p6p7
B
ASin Cin
SoutCout
BA
CinCout
Sout
Sin=
CSAArray
CPA
critical path BA
Sout
Cout CinCout
Sout
=Cin
BA
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Rectangular Arrayq Squash array to fit rectangular floorplan
y0y1y2y3
x0
x1
x2
x3
p0
p1
p2
p3
p4p5p6p7
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Fewer Partial Productsq Array multiplier requires N partial productsq If we looked at groups of r bits, we could form N/r
partial products.– Faster and smaller?– Called radix-2r encoding
q Ex: r = 2: look at pairs of bits– Form partial products of 0, Y, 2Y, 3Y– First three are easy, but 3Y requires adder L
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Booth Encodingq Instead of 3Y, try –Y, then increment next partial
product to add 4Yq Similarly, for 2Y, try –2Y + 4Y in next partial product
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Booth Hardwareq Booth encoder generates control lines for each PP
– Booth selectors choose PP bits
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Sign Extensionq Partial products can be negative
– Require sign extension, which is cumbersome– High fanout on most significant bit
multiplier x
x0
x15
0
00
x-1
x16x17
ssssssssssssssss
ssssssssssssss
ssssssssssss
ssssssssss
ssssssss
ssssss
ssss
ss
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PP8
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Simplified Sign Ext.q Sign bits are either all 0�s or all 1�s
– Note that all 0�s is all 1�s + 1 in proper column– Use this to reduce loading on MSB
s111111111111111s
s1111111111111s
s11111111111s
s111111111s
s1111111s
s11111s
s111s
s1s
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PP8
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Even Simpler Sign Ext.q No need to add all the 1�s in hardware
– Precompute the answer!
ssss
ss1
ss1
ss1
ss1
ss1
ss1
ss
PP0PP1PP2PP3PP4PP5PP6PP7PP8
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Advanced Multiplicationq Signed vs. unsigned inputsq Higher radix Booth encodingq Array vs. tree CSA networks