Lecture 12: Registers and Counters -...

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Lecture 12: Registers and Counters Aby K George, ECE Department, Wayne State University Syed M. Mahmud, Ph.D ECE Department Wayne State University

Transcript of Lecture 12: Registers and Counters -...

Lecture 12: Registers and Counters

Aby K George, ECE Department, Wayne State University

Syed M. Mahmud, Ph.DECE Department

Wayne State University

Contents

• Registers

• Shift Registers

• Ripple Counters

• Synchronous Counters

• Other Counters

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Registers• A register is a group of flip-flops (FFs), each one of which shares a

common clock and is capable of storing one bit of information.

• 𝑛-bit register -> 𝑛 FFs

• A counter is also a register that goes through a predetermined sequence of binary states.

• Clear and Preset pins of the FFs can be used to initialize the FFs.

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Register with Parallel Load

• The transfer of new information to the register is called loading or updating the register.

• If all the bits of the register are loaded simultaneously with a common clock pulse, then the loading is said to be in parallel.

• The simultaneous changes in all the inputs is difficult to achieve.

• To make the register content unchanged, there are two ways• Inputs must held constant

• Clock must be inhibited from the circuit

• Inserting gates into the clock path is not good.

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Register with Parallel Load

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Shift Register

• A register capable of shifting the binary information held in each cell to its neighboring cell, in a selected direction, is called a shift register.

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Universal Shift Register

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Counters

• A register that goes through a prescribed sequence upon the application of input pulse is called counter.

• The sequence may be binary sequence or other sequences.

• The counter that follows binary number sequence is called binary counter.

• 𝑛-bit counter consists of 𝑛 FFs, and can count from 0 to 2𝑛 − 1

• Two categories:• Ripple counter

• Synchronous counter

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Binary Ripple Counter

• Output of FF connected to the clock input of the next FF.

• Works with toggling mode of FFs. (T=1, J=K=1, D=Q’)

• Frequency divider

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RippleCounters

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Synchronous Counters

• Clock pulses are applied to all the FFs

• Follows the synchronous sequential circuit design procedure.

• Procedure:• Make the state diagram

• Draw the state table with present state and next state.

• Based on the FF you are using, generate the FF inputs using the excitation table.

• Simplify the Boolean functions for FF inputs.

• Draw the circuit.

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Example: 3-bit Up-Counter using T FF

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Summary

• How to design a register?

• What is a shift register?

• How to design a ripple counter?

• How to design a synchronous counter?

• What is the difference between ripple counter and synchronous counter?

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Homework 6

• 6.6

• 6.7

• 6.12

• 6.17

• 6.23

• 6.24

• 6.26

• 6.28

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