Lecture-1 Number Systemssajid.buet.ac.bd/courses/EEE_303_2020/Lecture_2-3.pdf · 2/26/20 1...

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Lecture-1Number Systems

Dr. Sajid Muhaimin ChoudhuryDept of EEE, BUET

EEE 303 – Digital Electronics

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There are 10 kinds of people in this world:

© Dr. S. M. Choudhury, EEE, BUET. Please do not redistribute without prior permission

Those who understand binary, and those who don’t.

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Number system: DecimalDecimal: Deca (ten)

Each subsequent digit a multiplier of 10

Base: 10

Symbols:0123456789

7651107650

765

1N/10 Q R


765/10 76 5

76/10 7 67/10 0 7

7 6 5 1|102/26/20 3

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61.255✕10-22✕10-11✕1006✕101

1✕100

© Dr. S. M. Choudhury, EEE, BUET. Please do not redistribute without prior permission2/26/20 4

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Number of Fingers


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Number system: Binary

Binary: Bi (two)Each subsequent digit a multiplier of 2Base: 2

Symbols:01, TF


N/2 Q R13/2 6 1

6/2 3 03/2 1 11/2 0 1

13|10 = 1101|2

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Base-n Number system

• The system uses n different symbols• Each subsequent digit: n-times • For this course we denote a number, N with it’s base as N|n, n is denoted in decimal

• For n<10, we use symbols as 0-9, and for n>10 we use symbols as ABCD…


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Base-8 and Base-16

• Base-8• Octal• Symbols: 01234567

• Base-16• Hexadecimal• Symbols: 0123456789ABCDEF

• F|16 = 15|10


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Base conversion from Decimal

230/8 28 328/8 3 13/8 0 3


N/8 Q R

230|10

230|10 = 313|8

Octal

230/16 14 314/16 0 14(E)

N/16 Q R

230|10 = E3|16 = E3H

Hexadecimal

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Base conversion to Decimal

0 ✕ 80 = 03 ✕ 81 = 242 ✕ 82 = 128


230|8

230|8 = 152|10

Octal Hexadecimal

152

4 ✕ 160 = 415 ✕ 161 = 2401 ✕ 162 = 256

1F4|16

1F4|16 = 500|10

500

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Table of ValuesDec Bin Oct Hex

0 0000 0 0

1 0001 1 1

2 0010 2 2

3 0011 3 3

4 0100 4 4

5 0101 5 5

6 0110 6 6

7 0111 7 7

8 1000 10 8

9 1001 11 9

10 1010 12 A

11 1011 13 B

12 1100 14 C

13 1101 15 D

14 1110 16 E

15 1111 17 F© Dr. S. M. Choudhury, EEE, BUET. Please do

not redistribute without prior permission

10|8 = 001 000|2

11|8 = 001 001|2

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For Oct, each digit represents 3 bits, and for Hex each digit represent 4 bits. Can be used to compactly visualize digital data


001101010|2

001 101 010|2 = 152|81 5 2

0110 1010|2 = 6A|86 A

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Binary Addition, Subtraction, Multiplication and Division


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Signed number

• A signed binary number consists of both sign and magnitude information.

• Three formats:• sign-magnitude• 1’s complement• 2’s complement.


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Signed Number

• Sign-Magnitude Format

• 1’s Complement Format


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• 2’s Complement Format• 1’s Complement + 1


+10 1 0 0 1 1 1 0

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Floating Point Number

• Binary floating point number


mantissa exponent

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• Single Precision Representation


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Binary Codes

• Binary Coded Decimal (BCD)• Grey Code• Hamming Code


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Grey Code


exhibits only a single bit change from one code word to the next in sequence

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ASCII


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Hardware Description Languages

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Hardware Description Language

• Describes structure and behaviorof electronic circuits

• Two most popular HDL are Verilog and VHDL


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Verilog vs VHDLVerilog VHDLMore “C” like Non “C” like. Ada basedPartially deterministic Very deterministicLow verbosity High verbosityWeakly typed Strongly typedASIC Design FPGA DesignMore common in large firms

More common in hobbistcommunity

Standardized by Cadence Developed by US DOD


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Verilog Compiler Suite

• Proprietary:

• Open Source:


• Expensive or free with limitation

• Device support• Vendor locking

• Free to use (commercially and university wide)

• Community support• No Vendor locking

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Intel Quartus


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• Install the Intel Quartus Prime Lite edition from the website: https://fpgasoftware.intel.com/?edition=lite

• Version I am using here is 18.1(Please use the version that is shown in your lab sheet)


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Click on new Project


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https://fpgasoftware.intel.com/?edition=lite

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Click through the steps


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Select Device (please consult your labsheet for details)


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[Important!] Select the tools for simulating the code


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Click Finish


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Click New, and select Verilog HDL file


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Code for the Verilog file


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Save the file and click “StartCompilation”


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On the left side, you can see the compilation progress


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After compilation, click File>New and select “VWF” file


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The VWF editor will open


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Click Edit>Grid Size, set Period to 1us


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Click Edit>Set End Time, set End Time to 16us


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Right Click on the “Name” region and select “Insert Node or Bus”


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Click List, select d and press >, again select q and press >


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Click and select d, and right click on the waveform. Click “Value”>”Count Value”


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Set Count every 1us, and click okay


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Input of the circuit is created. Now click on Run Functional Simulation


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Simulation result is shown. The code converts input into 2’s complement


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Lecture-1 Number Systemssajid.buet.ac.bd/courses/EEE_303_2020/Lecture_2-3.pdf · 2/26/20 1...

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Transcript of Lecture-1 Number Systemssajid.buet.ac.bd/courses/EEE_303_2020/Lecture_2-3.pdf · 2/26/20 1...