Lect2 up300 (100328)
Transcript of Lect2 up300 (100328)
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 300 – LOW VOLTAGE OP AMPSLECTURE ORGANIZATION
Outline• Introduction• Low voltage input stages• Low voltage gain stages• Low voltage bias circuits• Low voltage op amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 415-432
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONImplications of Low-Voltage, Strong-Inversion Operation• Reduced power supply means decreased dynamic range• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reversebiased.
• Large values of currents and W/L ratios to get high transconductance• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range• Switches will require charge pumps
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-3
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Limits of Power Supply?The limit comes when there is no signal range left when the dc drops are subtracted fromVDD.
Minimum power supply (no signal swing range):
VDD(min.) = VT + 2VON
For differential amplifiers, the minimum powersupply is:
VDD(min.) = 3VON
However, to have any input common mode range, theeffective minimum power supply is,
VDD(min.) = VT + 2VON
060802-01
VDD
VPB1
VNB1
M1
M2 M3
M4
+
−
VON
VT+VON
+
−
+
−VT+VON
VON+
−
060802-02
VPB1
VDD
VNB1
+
−VON
+
−VON
+
−
VON +
−VT+VON
+
−VT+VON
M1 M2
M3 M4
M5
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Minimum Power Supply Limit – ContinuedThe previous consideration of the differential amplifier did not consider getting the signalout of the amplifier. This will add another VON.
060802-03
VPB1
VDD
VNB1
+
−VON
+
−VON
+
−
VON +
−VT+VON
+
−VT+VON
M1 M2
M3 M4
M5
VPB1
VPB2M6
M7 M8
M9
+
−VON
VT+VON+
−
VT
Therefore,VDD(min.) = VT + 3VON
This could be reduced to 3VON with the floating battery but its implementation probablyrequires more than 3VON of power supply.
Note the output signal swing is VT + VON while the input common range is VON.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-5
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE INPUT STAGESInput Common Mode Voltage RangeMinimum power supply (ICMR = 0):
VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat) = VSD3(sat)+VDS1(sat)+VDS5(sat)
Input common-mode range:Vicm(upper) = VDD - VSD3(sat) + VT1
Vicm(lower) = VDS5(sat) + VGS1
If the threshold magnitudes are 0.7V, VDD =1.5V and the saturation voltages are 0.3V, then
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V
and Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.
vicm M1 M2
M3 M4
M5
VDD
VDS5(sat)VBias
+
-
VBias+
-
VGS1
-VT1
VSD3(sat)
Fig. 7.6-3
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Increasing ICMR using Parallel Input StagesTurn-on voltage for the n-channel input:
Vonn = VDSN5(sat) + VGSN1Turn-on voltage for the p-channel input:
Vonp = VDD - VSDP5(sat) - VSGP1The sum of Vonn and Vonp equals the minimumpower supply.
Regions of operation:VDD > Vicm > Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp Vicm Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn > Vicm > 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN isthe input transconductance for the n-channel input and gmP is the input trans-conductance for the p-channel input.
VDD
MN1 MN2MP1 MP2
MP3MP4
MP5MN3MN4
MN5
IBias
M6
M7
Fig. 7.6-4
Vicm Vicm
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD
gmN+gmP
gmNgmP
gm(eff)
Vicm
n-channel onn-channel off n-channel onp-channel onp-channel on p-channel off
Fig. 7.6-5
Vonn Vonp
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Removing the Nonlinearity in Transconductances as a Function of ICMRIncrease the bias current in the differentialamplifier that is on when the otherdifferential amplifier is off.
Three regions of operation depending on thevalue of Vicm:
1.) Vicm < Vonn: n-channel diff. amp. offand p-channel on with Ip = 4Ib:
gm(eff) = KP’W P
LP 2 Ib
2.) Vonn < Vicm < Vonp: both on with
In = Ip = Ib:
gm(eff) = KN’W N
LN Ib +
KP’W PLP
Ib
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
gm(eff) = KN’W N
LN 2 Ib
VDD
Ib
Ib1:3
3:1
MN1
MP1 MP2
MN2MB2 MB1
VB2 VB1
Inn
Ipp
Ip
In
VicmVicm
Fig. 7.6-6
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-8
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does the Current Compensation Work?Set VB1 = Vonn and VB2 = Vonp.
VonnMN1 MN2
MB1vicmvicm
IppIn
IbIf vicm >Vonn then In = Ib and Ipp=0
If vicm <Vonn then In = 0 and Ipp=Ib
VDD
Vonp
MP1 MP2
MB2vicmvicm
Inn Ip
IbIf vicm <Vonp then Ip = Ib and Inn=0
If vicm >Vonp then Ip = 0 and Inn=Ib
Fig. 7.6-6A
Result:gm(eff)
Vonn Vonp VDD
Vicm00
gmN=gmP
Fig. 7.6-7
The above techniques and many similar ones are good for power supply values down toabout 1.5V. Below that, different techniques must be used or the technology must bemodified (natural devices).
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Natural TransistorsNatural or native NMOS transistors normally have a threshold voltage around 0.1Vbefore the threshold is increased by increasing the p concentration in the channel.If these transistors are characterized, then they provide a means of achieving low voltageoperation.Minimum power supply (ICMR = 0):
VDD(min) = 3VON
Input common mode range:Vicm(upper) = VDD – VON + VT(natural)
Vicm(lower) = 2VON + VT(natural)
If VT(natural) VON = 0.1V, then
Vicm(upper) = VDD
Vicm(lower) = 3VON = 0.3V
Therefore,
ICMR = VDD - 3VON = VDD – 0.3V VDD(min) 1V
Matching tends to be better (less doping and magnitude is smaller).
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Driven MOSFETA depletion device would permit large ICMR even with very small power supply voltagesbecause VGS is zero or negative.When a MOSFET is driven from the bulk with the gate held constant, it acts like adepletion transistor.Cross-section of an n-channelbulk-driven MOSFET:
Large signal equation:
iD = KN’W
2L VGS - VT0 - 2| F| - vBS + 2| F| 2
Small-signal transconductance:
gmbs = (2KN’W/L)ID
2 2| F| - VBS
����
p-well
n+
����n+
����n+
����p+ Channel
����������������
QP
QV
Bulk Drain Gate Source Substrate
VDDVGSVDSvBS
DepletionRegion
n substrateFig. 7.6-8
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Driven MOSFET - ContinuedTransconductance characteristics:
Saturation: VDS > VBS – VP gives,
VBS = VP + VON
iD = IDSS 1 -VBSVP
2
Comments:• gm (bulk) > gm(gate) if VBS > 0
(forward biased )• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET• Very useful for generation of IDSS floating current sources.
0
500
1000
1500
2000
-3 -2 -1 0 1 2 3
Dra
in C
urre
nt (μ
A)
Gate-Source or Bulk-Source Voltage (Volts)
IDSS
Bulk-source driven
Gate-sourcedriven
Fig. 7.6-9
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Bulk-Driven, n-channel Differential AmplifierWhat is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
As Vicm increases, the current throughM1 and M2 is constant so the sourceincreases. However, the gate voltage staysconstant so that VGS1 decreases. Since thecurrent must remain constant through M1and M2 because of M5, the bulk-sourcevoltage becomes less negative causing VTN1to decrease and maintain the currentsthrough M1 and M2 constant. If Vicm isincreased sufficiently, the bulk-sourcevoltage will become positive. However,current does not start to flow until VBS isgreater than 0.3 volts so the effectiveVicm(max) is
Vicm(max) VDD - VSD3(sat) - VDS1(sat) + VBS1.
VDD
VSS
M1 M2
M3 M4
M5M6
M7
IBiasvi1 vi2
Fig. 7.6-10
+ VBS1-
+ VBS2-
+ VGS-
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the ICMR of the Bulk-Driven, Differential Amplifier
-50nA
0
50nA
100nA
150nA
Bul
k-So
urce
Cur
rent
Input Common-Mode Voltage-0.50V -0.25V 0.00V 0.25V 0.50V
200nA
250nA
Fig. 7.6-10A
Comments:• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMRwhich makes it very difficult to compensate
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Reduction of VT through Forward Biasing the Bulk-Source
The bulk can be used to reduce the threshold sufficiently to permit low voltageapplications. The key is to control the amount of forward bias of the bulk-source.Current-Driven Bulk Technique†:
IBB
S
G
D
B
IBB
S
G
D
BIE
ICD ICS
Reduced Threshold MOSFET Parasitic BJT
n-well
p+ p+
n+
����
Source Drain
Gate
p- substrateLayout Fig. 7.6-19
Problem:Want to limit the BJT current to some value called, Imax.Therefore,
IBB = Imax
CS + CD + 1
† T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Current-Driven Bulk TechniqueBias circuit for keeping the Imax definedindependent of BJT betas.
Note:ID,C = ICD + IDIS,E = ID + IE + IR
The circuit feedback causes a bulk biascurrent IBB and hence a bias voltage VBIASsuch that
IS,E = ID + IBB(1+ CS + CD) + IRUse VBias1 and VBias2 to set ID,C 1.1ID,IS,E 1.3ID and IR 0.1ID which sets IBB at 0.1ID assuming we can neglect ICS withrespect to ICD.
For this circuit to work, the following conditions must be satisfied:VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
M1 M2
M3
M4M5
M6
M7
VDD
VSS
VBias1
M8
VBias2VBias
IBB
IS,E
ID,C
Fig. 7.6-20
R
IR
+
-
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-16
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE GAIN STAGESCascade StagesSimple cascade of inverters:
060803-01
VDD
VPB1
VNB1
M1
M2 M3
M4
VPB1
M6
M5
VNB1
M7
M8
-gm1
R1
-gm2
R2
-gm3
R3
-gm4
R4
The problem with this approach is the number of poles that occur (one per stage) if theamplifier is to be used in a closed loop application.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Nested Miller CompensationPrinciple: Use Miller compensationto split the poles within a feedbackloop.Compensating Results:1) Cm1 pushes p4 to higherfrequencies and p3 down to lowerfrequencies2) Cm2 pushes p2 to higherfrequencies and p1 down to lower frequencies
3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lowerfrequenciesEquations:
GB gm1/C m3 p2 gm2/Cm3 p3 gm3Cm3/(Cm1Cm2) p4 gm4/CL
The objective is to get all poles larger than GB:GB < p2, p3, p4
060812-01
vinvout-gm3-gm2-gm1 -gm4
Cm3
Cm1Cm2
p1 p2 p3 p4
R2R1 R3 RL CL
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of the Nested Miller Compensation Technique
jω
σp4 p3 p2 p1
jω
σp4 p3 p2 p1
jω
σp4 p3p2 p1
jω
σp4 p3 p2 p1
Cm1
Cm2
Cm3
070508-01-GB
This approach is complicated by the feedforward paths which create RHP zeros.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Elimination of the RHP ZerosThe following are least three ways in which the RHP zeros can be eliminated.
1.) Nulling resistor.
060803-02
VDD
VPB1
Rz1
Cc1M2
M1
z1 = 1
Cc1(1/gm1 Rz1)
2.) Feedback only – buffer.
060803-03
VDD
VPB1
Cc1
M2
M1VPN1
VDD
M3
Increases the minimum powersupply by VON.
3.) Feedback only – gain.
060803-04
VDD
VPB1
Cc1M2
M1
VDD
VPB2
VNB1
M3
M4
M5
Increases the pole andincreases the minimumpower supply by VON.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of LHP Zeros to Compensate Cascaded AmplifiersPrinciple: Feedforward around a noninverting stage creates a LHP zero or invertingfeedforward around an inverting stage also creates a LHP zero.Example of Multipath, Nested Miller Compensation†:
060803-05
R3
+gm4
VoutVin
C3
+gm2+gm1
R1
-gm3
R2,4
M1 M2M3 M4
CM1
CM2
M8
VNB1
M7
VDD
VPB1M5 M6
VRef1M12
M11
VRef2
M14
Vout
C3Vin
M9 M10
M13
CM1CM2
Unfortunately, the analysis becomes quite complex - for the details refer to the referencebelow.
† R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publishers, 1996, pp. 127-131.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-21
CMOS Analog Circuit Design © P.E. Allen - 2010
CascodingPossibilities that trade off output resistance and headroom:
051205-01
VGG
ID
+
−vout
Rout
No Cascoding
VGG
ID
+
−
vout
Rout
Normal Cascoding
M1
M2Sat.
Sat.
VT+2Von
VGG
ID
+
−
vout
Rout
Reduced Headroom Cascoding
M1
M2Sat.
Act.
VT+2Von
VGG
ID
+
−
vout
Rout
Gate-Connected Cascode
M1
M2Sat.
Act.
NoCascode
NormalCascode
Reduced HeadroomCascode
Gate-ConnectedCascode
voutVon1 1
1 + ß1ß2 1 +
ß1ß2 (2x-x2) 2x +
ß1ß2 (2x-x2)
Routrds
1 2ß22ID
2ß2(x-0.5x2)
ß1(1-x) + ID x-0.5x2 2ß2(x-0.5x2)
ß1(1-x) + ID x-0.5x2
Note: vDS(active) = x·Von1 = x·(VGG–VT)x = 0.1 and ß2 = 9ß1 vout=1.145Von1 and Rout=1.45rds for reduced headroom cascode
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Solutions to the Low Headroom Problem – High Voltage Tolerant CircuitsHigh voltage tolerant transistors in standard CMOS†:
050416-02
Thick oxidetransistor Thick oxide
cascode
VDD(nom.)
VDD(nom.)
Upper gateswitchedto highestpotential
Retractable cascodecomposite transistor
(Transistor symbols with additional separation between the gate line and the channel linerepresent thick oxide transistors.)
† Anne-Johan Annema, et. Al., “5.5-V I/O in a 2.5-V 0.25μm CMOS Technology,” IEEE J. of Solid-State Circuits, Vol. 36, No. 3, March 2001, pp.
528-538.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-23
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE BIAS CIRCUITSA Low-Voltage Current Mirror with Wide Input and Output SwingsThe current mirror below requires a power supply of VT+3VON and has a Vin(min) =VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
iin
M1 M2
M3
VDD
IB
M4
M5
M6
M7
iout
I1-IB IB I2
or
iin
M1
M2
M3
VDD
IB1
M4
M5M6
M7
iout
I1 IB2 I2IB1
IB2
Fig. 7.6-13A
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Low-Voltage Current Mirrors using the Bulk-Driven MOSFETThe biggest problem with current mirrors is the large minimum input voltage required forpreviously examined current mirrors.If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it isenhancement and can be used as a current mirror.
VDD
iin
iout
M1 M2
+
-VGS
+-
VBS+
-VGS
VDD
iin iout
M1 M2
+
-VGS1
+-
VBS1+
-VGS2
M3 M4
Simple bulk-driven current mirror
Cascodebulk-driven current mirror. Fig.7.6-11
+-
VBS3+
-VGS3
+-
VGS4
The cascode current mirror gives a minimum input voltage of less than 0.5V for currentsless than 100μA
0
1 10-5
2 10-5
3 10-5
4 10-5
5 10-5
6 10-5
0 0.2 0.4 0.6 0.8 1
Cascode Current MirrorAll W/L's = 200μm/4μm
Iout
(A
)
Vout (V)
Iin=50μA
Iin=40μA
Iin=30μA
Iin=20μA
Iin=10μA
2μm CMOS
Fig. 7.6-12
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Bandgap Topologies Compatible with Low Voltage Power Supply
VPTAT
VBE
IPTAT
VRef
VDD
Voltage-mode bandgap topology.
INL
VRef
VDD
IVBE
VDD
IPTAT
VDD
Current-mode bandgap topology.
VRef
VDD
IPTAT
VDDVDD
INL
IVBE
R2
R3
R1
Voltage-current mode bandgap topologyFig. 7.6-14
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Technique for Canceling the Bandgap CurvatureVDD
M1 M2 M3 M4
IVBE K1IPTAT
1:K2 1:K3
I2 INLK3INL
Cur
rent K2IVBE K1IPTAT
Temperature
INL
M2 activeM3 off
M2 sat.M3 on
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.Fig. 7.6-16
INL = 0
K1IPTAT - K2IVBE ,,
K2IVBE > K1IPTAT
K2IVBE < K1IPTAT
The combination of the above concept with the previous slide yielded a curvature-corrected bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C° usinga 1.1V power supply.† In addition, the line regulation was 408 ppm/V for 1.2 VDD 10Vand 2000 ppm/V for 1.1 VDD 10V. The quiescent current was 14μA.
† G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-27
CMOS Analog Circuit Design © P.E. Allen - 2010
LOW VOLTAGE OP AMPSA Low Voltage Op Amp using Normal TechnologyVDD(min) = 3VON + VT (ICMR = VON):
060804-01
VDD
VPB1
VNB1
VPB2
vIN+
−
vOUTM1 M2
M3 M4
M5
M6 M7
M8 M9 M10
M11
Cc
Performance:Gain gm
2rds2
Miller compensatedOutput swing is VDD -2VONMax. CM input = VDD
Min. CM input = 2VON + VT
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-28
CMOS Analog Circuit Design © P.E. Allen - 2010
A Low-Voltage, Wide ICMR Op AmpVDD(min) = 4VON + 2VT (ICMR = VDD):
3:1
1:3
041231-15
VDD
VDD-VT-VDS(sat)
VDD-VT-2VDS(sat)+ −
VT+VDS(sat)
VT+2VDS(sat)
vOUT
Performance:
Gain gm2rds
2, self compensated, and output swing is VDD -4VON
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-29
CMOS Analog Circuit Design © P.E. Allen - 2010
An Alternate Low-Voltage, Wide ICMR Op AmpVDD(min) = 4VON + 2VT (ICMR = VDD):
3:1
1:3060804-02
VDD
+ − vOUT
VPB2
VPB1
VPB2
VNB2
VNB1
VNB2
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-30
CMOS Analog Circuit Design © P.E. Allen - 2010
A 1-Volt, Two-Stage Op AmpUses a bulk-driven differential input amplifier.
vin+
vout
VDD=1V
IBias
Cc=30pF
CL
Rz=1kΩ
vin-
M1 M2
M3 M4Q5 Q6
M7
M8 M9 M10 M11M12
2000/2
400/2 400/2 400/2
6000/6 6000/6 3000/6 6000/6
Fig. 7.6-18
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Performance of the 1-Volt, Two-Stage Op AmpSpecification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)Power supply current 300μAUnity-gainbandwidth (GB) 1.3MHz (Vicm mid range)Phase margin 57° (Vicm mid range)Input offset voltage ±3mVInput common mode voltage range -0.475V to 0.450VOutput swing -0.475V to 0.491VPositive slew rate +0.7V/μsecNegative slew rate -1.6V/μsecTHD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,81nV/ Hz @ 100kHz444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHzNegative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-32
CMOS Analog Circuit Design © P.E. Allen - 2010
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique
-
+vin M1 M2
M3 M4M5
M6
M7
vout
VDD
VSS
VBiasN
Cx
CL
VBiasP
M8
M9 M10
M11 M12
M13
M14M15
M16
M17
Fig. 7.6-21
Transistors with forward-biased bulks are in a shaded box.For large common mode input changes, Cx, is necessary to avoid slewing in the inputstage.To get more voltage headroom at the output, the transistors of the cascode mirror havetheir bulks current driven.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-33
CMOS Analog Circuit Design © P.E. Allen - 2010
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -ContinuedExperimental results:
0.5μm CMOS, 40μA total bias current (Cx = 10pF)Supply Voltage 1.0V 0.8V 0.7V
Common-mode inputrange
0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
High gain output range 0.35V-0.75V 0.25V-0.5V 0.2V-0.4VOutput saturation limits 0.1V-0.9V 0.15V-0.65V 0.1V-0.6V
DC gain 62dB-69dB 46dB-53dB 33dB-36dBGain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate (CL=20pF) 0.5V/μs 0.4V/μs 0.1V/μsPhase margin (CL=20pF) 57° 54° 48°
The nominal value of bulk current is 10nA gives a 10% increase in differential pairquiescent current assuming a BJT of 100.
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-34
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT 0.1V)
- Drive the bulk terminal- Forward bias the bulk- Use depeletion devices
• The dynamic range will be compressed if the noise is not also reduced• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology