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BJT AC ANALYSIS BJT AC ANALYSIS BJT AC ANALYSIS BJT AC ANALYSIS

Semester II 2010/11Semester II 2010/11Semester II 2010/11Semester II 2010/11

BJT AC ANALYSIS BJT AC ANALYSIS BJT AC ANALYSIS BJT AC ANALYSIS

(COMMON EMITTER AMPLIFIERS (COMMON EMITTER AMPLIFIERS (COMMON EMITTER AMPLIFIERS (COMMON EMITTER AMPLIFIERS AC LOADLINE)AC LOADLINE)AC LOADLINE)AC LOADLINE)

School of Microelectronic Engineering School of Microelectronic Engineering School of Microelectronic Engineering School of Microelectronic Engineering

((((SoMeSoMeSoMeSoMe) ) ) )

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AC LOAD LINE ANALYSIS

R1RC

VCC vO

RS

RC RL

NoteNoteNoteNote: The DC & AC load line analysis will be based on these circuits

RS

R1

R2 RE

RL

vs

vO

CC1

CC2 vs R1 || R2RE

RL

Common-emitter amplifier with emitter resistor

AC equivalent circuit

AC LOAD LINE ANALYSIS - DC Load Line

•KVL at C-E loop

ECCCCE

EECCCECC

RIRIV

RIRIVV

+

+++=

++=

1

1

β

β

β

DC Load Line

EC

ECCQCEQCC

ECCQCEQCC

RR

RRIVV

RRIVV

+=

+=−

++=

≅+

1- Slope

)(

)(

11 assume point, -QFor

β

β

AC LOAD LINE ANALYSIS - AC Load Line

AC Load Line

DC Load Line

Common-Emitter Amplifier with Emitter Bypass Capacitor

RS

R1RC

vO

VCC

Emitter bypass capacitor, CEmitter bypass capacitor, CEmitter bypass capacitor, CEmitter bypass capacitor, CEEEE

provides a provides a provides a provides a short circuitshort circuitshort circuitshort circuit to to to to ground for the ac signalsground for the ac signalsground for the ac signalsground for the ac signals

R2 RE

vs

CC

CE

Vo

Vs RC

RS

rπ roR1|| R2 gmVπSmallSmallSmallSmall----signal signal signal signal hybridhybridhybridhybrid----ππππequivalent circuitequivalent circuitequivalent circuitequivalent circuit

Note: Calculation examples in Neamen (Example 6.7)

Common-Emitter Amplifier with Emitter Bypass Capacitor

By include RE, it provide stability of Q-point.

If RE is too high +++> small-signal voltage gain will be reduced severely. (see Av equation)

Thus, RE is split to RE1 & RE2 and the second resistor is bypassedwith “emitter bypass capacitor”. CE provides a short circuit to ground for ac signal.

So, only RE1 is a part of ac equivalent circuit.

For dc stability: RE=RE1+RE2 For ac gain stability: RE=RE1 since CE will short RE2 to ground.

AC LOAD LINE ANALYSIS

NoteNoteNoteNote: The next DC & AC load line analysis will be

CommonCommonCommonCommon----emitteremitteremitteremitter amplifier with emitter bypass capacitoramplifier with emitter bypass capacitoramplifier with emitter bypass capacitoramplifier with emitter bypass capacitor

analysis will be based on this circuit

AC LOAD LINE ANALYSIS - DC Load Line

KVL on C-E loop

21

21

1 when ,)(

1

)(

CEEECCECC

EEECECC

IIVRRIVRI

VRRIVRIV

+=++

+++=

++++=

−

−+

β

β

β

β

21

21

21

1 Slope

)( So,

11

1, when point,-QFor

)(1

EEC

EECCQCEQ

EECCCCE

RRR

-

RRRIVVV

RRIRIVVV

++=

+++=−−+

≅

+>>

+

+++=−

−+

β

ββ

β

β

AC LOAD LINE ANALYSIS - AC Load Line

KVL on C-E loop

1

Assuming

0

ec

EeceCc

ii

RivRi

≅

=++

1

11

1- Slope

)(

EC

ECcEcCcce

RR

RRiRiRiv

+=

+−=+−=

AC equivalent circuit

NoteNoteNoteNote: The plot for DC & AC load line for this circuit is in Neamen (Figure 6.42)

Maximum Symmetrical Swing

When symmetrical sinusoidal signal applied to the input of an amplifier, the output generated is also a symmetrical sinusoidal signal

AC load line is used to determine maximum AC load line is used to determine maximum output symmetrical swing

If output is out of limit, portion of the output signal will be clipped & signal distortion will occur

Maximum Symmetrical Swing

Steps to design a BJT amplifier for maximum symmetrical swing

Write DC load line equation (relates of ICQ & VCEQ)

Write AC load line equation (relates ic, vce; vce = -icReq, Req = effective ac resistance in C-E circuit)icReq, Req = effective ac resistance in C-E circuit)

Generally, ic = ICQ – IC(min), where IC(min) = 0 or some other specified min collector current

Generally, vce = VCEQ – VCE(min), where VCE(min) is some specified min C-E voltage

Combination of the above equations produce optimum ICQ & VCEQ values to obtain maximum symmetrical swing in output signal

Maximum Symmetrical Swing

Example:Determine the maximum symmetrical swing in the output voltage of the circuit given in Figure 6.43 (Neamen) (Note: RC = 5 kΩ, RL = 2 kΩ)

Solution: Solution:

Calculate the values or draw the dc load line. Calculate the values or draw the ac load line (resulting plot in Figure 6.44).

From the dc & ac load line, the maximum negative swing in the Ic is from 0.894 mA to zero (ICQ).

Maximum Symmetrical Swing

Example (cont)

So, the max possible peak-to-peak ac collector current:

mA 79.1)894.0(2

(min)),(2

==

−=∆ CCQc IIi

The max. symmetrical peak-to-peak output voltage:

Max instantaneous collector current:

V 56.2)2||5)(79.1()||(||

||||

==∆=

∆=∆

LCc

eqcce

RRi

Riv

mA 79.1894.0894.0||2

1=+=∆+= cCQC iIi