With advances in technology scaling, CMOS circuits are

increasingly more sensitive to transient pulses caused by

single event (SE) particles.

The reduced nodal capacitances, supply voltages and

transistor drive currents coupled with more dense chips are

increasing soft error rates and making them an important

design issue.

Effect of Power Optimizations on Soft Errors

Another important issue a circuit designer faces today is

the increasing power consumption. As technology scaling

continues, the leakage or static power consumption of a

circuit increases.

In order to reduce power consumption in chips, one

common approach has been the scaling of the

power supply voltage. This should be accompanied

by threshold voltage reduction in order to keep

circuit speed and high current drive to avoid

performance penalties.

However, the threshold voltage reduction results in

great amount of increase on the sub-threshold leakage sub-threshold leakage

current current

Subthreshold leakage is the current that flows between the

source and drain of a MOSFET when the transistor is in

subthreshold region, or weak-inversion region ( for gate-to-

source voltages below the threshold voltage)

The transistor in this region is not completely turned

OFFOFF. Instead, a small current still flows between the

source and drain terminals.

Dynamic power dissipation resulting from continuous

switching of transistors and charging and discharging of

capacitances, previously contributed the most to the total

chip’s power dissipation in CMOS digital circuits thus

most efforts were devoted towards reducing it.

LEAKAGE (STATIC) POWER

Load cap. Consists of diffusion capacitance of the drains of the inverter transistors, the total interconnect capacitance, and the input gate oxide capacitance of the driven gates that are connected to the inverter's output.

Dynamic power dissipation

The average dynamic power dissipation of the

inverter can be calculated from the energy

required to charge up the output node to VDD and

discharge the total output load capacitance to

ground (GND). The generalized expression for the

switching power dissipation of a CMOS logic gate

can be written

Pavg = αT Cload VDD 2 fCLK;

αT is the switching activity factor of the gate

But as technology advances into the sub-100nm

regime, leakage power dissipation, which is a static

power, increases at a much faster rate than dynamic

power and it is expected to dominate the chips’ total

power dissipation.

But as technology advances into the sub-100 nmregime, leakage power dissipation increases in a much faster rate than dynamic power.

we started to see these effects with DSM technology

Leakage power is static power dissipation and can be described as the power that is dissipated through transistors without producing any useful outcome.

For example, even if the gate voltage of a transistor is lower than the threshold voltage required to turn it ON, the transistor is not completely off and a small current still flows causing what is known as sub-threshold leakage current.

The second term corresponds to the static power

dissipation where Ileak corresponds to the

total static leakage current.

Total power dissipation then can be written as:

The active and leakage power

trends for process technologies

Since leakage power dissipation is approaching 40%

of today’s high performance microprocessors total

power dissipation, new techniques and new

technology innovations are urgently needed to

reduce leakage current components.

The continuous scaling down of technology minimum

feature size increases the Short Channel Effects.

A MOSFET device is considered to be short when

the channel length is the same order of magnitude

as the depletion-layer widths (xdD, xdS) of the

source and drain junction.

In short channel devices source and drain depletion

regions penetrate significantly into the channel and

control the potential and the field inside the channel.

This is known as the short channel effect

Due to the short channel effect, Vth reduces with

reduction in channel length (Vth roll off), and with an with an

increase in the drain biasincrease in the drain bias (Drain Induced Barrier

Lowering (DIBL))

If the drain voltage is increased, the potential barrier in

the channel decreases, leading to drain-induced barrier

lowering (DIBL).

The reduction of the potential barrier eventually allows

electron flow between the source and the drain, even if even if

the gate-to-source voltage is lower than the threshold

voltage..

The channel current that flows under this conditions

(VGS<VT) is called the sub-threshold currentsub-threshold current.

To effectively control channel, reducing gate oxide

thickness tox helps in controlling Short Channel Effects,

but the reduction in tox results also in higher gate leakage

current.

Large leakage power can lead to dramatic effects thatmay cause circuits to fail to function properly. Large leakage currents will:

■ Degrade noise immunity in dynamic circuits which may lead to circuit failure.

■ Increase the standby power dissipation to unacceptable levels.

■ Lead to excessive heating which may make components susceptible to failure and, as stated above, will consequently require complicated cooling and packaging techniques.

Even they affect IDDQ testing

Leakage current is also an important factor in setting total supply current (IDDQ) value, which is used as a

pass/fail threshold for testing chips.

IDDQ value is now determined by the sum of leakage

currents of those transistors that can leak.

Setting this value too high would cause some defective

chips to be considered non-defective; similarly if this

value is set too low, functional chips may be considered

defective.

Effect of Channel Length

In short channel transistors, the drain and source depletion

regions are in a near proximity of each other. They enter

more into the channel length and as a result part of the

channel gets depleted.

Consequently, less gate voltage is needed to turn the

transistor on. This means that the threshold voltage is lower

for the short channel transistor and sub-threshold current is

higher.

Equation shows the various parameters that affect the threshold voltage of a transistor such as doping densities, source to substrate bias, and some other process parameters:

Vth0 is the zero-bias threshold voltage and depends on

the manufacturing process,

γ is the body effect coefficient (typically equals to 0.4 V0.5) and it depends on the gate oxide capacitance, silicon permittivity, doping.

φF is the surface potential at threshold (typically |− 2φF | equals 0.6 V);

VSB is the source-to-body voltage;

ηVDS and the term represents the effect of Drain-

Induced Barrier Lowering (DIBL)

η is the DIBL coefficient and it is in the range of 0.02–0.1

Body bias:

Increasing the source-to-body biasing results in increasing the transistor’s threshold voltage as indicated by equation below and this effect is known as the Body Bias effect

Vth = Vth0 + γ |2φF| + VSB − |2φF | −

ηVDSand hence it reduces the sub-threshold leakage

current.

The increasing use of portable devices and higher demand

on battery life has made power consumption even more

important in today’s CMOS designs.

Subsequently, there have been several efforts spanning

from the circuit level to the architectural level at reducing the

consumed energy.

[1] L. Wei, K. Roy, and V. K. De. Low voltage low power CMOS design

techniques for deep submicron ICs. In VLSI Design, 2000. Thirteenth

International Conference on, pages 24-29, 2000.

[2] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current

mechanisms and leakage reduction techniques in deep-submicrometer CMOS

circuits”, Proceedings of the IEEE, 91(2):305-327, 2003.

Circuit mechanisms include adaptive substrate biasing,

dynamic supply scaling, dynamic frequency scaling, and

supply gating.

Circuit Level Leakage Reduction Techniques

Leakage reduction circuit techniques can be put into four categories :

A. Transistor stacking TechniquesB. Multi-Vth TechniquesC. Input Vector Control TechniquesD. Body Biasing Techniques

A.Transistor Stacking Techniques

All these techniques are based on the fact that when

there are two or more stacked transistors which are

switched OFF, we will have approximately an order of

magnitude lower subthreshold leakage.

Transistor stacking has a dual effect in reducing the

sub-threshold leakage current, it increases the source

bias of upper transistors in the stack and also lowers

the gate-to source voltages of these transistors,

A.Transistor Stacking Techniques

Reducing leakage through the use

of transistor stacks depends on the depends on the

choice of input pattern choice of input pattern during

standby periods since it determines

the number of OFF transistors in the

stack.

Serious connected ‘off’ Serious connected ‘off’ Transistors (Transistor Stacking) Transistors (Transistor Stacking) can reduce leakage current can reduce leakage current greatlygreatly

Leakage currents dependencies on circuit state canbe exploited and used to determine a low leakage state by searching the minimum leakage input vector, which is fed into the circuit during sleep mode

After this input vector is found, the circuit is evaluated and additional leakage control transistors are inserted in the non-critical paths where only one transistor is originally turned OFF.

B. Multi-Vth Techniques

This is one of the most common approaches to reduceleakage currents where two different types of transistorsare fabricated on the chip, a high-Vth to lower subthresholdleakage current and a low-Vth to enhance circuit performance by increasing its speed.

Obtaining two different sets of transistors each with either a low or a high is usually done by changing the channel doping profile, having two different oxide thicknesses, or by changing channel lengths

It is designed using an NMOS and a

PMOS transistor that have different

threshold voltages than the CMOS

logic circuit.

The CMOS logic circuit is designed

with low thresholds as usual to

ensure speed and performance.

The separate NMOS and PMOS transistors will have a high threshold voltage and will not suffer significant leakage currents.

These will be used to isolate the CMOS logic circuit by being placed in series with the CMOS structure and in essence will isolate the logic circuit in stand-by mode and prevent any significant leakage power.

the stand-by transistor design the stand-by transistor design creates a virtual power supply creates a virtual power supply and/or virtual ground.and/or virtual ground.

There are two families of the MTCMOS technique,the first family uses a high-Vth device to supplyvoltages TO a low-Vth logic block thus creating avirtual power rail instead of directly connecting the blockto the main power rail as shown.

The voltage continues scaling down with every generation, employing a high-a high-Vth Vth would not be practicalwould not be practical with supply voltages equal or lower than 0.7 V. Other techniques such as Super Cutoff CMOS (SCCMOS) provide a solution to this potential problem.

SCCMOS technique is another multi-Vth circuit technique used to reduce leakage currents.

In this technique, instead of using a high-Vth transistor to

provide the supply voltage, a low-Vth PMOS switch is

used whose gate is overdriven to VDD + 0.4 V through

the use of a MOS charge pump (to fully cut-off leakage)

The Super Cutoff CMOS (SCCMOS) technique

ALSO:

C. Input Vector Control Techniques

The basic idea behind input vector control techniques forleakage reduction is to force the circuits’ combinational logic into a low-leakage state during standby periods.

This low-leakage state forces the largest number possible of transistors to be turned OFF so as to reduce leakage and make use of multiple OFF transistors in stacks. Leakage current can be reduced to 10 times lower if input vector control is used

An alternative approach is to exploit transistor stacks

already embedded in the logic, by preferring to put each

gate in a low leakage state, for example, by inputting all

0’s for a NAND gate. Controlling each gate directly is

too expensive in terms of area and power, so typically

one wants to find an input vector (to a combinational

circuit) that minimizes total leakage current.

C. Input Vector Control Techniques contd. There are three main methods for selecting the required input vector:

(1) Analyzing the circuit and looking for a good inputvector;

(2) Employing an algorithm that searches forthe best input vector;

(3) Simulating the circuit with a large number of input test patterns and selecting the one that results in the lowest leakage power among these test patterns.

D. Body Biasing Techniques

A) Variable Threshold CMOS (VTCMOS)

To overcome subthreshold leakage, the threshold

voltage can be adjusted. This is accomplished by

changing the substrate-bias voltage as noticed in

Equation

In Variable Threshold CMOS (VTMOS)

technique, deep reverse body bias is applied during deep reverse body bias is applied during

standby, standby, a higher than VDD bias for PMOS transistors

and lower than GND bias for NMOS transistorslower than GND bias for NMOS transistors, to

further increase the threshold voltage and further push

the transistors in the OFF region to achieve lower

subthreshold leakage currents;

Body bias applied in the reverse bias regime, where threshold

voltage increases as body-to-source reverse bias is made

larger to reduce leakage.

1V

3V3V

-2V-2V

For controlling substrate

voltage, triple well technology

or SOI needed

-2V

3V

As mentioned earlier, whenever VDD is scaled to

reduce power consumption, it should be followed by

threshold voltage reduction in order to keep circuit

speed and high current drive to avoid performance

penalties.

However, the threshold voltage reduction results in

great amount of increase on the sub-threshold

leakage current

B) Dynamic Threshold MOS (DTMOS)B) Dynamic Threshold MOS (DTMOS)

.One solution to this problem is a dynamic threshold

(DTMOS) operation which applies an active body-bias to

MOSFETs

Technique applies a low threshold voltage during the

logic transition and high threshold voltage during the off-

state, the dynamic threshold circuit operates at high

speed with low power.

Dynamic threshold technique however can only be used

for low voltage (0.6 V and below) VLSI circuits.

In a Standard DTMOS logic gate, all transistors’ gates are

tied to their substrates

Namely, the body-source junction is “forward biased” (at less than

0.6 V), forcing the threshold voltage to drop.

0.6 V

Logic High

VSB=0-0.6= -0.6 V

NMOSNMOS threshold reduces while it

is switching which makes it faster

In comparison to VTCMOS, DTMOS operates in the

exact opposite regime.

0.6

0.6 V

Logic High

0 V

Logic LOW High threshold (normal

threshold applied to

OFF NMOS)

NMOS is ON. NMOS

threshold reduces via

body to source voltage.

negative

The high speed operation is provided by

forward bias to switching transistors, while

low leakage is obtained by applying zero

bias to other transistors

During switching, the body-source junction is “forward

biased” (at less than 0.6 V), forcing the threshold voltage

to drop.

PMOS gets 0 bias having low leakage while

NMOS gets a forward bias speeding up

All of these power optimizations AFFECT the susceptibility

of the circuits to soft errors. As circuit designers try to

address the excessive power consumption problem, they

need to be aware of the impact of the power optimizations

on circuit SE robustness.

This sort of analysis is important because it helps us in

making clever design choicesclever design choices that reduce static power

consumption and improve soft error reliability of the newer

designs.

There has been some work to examine the effect of

power optimizations on the soft errors.

Degalahal et al. have analyzed the effect of increasing effect of increasing

threshold voltagethreshold voltage (widely used for reducing static power

consumption) on circuit soft error rate (SER) and found

that increasing threshold voltages cause devices to devices to

slow downslow down which in turn increase CL circuit increase CL circuit

susceptibilitysusceptibility to Single Event transients.

V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "The

Effect of Threshold Voltages on the Soft Error Rate", 5th International

Symposium on Quality Electronic Design (ISQED'04), pp. 503-508, 2004.

For increasing CL soft error tolerance, Dhillon et al.

have proposed a technique that used optimal

assignment of gate sizes, supply voltages, and

threshold voltages while meeting timing constraint.

Y. S. Dhillon, A. U. Diril, A. Chatterjee, and A. D. Singh, “Analysis

and optimization of nanometer CMOS circuits for soft-error

tolerance,” in IEEE Trans. on Very Large Scale Integration (VLSI)

Systems, Vol. 14, No. 5, pp. 514-524, 2006.

Later work has presented a power-aware methodology for

soft error hardening using dual supply voltages. In this

methodology, a higher supply voltage is assigned to the

gates that have large error impact and contribute most to

the overall SER.

Kai-Chiang Wu and Diana Marculescu, "Power-Aware Soft

Error Hardening via Selective Voltage Scaling", Proc. of Int'l

Conference on Computer Design (ICCD), pp. 301-306, 2008.

Recently, we have studied the radiation tolerance of Dynamic Recently, we have studied the radiation tolerance of Dynamic

Threshold based MOS Design (DTMOS) Technique.Threshold based MOS Design (DTMOS) Technique.

Various DTMOS inverter schemes have been proposed to

improve Standard DTMOS logic inverter. In order to

reduce standby leakage current, Chung et al. have

proposed a new scheme with minimum size small minimum size small

subsidiary transistors subsidiary transistors

The subsidiary transistors increase

the current drive by managing the

body bias

The input load of the inverter circuit

is reduced since the output charges

are used to raise the body potential

of the main transistors.

Later Gil et al. proposed another scheme with subsidiary

transistors that achieved better performance in terms of

speed

Another Dynamic Threshold Inverter Scheme

Below scheme is another DTMOS with subsidiary

transistors, but this time the gates of subsidiary devices

are tied to main transistor’s drain instead of gate

This configuration reported to perform best in terms of

power-delay product when compared to previous

schemes

Soleimani et al. [16] reported even better power

efficiency with the following

stability with respect to temperature was

an issue

In our initial analysis, we studied the effect of decreasing

threshold on SEU and soft delay tolerance. In order to

analyze the effect of decreasing the threshold voltage on

SE Transients and delay effects, we have used a string

of six inverters shown

ANALYSIS

For measuring SE Transients, the input of first inverter is

tied to logic 1, and for soft delay measurements, it is tied

to a switching input waveform. In our analysis, we have

considered 65 nm technology with parameters obtained

using Predictive Technology Model

A soft error occurs when the collected charge collected charge QQcolcol at a at a

particular node exceeds the critical charge particular node exceeds the critical charge QQcritcrit. When

this happens, the generated SE pulse can be latched,

resulting in bit flip in storage element or soft error.

The critical charge here can be defined as the minimum

charge collected due to a particle hit that can cause a

change in circuit output

In order to determine critical charge, the deposited

charge is slowly increased until the SET pulse appears at

the output of inverter string and hence cause a bit flip in

storage element.

Since our aim here is to examine the effect of decreasing

threshold on circuit SET, the threshold voltage value has

been modified via vth0 parameter using delvto option in

Hspice.

Results show that a 100 mV reduction from normal

threshold value increases Qcrit by 33%.

This indicates that if threshold voltage can be reduced,

the circuit robustness to SETs could be increased as the

critical charge value of a node becomes larger. This

confirms the results of Degalahal et al.

We have also studied the effect of threshold on soft delay

effect. This has not been done before to our knowledge.

For soft delay measurement, a pulse signal has been

connected to the input of the first inverter in the inverter

string

67

For soft delay measurement of a series of six inverters, a pulse input signal has been connected to the input of the first inverter. Since soft delay occurs when a particle strikes a sensitive node during signal transition, a radiation hit has been injected around halfway during falling transition at the output of first inverter using double exponential current source.

For soft delay calculation, the 50% delay at the output of

the last inverter gate is first recorded in the presence of

an SE charge. The delay measurement is then repeated

with SE current source removed (no SE charge). The

difference between the two is recorded as “soft delay” at

the output of the inverter string. In our simulations, we

have assumed the critical delay of the circuit is 200 ps

meaning any delay increase more than 200 ps results in

a timing violation and an SDE.

The minimum charge that creates this critical delay has

been recorded as critical charge Qcrit-delay. The result

shows that circuit robustness to soft delay effect also

increases with decreasing threshold voltage.

Fig. Critical Charge Qcrit vs. Vth for a soft delay of 200 pS.

Our initial analysis on threshold voltage has shown that

decreasing threshold voltages increase the critical

charge of logic circuits hence provide more robustness

to SE transients and Soft Delay effects. In normal

DTMOS scheme, the body-source junction is “forward

biased” (at less than 0.6 V), forcing the threshold

voltage to drop and hence this effect can be exploited

for Single Event mitigation. Therefore, in this work, we

study various Dynamic Threshold (DTMOS) schemes

for the purpose of mitigating SE transients and soft

delay errors.

DTMOS Schemes

Based on these results, we have examined various

dynamic threshold based schemes for their vulnerability

to SET and soft delay errors. These methods are widely

used for high speed and low power operations. Results

are then compared to that of Conventional configuration

where transistor body terminals connected to source

terminal.

Various Dynamic Threshold Inverter Schemes Reported

In the comparison, five different circuits including

benchmark circuits have been utilized. These circuits are

6-stage inverter chain, c17 ISCAS-85 and c432

ISCAS-85 benchmark circuit, Full Adder module in

ISCAS-85 c6288 and ALU module in AM2901 4-bit

microprocessor bit-slice.

Although it is dated, the ALU module alone contains 83

gates, 12 input and 10 outputs and 276 SE vulnerable

nodes.

Fig. ISCAS-85 benchmark Circuit

The sizes of all gates are taken as minimum size minimum size with power supply

voltage used in these configurations is 0.6V. The hit locations for

these circuits at nodes close to primary inputs. For example, in c17

benchmark circuit given, node “g7” was selected for hit location and

noise has been propagated to the output for observation. The

critical charge values Qcrit and Qcrit-delay for each circuit have

been determined using the procedure explained before.

ALU module in AM2901 4-bit microprocessorALU module in AM2901 4-bit microprocessor

Configuration

6-stage inverter c17 ISCAS-85 ISCAS-85 c432 ISCAS-85

c6288

AM2901ALU Module

Qcrit

(fC)

Qcrit-delay

(fC)

Qcrit

(fC)

Qcrit-delay

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Normal Body Tie 2.46 6.51 1.70 2.07 2.63 6.51 2.58 6.34 2.03 1.99

Standard DTMOS 3.72 11.05 2.64 4.56 3.76 10.30 3.79 10.86 3.01 3.74

Fig. 4.a [11] 3.27 7.96 2.31 2.65 3.42 8.14 3.48 7.82 2.87 2.53

Fig. 4.b [12] 3.53 8.33 2.50 2.55 3.59 7.94 3.64 7.98 3.44 2.56

Fig. 4.c [13] 2.66 10.00 1.80 3.55 2.84 9.42 2.84 9.46 2.16 2.84

Fig. 4.d [14] 3.22 9.39 2.12 3.24 3.34 9.26 3.36 8.81 2.56 3.02

CRITICAL CHARGE VALUES FOR VARIOUS DTMOS INVERTER SCHEMES

For all four example circuits considered, body tie design achieves the

smallest critical charge among all techniques and hence it is the most

vulnerable one to SETs and soft delay effects.

Configuration

6-stage inverter c17 ISCAS-85 ISCAS-85 c432 ISCAS-85 c6288AM2901

ALU Module

Qcrit

(fC)

Qcrit-del

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Qcrit

(fC)

Qcrit-del

(fC)

Normal Body Tie

2.46 6.51 1.70 2.07 2.63 6.51 2.58 6.34 2.03 1.99

Standard DTMOS

3.72 11.05 2.64 4.56 3.76 10.30 3.79 10.86 3.01 3.74

Fig. 4.a [11] 3.27 7.96 2.31 2.65 3.42 8.14 3.48 7.82 2.87 2.53

Fig. 4.b [12] 3.53 8.33 2.50 2.55 3.59 7.94 3.64 7.98 3.44 2.56

Fig. 4.c [13] 2.66 10.00 1.80 3.55 2.84 9.42 2.84 9.46 2.16 2.84

Fig. 4.d [14] 3.22 9.39 2.12 3.24 3.34 9.26 3.36 8.81 2.56 3.02

CRITICAL CHARGE VALUES FOR VARIOUS DTMOS INVERTER SCHEMES

Standard DTMOS technique shows superior characteristics in terms of

SEU robustness due to highest critical charge for all cases. The critical

charge value needed for soft error in Standard DTMOS is 50% more than

what is required for normal body tie scheme, and hence more robust in

terms of SEU tolerance.

The reason can be explained as follows: Referring to Fig.

when input to DTMOS inverter is low, the body for PMOS

is low and hence PMOS has a forward bias. Since, this , this

increases the drivability of PMOS transistorincreases the drivability of PMOS transistor, a negative

SET pulse at the output can be easily dissipated due to

increased PMOS current drive.

A similar explanation can be made for the case that input is high and a positive SET pulse present at inverter output.

0.6 V

Logic High

For soft delay error, the critical charge values for Standard

DTMOS is more than 60% higher in all cases compared to

Normal body tie configuration. Let us assume the input

waveform is a rising from logic low to high. During the falling

waveform at the output of inverter, if a positive charge is

deposited by an SE particle, this may result in delay increase

or soft delay.

When input rises from Low to High, body of NMOS follows the input body of NMOS follows the input and as a result and as a result NMOS gets a NMOS gets a forward bias. forward bias. This causes output waveform to switch more rapidly and results in a reduced soft delay.

Hardening Against Combinational Circuit Related Soft Errors Hardening Against Combinational Circuit Related Soft Errors

Using DTMOSUsing DTMOS

Researchers have proposed many circuit level techniques

to mitigate SE Transients in CL:

The Spatial redundancy techniques such as Triple

Modular Redundancy (TMR) circuits triplicate the CL to

be protected and then use a voting circuit to filter out the

transient.

Temporal methods sample the data with different delays

and produce the output to a voting circuit to eliminate an

SET pulse.

The driver sizing technique proposed increases device

capacitance and drive current to decrease the device

vulnerability to SEUs

Larger drive strengths of NMOS and PMOS quickly

dissipates the collected charge, reduces the vulnerability

to Single Event particles.

Other techniques such as the one BELOW use different

circuit layouts at the gate and transistor levels to reduce

the chance of a SE to become a transient.

M. P. Baze, S. P. Buchner, D. McMorrow, A Digital CMOS Design

Technique for SEU Hardening, IEEE Trans. on Nuclear Science, vol. 43,

no.6, Dec. 2000.

Our proposed hardening technique is based on use of

Standard DTMOS scheme along with driver sizing. This

combine approach results in considerable area saving

compared to driver sizing alone. This is possible since a

Standard DTMOS gate is more SE robust compared to a

conventional one.

In sizing simulation, we consider the 6-stage inverter chain

consisting of conventional inverters and apply various

deposited charges in between 10-150 fC. For each charge

level, we determine the necessary hit inverter size to

eliminate the soft error effect. We size up the gate

transistors until the soft error is eliminated.

We then repeat the same for soft delay. In this case, the hit

driver should be sized up such that the delay should be

reduced to less than 200 ps. This process is then applied

for the Standard DTMOS inverters.

Above procedure has been repeated for all four example

circuits, and necessary gate sizes have been determined

to eliminate soft error and soft delay error effects.

Again, these circuits are 6-stage inverter chain, c17

ISCAS-85 and ISCAS-85 c432 benchmark circuit, Full

Adder module in ISCAS-85

Deposited Charge

6-stage inverter c17 ISCAS-85 ISCAS-85 c432 ISCAS-85 c6288AM2901

ALU Module

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

10 fC10 fC5X 3X

2X1X

7X5X

4X2X

4X3X

2X1X

4X3X

2X1X

5X4X

4X3X

25 fC25 fC11X7X

3X2X

17X11X

9X4X

10X7X

4X2X

9X6X

4X3X

11X8X

11X6X

50 fC50 fC21X15X

6X4X

34X22X

17X8X

19X14X

7X4X

17X11X

7X5X

20X16X

23X11X

100 fC100 fC42X29X

12X7X

67X44X

34X15X

38X28X

13X9X

33X17X

13X9X

36X29X

47X23X

150 fC150 fC62X43X

18X11X

100X66X

50X22X

57X42X

19X13X

50X21X

19X14X

51X42X

83X33X

GATE SIZES REQUIRED FOR SOFT ERROR AND SOFT DELAY

MITIGATION AT VARIOUS DEPOSITED CHARGES

Deposited Charge

6-stage inverter c17 ISCAS-85 ISCAS-85 c432 ISCAS-85 c6288AM2901

ALU Module

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

SEU Normal /DTMOS

SDE Normal /DTMOS

10 fC10 fC5X 3X

2X1X

7X5X

4X2X

4X3X

2X1X

4X3X

2X1X

5X4X

4X3X

25 fC25 fC11X7X

3X2X

17X11X

9X4X

10X7X

4X2X

9X6X

4X3X

11X8X

11X6X

50 fC50 fC21X15X

6X4X

34X22X

17X8X

19X14X

7X4X

17X11X

7X5X

20X16X

23X11X

100 fC100 fC42X29X

12X7X

67X44X

34X15X

38X28X

13X9X

33X17X

13X9X

36X29X

47X23X

150 fC150 fC62X43X

18X11X

100X66X

50X22X

57X42X

19X13X

50X21X

19X14X

51X42X

83X33X

Results show that Standard DTMOS technique can be used

along with gate sizing in mitigating the Single Event Transients

and Soft Delays with considerably less area overhead.

CONCLUSIONCONCLUSION

As designers address the static power consumption via

optimizations, they need to be aware of the impact on

SEU robustness.

We have analyzed various DTMOS schemes for their soft

error tolerance.

We have found that DTMOS increase circuit robustness

due to increased current drive and hence can be

combined with driver sizing technique to mitigate SET

transients and soft delay effects. This approach results in

considerable area saving compared to driver sizing alone.