Lec Feb02 2009

Anshul Kumar, CSE IITD

CSL718 : Superscalar Processors

CSL718 : Superscalar CSL718 : Superscalar ProcessorsProcessors

Handling Data Dependencies2nd Feb, 2009

Anshul Kumar, CSE IITD slide 2

Illustration 1Illustration 1Illustration 1

CDC6600 : score-boarding scheme• Dispatch bound fetch• FUs : INT, MUL1, MUL2, ADD/SUB, DIV• 1 RS per FU• 1 RF• In order issue, dispatch order trivial, out of

order execution


Checking in dispatch bound fetchChecking in dispatch bound fetchChecking in dispatch bound fetch

RegisterFile

Reservationstation

OC Rs1 Rs2 Rd

EU

decodedinstruction

check V bits of sources

update Rdset V bitRs1,Rs2,Rd

reset V bit of Rd

OC(opcode)

Os1

Os2 (operand value)

result, Rd

INSTRUCTION ISSUE READ OP EX COMPL WRITERESLF F6, 34(R2)LF F2, 45(R3) MUL F0,F2,F4SUB F8,F6,F2DIVF10,F0,F6ADD F6,F8,F2

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT2 MUL13 MUL24 ADD5 DIV

F0 F2 F4 F6 F8 F10 F12 F14FU No

Inst

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stat

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RF

INSTRUCTION ISSUE READ OP EX COMPL WRITERES

LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √

MUL F0,F2,F4 √

SUB F8,F6,F2 √

DIVF10,F0,F6 √ADD F6,F8,F2

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT Y LF2 MUL1 Y MUL3 MUL2 N4 ADD Y SUB5 DIV Y DIV

F0 F2 F4 F6 F8 F10 F12 F14FU No

Inst

ruct

ion

stat

usFu

nctio

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nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √

MUL F0,F2,F4 √

SUB F8,F6,F2 √


No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT Y LF F2 R32 MUL1 Y MUL F0 F2 F43 MUL2 N4 ADD Y SUB F8 F6 F25 DIV Y DIV F10 F0 F6

F0 F2 F4 F6 F8 F10 F12 F14FU No

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √

MUL F0,F2,F4 √

SUB F8,F6,F2 √


No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT Y LF F2 R3 Y Y2 MUL1 Y MUL F0 F2 F4 1 N Y3 MUL2 N4 ADD Y SUB F8 F6 F2 1 Y N5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 1 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √

√

MUL F0,F2,F4 √

SUB F8,F6,F2 √


No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT Y LF F2 R3 N N2 MUL1 Y MUL F0 F2 F4 1 N Y3 MUL2 N4 ADD Y SUB F8 F6 F2 1 Y N5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 1 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √

√ √

MUL F0,F2,F4 √

SUB F8,F6,F2 √


No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 Y MUL F0 F2 F4 Y Y3 MUL2 N4 ADD Y SUB F8 F6 F2 Y Y5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √

SUB F8,F6,F2 √ √

√ √


No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 Y MUL F0 F2 F4 N N3 MUL2 N4 ADD N5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √

SUB F8,F6,F2 √ √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 Y MUL F0 F2 F4 N N3 MUL2 N4 ADD Y ADD F6 F8 F2 Y Y5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √

SUB F8,F6,F2 √ √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

√

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 Y MUL F0 F2 F4 N N3 MUL2 N4 ADD Y ADD F6 F8 F2 N N5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √

SUB F8,F6,F2 √ √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √ √

√

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 Y MUL F0 F2 F4 N N3 MUL2 N4 ADD Y ADD F6 F8 F2 N N5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 2 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √

√ √

SUB F8,F6,F2 √ √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √ √ √

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 N3 MUL2 N4 ADD Y ADD F6 F8 F2 N N5 DIV Y DIV F10 F0 F6 Y Y

F0 F2 F4 F6 F8 F10 F12 F14FU No 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √ √ √

SUB F8,F6,F2 √ √ √ √

DIVF10,F0,F6 √

√

ADD F6,F8,F2 √ √ √

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 N3 MUL2 N4 ADD Y ADD F6 F8 F2 N N5 DIV Y DIV F10 F0 F6 N N

F0 F2 F4 F6 F8 F10 F12 F14FU No 4 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √ √

LF F2, 45(R3) √ √ √ √

MUL F0,F2,F4 √ √ √ √

SUB F8,F6,F2 √ √ √ √

DIVF10,F0,F6 √ √

ADD F6,F8,F2 √ √

√

√

No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk1 INT N2 MUL1 N3 MUL2 N4 ADD N5 DIV Y DIV F10 F0 F6 N N

F0 F2 F4 F6 F8 F10 F12 F14FU No 5

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


Illustration 2Illustration 2Illustration 2

IBM 360/91 - Tomasulo’s scheme• Issue bound fetch• FUs : LOAD, STORE, 3 x ADD/SUB,

2 x MUL/DIV• Group RS’s with 1 slot per FU• 1 RF• In order issue, out of order execution


Checking in issue bound fetchChecking in issue bound fetchChecking in issue bound fetch

OC Os1/Is1 Vs1 Os2/Is2 Vs2 Rd

EU

decodedinstruction

OC, Os1, Os2, Rd

result, Rd

RegisterFile

update Rd, set V bitRs1,Rs2,Rdreset V bit of Rd

Os1

Os2 (operand value)

Reservation station check Vs1, Vs2

associative update ofIs1, Is2 with Rd, set Vs bits

INSTRUCTION ISSUE EX COMPL WRITERESLF F6, 34(R2)LF F2, 45(R3)MUL F0,F2,F4SUB F8,F6,F2DIVF10,F0,F6ADD F6,F8,F2

NAME BUSY OP Vj Vk Qj QkADD1ADD2ADD3MUL1MUL2

F0 F2 F4 F6 F8 F10 F12 F14Qi

Inst

ruct

ion

stat

usFu

nctio

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nits

RF

INSTRUCTION ISSUE EX COMPL WRITERES

LF F6, 34(R2) √ √ √

LF F2, 45(R3) √

MUL F0,F2,F4 √

SUB F8,F6,F2 √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

NAME BUSY OP Vj Vk Qj QkADD1 Y SUBADD2 Y ADDADD3 NMUL1 Y MULMUL2 Y DIV

F0 F2 F4 F6 F8 F10 F12 F14Qi

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √

LF F2, 45(R3) √

MUL F0,F2,F4 √

SUB F8,F6,F2 √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

NAME BUSY OP Vj Vk Qj QkADD1 Y SUB (LD1) LD2ADD2 Y ADD ADD1 LD2ADD3 NMUL1 Y MUL (F4) LD2MUL2 Y DIV (LD1) MUL1

F0 F2 F4 F6 F8 F10 F12 F14Qi MUL1 LD2 ADD2 ADD1 MUL2

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √

LF F2, 45(R3) √

√ √

MUL F0,F2,F4 √

SUB F8,F6,F2 √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

NAME BUSY OP Vj Vk Qj QkADD1 Y SUB (LD1) (LD2)ADD2 Y ADD (LD2) ADD1ADD3 NMUL1 Y MUL (LD2) (F4)MUL2 Y DIV (LD1) MUL1

F0 F2 F4 F6 F8 F10 F12 F14Qi MUL1 ADD2 ADD1 MUL2

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √

LF F2, 45(R3) √ √ √

MUL F0,F2,F4 √

SUB F8,F6,F2 √

√ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

NAME BUSY OP Vj Vk Qj QkADD1 NADD2 Y ADD (ADD1) (LD2)ADD3 NMUL1 Y MUL (LD2) (F4)MUL2 Y DIV (LD1) MUL1

F0 F2 F4 F6 F8 F10 F12 F14Qi MUL1 ADD2 MUL2

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √

LF F2, 45(R3) √ √ √

MUL F0,F2,F4 √

√

SUB F8,F6,F2 √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √

√

NAME BUSY OP Vj Vk Qj QkADD1 NADD2 Y ADD (ADD1) (LD2)ADD3 NMUL1 Y MUL (LD2) (F4)MUL2 Y DIV (LD1) MUL1

F0 F2 F4 F6 F8 F10 F12 F14Qi MUL1 ADD2 MUL2

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √

LF F2, 45(R3) √ √ √

MUL F0,F2,F4 √ √

SUB F8,F6,F2 √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √ √ √

NAME BUSY OP Vj Vk Qj QkADD1 NADD2 NADD3 NMUL1 Y MUL (LD2) (F4)MUL2 Y DIV (LD1) MUL1

F0 F2 F4 F6 F8 F10 F12 F14Qi MUL1 MUL2

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


LF F6, 34(R2) √ √ √

LF F2, 45(R3) √ √ √

MUL F0,F2,F4 √ √ √

SUB F8,F6,F2 √ √ √

DIVF10,F0,F6 √

ADD F6,F8,F2 √ √ √

NAME BUSY OP Vj Vk Qj QkADD1 NADD2 N ADD3 NMUL1 NMUL2 Y DIV (MUL1) (LD1)

F0 F2 F4 F6 F8 F10 F12 F14Qi MUL2

Inst

ruct

ion

stat

usFu

nctio

nal U

nits

RF


ReferenceReferenceReference

1. D.A. Patterson, J.L. Hennessy, "Computer Architecture : A Quantitative Approach", Morgan Kaufmann Publishers, 2006.

Lec Feb02 2009

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Transcript of Lec Feb02 2009