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Introduction to

CMOS VLSIDesign

Datapath Functional Units

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CMOS VLSI DesignDatapath Slide 2

Outline

Comparators

Shifters

Multi-input Adders

Multipliers

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CMOS VLSI DesignDatapath Slide 3

Comparators

0s detector: A = 00000

1s detector: A = 11111

Equality comparator: A = B

Magnitude comparator: A < B

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CMOS VLSI DesignDatapath Slide 4

1s & 0s Detectors

1s detector: N-input AND gate

0s detector: NOTs + 1s detector (N-input NOR)

A0

A1

A2

A3

A4

A5

A6

A7

allones

A0

A1

A2

A3

allzeros

allones

A1

A2

A3

A4

A5

A6

A7

A0

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CMOS VLSI DesignDatapath Slide 5

Equality Comparator

Check if each bit is equal (XNOR, aka equality gate)

1s detect on bitwise equality

A[0]B[0]

A = B

A[1]B[1]

A[2]B[2]

A[3]B[3]

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CMOS VLSI DesignDatapath Slide 6

Magnitude Comparator

Compute B-A and look at sign

B-A = B + ~A + 1

For unsigned numbers, carry out is sign bit

A0

B0

A1

B1

A2

B2

A3

B3

A = BZ

CA B

N A B

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CMOS VLSI DesignDatapath Slide 7

Signed vs. Unsigned

For signed numbers, comparison is harder

C: carry out

Z: zero (all bits of A-B are 0)

N: negative (MSB of result)

V: overflow (inputs had different signs, output sign B)

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CMOS VLSI DesignDatapath Slide 8

Shifters

Logical Shift:

Shifts number left or right and fills with 0s

1011 LSR 1 = ____ 1011 LSL1 = ____

Arithmetic Shift: Shifts number left or right. Rt shift sign extends

1011 ASR1 = ____ 1011 ASL1 = ____

Rotate:

Shifts number left or right and fills with lost bits 1011 ROR1 = ____ 1011 ROL1 = ____

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CMOS VLSI DesignDatapath Slide 9

Shifters

Logical Shift:

Shifts number left or right and fills with 0s

1011 LSR 1 = 0101 1011 LSL1 = 0110

Arithmetic Shift: Shifts number left or right. Rt shift sign extends

1011 ASR1 = 1101 1011 ASL1 = 0110

Rotate:

Shifts number left or right and fills with lost bits 1011 ROR1 = 1101 1011 ROL1 = 0111

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CMOS VLSI DesignDatapath Slide 10

Funnel Shifter

A funnel shifter can do all six types of shifts

Selects N-bit field Y from 2N-bit input

Shift by k bits (0 k < N)

B C

offsetoffset + N-1

0N-12N-1

Y

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CMOS VLSI DesignDatapath Slide 11

Funnel Shifter Operation

Computing N-k requires an adder

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CMOS VLSI DesignDatapath Slide 12

Funnel Shifter Operation

Computing N-k requires an adder

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CMOS VLSI DesignDatapath Slide 13

Funnel Shifter Operation

Computing N-k requires an adder

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CMOS VLSI DesignDatapath Slide 14

Funnel Shifter Operation

Computing N-k requires an adder

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CMOS VLSI DesignDatapath Slide 15

Funnel Shifter Operation

Computing N-k requires an adder

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CMOS VLSI DesignDatapath Slide 16

Simplified Funnel Shifter

Optimize down to 2N-1 bit input

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CMOS VLSI DesignDatapath Slide 17

Simplified Funnel Shifter

Optimize down to 2N-1 bit input

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CMOS VLSI DesignDatapath Slide 18

Simplified Funnel Shifter

Optimize down to 2N-1 bit input

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CMOS VLSI DesignDatapath Slide 19

Simplified Funnel Shifter

Optimize down to 2N-1 bit input

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CMOS VLSI DesignDatapath Slide 20

Simplified Funnel Shifter

Optimize down to 2N-1 bit input

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CMOS VLSI DesignDatapath Slide 21

Funnel Shifter Design 1

N N-input multiplexers

Use 1-of-N hot select signals for shift amount

nMOS pass transistor design (Vtdrops!)k[1:0]

s0

s1

s2

s3

Y3

Y2

Y1

Y0

Z0

Z1

Z2

Z3

Z4

Z5

Z6

left Inverters & Decoder

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CMOS VLSI DesignDatapath Slide 22

Funnel Shifter Design 2

Log N stages of 2-input muxes

No select decoding needed

Y3

Y2

Y1

Y0Z

0

Z1

Z2

Z3

Z4

Z5

Z6

k0

k1

left

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CMOS VLSI DesignDatapath Slide 23

Multi-input Adders

Suppose we want to add k N-bit words

Ex: 0001 + 0111 + 1101 + 0010 = _____

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CMOS VLSI DesignDatapath Slide 24

Multi-input Adders

Suppose we want to add k N-bit words

Ex: 0001 + 0111 + 1101 + 0010 = 10111

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CMOS VLSI DesignDatapath Slide 25

Multi-input Adders

Suppose we want to add k N-bit words

Ex: 0001 + 0111 + 1101 + 0010 = 10111

Straightforward solution: k-1 N-input CPAs

Large and slow

+

+

0001 0111

+

1101 0010

10101

10111

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CMOS VLSI DesignDatapath Slide 26

Carry Save Addition

A full adder sums 3 inputs and produces 2 outputs

Carry output has twice weightof sum output

N full adders in parallel are called carry save adder

Produce N sums and N carry outs

Z4

Y4

X4

S4

C4

Z3

Y3

X3

S3

C3

Z2

Y2

X2

S2

C2

Z1

Y1

X1

S1

C1

XN...1 YN...1 ZN...1

SN...1

CN...1

n-bit CSA

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CMOS VLSI DesignDatapath Slide 27

CSA Application

Use k-2 stages of CSAs

Keep result in carry-save redundant form

Final CPA computes actual result

4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

0001

0111

+1101

1011

0101_

X

YZ

S

C

0101_

1011

+0010

X

Y

Z

SC

A

B

S

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CMOS VLSI DesignDatapath Slide 28

CSA Application

Use k-2 stages of CSAs

Keep result in carry-save redundant form

Final CPA computes actual result

4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

01010_ 00011

0001

0111

+1101

1011

0101_

X

YZ

S

C

0101_

1011

+0010

0001101010_

X

Y

Z

SC

01010_

+ 00011

A

B

S

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CMOS VLSI DesignDatapath Slide 29

CSA Application

Use k-2 stages of CSAs

Keep result in carry-save redundant form

Final CPA computes actual result

4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

01010_ 00011

0001

0111

+1101

1011

0101_

X

YZ

S

C

0101_

1011

+0010

0001101010_

X

Y

Z

SC

01010_

+ 00011

10111

A

B

S

10111

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CMOS VLSI DesignDatapath Slide 30

Multiplication

Example: 1100 : 1210

0101 : 510

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CMOS VLSI DesignDatapath Slide 31

Multiplication

Example: 1100 : 1210

0101 : 510

1100

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CMOS VLSI DesignDatapath Slide 32

Multiplication

Example: 1100 : 1210

0101 : 510

1100

0000

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CMOS VLSI DesignDatapath Slide 33

Multiplication

Example: 1100 : 1210

0101 : 510

1100

0000

1100

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CMOS VLSI DesignDatapath Slide 34

Multiplication

Example: 1100 : 1210

0101 : 510

1100

0000

11000000

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CMOS VLSI DesignDatapath Slide 35

Multiplication

Example: 1100 : 1210

0101 : 510

1100

0000

11000000

00111100 : 6010

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CMOS VLSI DesignDatapath Slide 36

Multiplication

Example:

M x N-bit multiplication

Produce N M-bit partial products Sum these to produce M+N-bit product

1100 : 1210

0101 : 510

1100

0000

11000000

00111100 : 6010

multiplier

multiplicand

partial

products

product

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CMOS VLSI DesignDatapath Slide 37

General Form

Multiplicand: Y = (yM-1, yM-2, , y1, y0)

Multiplier: X = (xN-1, xN-2, , x1, x0)

Product:1 1 1 1

0 0 0 0

2 2 2

M N N Mj i i j

j i i j

j i i j

P y x x y

x0y

5 x

0y

4 x

0y

3 x

0y

2 x

0y

1 x

0y

0

y5

y4

y3

y2

y1

y0

x5

x4

x3

x2

x1

x0

x1y

5 x

1y

4 x

1y

3 x

1y

2 x

1y

1 x

1y

0

x2y5 x2y4 x2y3 x2y2 x2y1 x2y0x

3y

5 x

3y

4 x

3y

3 x

3y

2 x

3y

1 x

3y

0

x4y

5 x

4y

4 x

4y

3 x

4y

2 x

4y

1 x

4y

0

x5y

5 x

5y

4 x

5y

3 x

5y

2 x

5y

1 x

5y

0

p0

p1

p2

p3

p4

p5

p6

p7

p8

p9

p10

p11

multiplier

multiplicand

partialproducts

product

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CMOS VLSI DesignDatapath Slide 39

Array Multiplier

y0y1y2y3

x0

x1

x2

x3

p0

p1

p2

p3

p4

p5

p6

p7

B

ASin Cin

SoutCout

BA

CinCout

Sout

Sin

=

CSA

Array

CPA

critical path BA

Sout

Cout CinCout

Sout

=Cin

BA

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CMOS VLSI DesignDatapath Slide 42

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 43

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 44

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 45

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 46

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 48

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 49

Booth Encoding

Instead of 3Y, tryY, then increment next partialproduct to add 4Y

Similarly, for 2Y, try2Y + 4Y in next partial product

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CMOS VLSI DesignDatapath Slide 50

Booth Hardware

Booth encoder generates control lines for each PP

Booth selectors choose PP bits

Mi

yj

Xi

yj-1

2Xi

PPij

Booth

Selector

Booth

Encoder

x2i+1

x2i

x2i-1

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CMOS VLSI DesignDatapath Slide 51

Sign Extension

Partial products can be negative

Require sign extension, which is cumbersome

High fanout on most significant bit

multiplierx

x0

x15

0

00

x-1

x16

x17

ssssssssssssssss

s

sssssssssssss

ssssssssssss

ssssssssss

ssssssss

ssssss

ssss

ss

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PP8

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CMOS VLSI DesignDatapath Slide 52

Simplified Sign Ext.

Sign bits are either all 0s or all 1s

Note that all 0s is all 1s + 1 in proper column

Use this to reduce loading on MSB

s111111111111111

s

s1111111111111s

s11111111111s

s111111111s

s1111111s

s11111

s

s111s

s1s

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PP8

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CMOS VLSI DesignDatapath Slide 53

Even Simpler Sign Ext.

No need to add all the 1s in hardware

Precompute the answer!

ssss

s

s1

ss1

ss1

ss1

ss1

ss1

ss

PP0

PP1

PP2PP

3

PP4

PP5

PP6

PP7

PP8

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CMOS VLSI DesignDatapath Slide 54

Advanced Multiplication

Signed vs. unsigned inputs

Higher radix Booth encoding

Array vs. tree CSA networks