Leakage-Biased Domino Circuits for Dynamic Fine- Grain Leakage Reduction Seongmoo Heo and Krste...
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Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction Seongmoo Heo and Krste Asanović Massachusetts Institute of Technology Lab for Computer Science Symposium on VLSI Circuits 2002
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Transcript of Leakage-Biased Domino Circuits for Dynamic Fine- Grain Leakage Reduction Seongmoo Heo and Krste...
Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction
Seongmoo Heo and Krste Asanović
Massachusetts Institute of Technology Lab for Computer Science
Symposium on VLSI Circuits 2002
Leakage Power
• Growing impact of leakage power– Increase of leakage power due to
scaling of transistor lengths and threshold voltages
– Power budget limits use of fast leaky transistors
• Challenge:– How to maintain performance scaling in
face of increasing leakage power?
Leakage Reduction Techniques
Static: Design-time Selection of Slow Transistors (SSST) for non-critical paths– Replace fast transistors with slow ones on
non-critical paths– Tradeoff between delay and leakage power
Dynamic: Run-time Deactivation of Fast Transistors (DDFT) for critical paths– DDFT switches critical path transistors
between inactive and active modes
Observation:
Critical paths dominate leakage after applying SSST techniques
Example: PowerPC 750– 5% of transistor width is low Vt, but
these account for >50% of total leakage.
DDFT could give large leakage savings
DDFT Techniques for Domino
• Dual-Vt Domino [Kao and Chandrakasan, 2000]
– High Vt for precharge phase– Input gating increased delay and active
energy– High Vt keeper increased noise margin
1
(High Vt transistor: Green colored)
DDFT Techniques for Domino
• Dual-Vt Domino– High Vt for precharge phase– Input gating increased delay and active
energy– High Vt keeper increased noise margin
1
DDFT Techniques for Domino• MHS-Domino [Allam, Anis, Elmasry, 2000]
– Clock-delayed keeper
sleepb
clk
in
DDFT Techniques for Domino• MHS-Domino– Pull-down through PMOS short circuit-
current in static inverter
sleepb=0
clk
in
dynamic node
Conventional Domino
clk
in
Leakage-Biased (LB) Domino
clk
Sleep
in
Sleepb
Two sleep transistors in non-critical path
Leakage-Biased (LB) Domino
Active mode
clk
Sleep(=0)
in
Sleepb(=1)
Leakage-Biased (LB) Domino
Sleep mode
clk(=1)
Sleep(=1)
In(=0) NODE1 (10)
Sleepb(=0)
NODE2 (01)
LB-Domino biases itself into a low-leakage stage by its leakage current
Han-Carlson Adder
• Evaluation with carry generation circuit of a 32-bit Han-Carlson adder– 6 levels of alternating dynamic and
static logic– 4 circuits: LVT, DVT, LB, and LB2
• Constraints– Input/Output noise margin kept to 10%
of Vdd
– Precharge/Evaluation delay equalized to within 1% error
PG Cells of Han-Carlson Adder
(a) Low Vt (LVT) (b) Dual Vt (DVT)
(c) Leakage-Biased 1 (LB) (d) Leakage-Biased 2 (LB2)
Processes• 180nm: TSMC 180nm Processes• 70nm: BPTM 70nm Processes
Process 180nm 70nm
High Vt (NMOS/PMOS)
0.46V/-0.45V 0.39V/-0.40V
Low Vt (NMOS/PMOS)
0.27V/-0.23V 0.15V/-0.18V
Vdd 1.8V 0.9V
Temperature 100C 100C
Input Vectors
• 3 different input vectors– Active energy and leakage power dependent
upon inputs– Vec1 discharges no dynamic nodes– Vec2 discharge half of dynamic nodes– Vec3 discharge all dynamic nodes
A B Ci
Vector 1 0x00000000 0x00000000 0
Vector 2 0xffffffff 0x00000000 0
Vector 3 0xffffffff 0xffffffff 1
Delay and Active Power: 180nmEval/Prech delay
0
40
80
120
160
200
240
LVT DVT LB LB2
Del
ay (
ps)
eval
prech
Active energy
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
LVT DVT LB LB2
En
erg
y (n
J)
vec1
vec2
vec3
Delay and Active Power: 70nmActive energy
0
5
10
15
20
25
30
35
LVT DVT LB LB2
En
erg
y (p
J)
vec1
vec2
vec3
Eval/Prech delay
0
10
20
30
40
50
60
LVT DVT LB LB2
Del
ay (
ps)
eval
prech
Steady-State Leakage Power
70 nm process
1
10
100
1000
10000
LVT DVT LB LB2
Le
ak
ag
e p
ow
er
(uW
)
vec1
vec2
vec3
180 nm process
0
20
40
60
80
100
120
LVT DVT LB LB2
Le
ak
ag
e p
ow
er
(uW
)
vec1
vec2
vec3
Cumulative Sleep Energy: 180nm
vec1
0
50
100
150
200
250
0 1 2 3
Time (us)
En
erg
y (p
J)
vec2
0
50
100
150
200
250
0 1 2 3
Time (us)
vec3
0
50
100
150
200
250
0 1 2 3
Time (us)
LVT
DVT
LB
LB2
Cumulative Sleep Energy: 70nm
vec1
0
4
8
12
16
20
0 5 10
Time (ns)
En
erg
y (p
J)
vec2
0
4
8
12
16
20
0 5 10
Time (ns)
vec3
0
4
8
12
16
20
0 5 10
Time (ns)
LVT
DVT
LB
LB2
Conclusion
• Leakage-Biased Idea– Leakage can be used to bias nodes into
low-leakage states
• LB-Domino for Fine-grain leakage reduction– 100x reduction in steady-state leakage– Low deactivation and wakeup time – Low transition energy • >10ns breakeven time at 70nm process
Acknowledgement
• Funded by DARPA PAC/C award F30602-00-2-0562, NSF CAREER award CCR-0093354, and a donation from Infineon Technologies.
