Lcdf3 Chap 04

Chapter 4 Combinational Logic

Digital Design with an Introduction to the Verilog HDL

Pearson Education, Inc. Modified by Y. L. Li, CS/NCTU Digital Design with Verilog Practice

Chap 4

2

Overview Combinational Circuits Analysis Procedure Design Procedure Binary Adder-Subtractor Decimal Adder Binary Multiplier Magnitude Comparator Decoders Encoders Multiplexers

2


Chap 4

3

Combinational Circuits

A combinational logic circuit has: A set of n Boolean inputs, A set of m Boolean outputs, and m switching functions, each mapping the 2n input

combinations to an output such that the current output depends only on the current input values

A block diagram:

n Boolean Inputs m Boolean Outputs

CombinatorialLogicCircuit


Chap 4

4

Reusable Functions Whenever possible, we try to decompose

a complex design into common, reusablefunction blocks Reusable can be used in more than on

place in the circuit design as well as in other circuits.

Instance the use of a block in each such place.

These blocks are verified and well-documented placed in libraries for future use


Chap 4

5

Top-Down versus Bottom-Up

A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement

A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks

Designs usually proceed from both directions simultaneously Top-down design answers: What are we building? Bottom-up design answers: How do we build it?

Top-down controls complexity while bottom-up focuses on the details


Chap 4

6

Hardware Description Language

HDL is to describe hardware structures and behaviors. Whats the difference between HDL and PL HDL

describes extensive parallel operation. Why HDL?

Flexible can describe hardware at any level in the hierarchical tree.

Portable across many CAD tools. (schematic tool is not) Easy to test can perform simulation on HDL designs.

Analysis lexicon and grammar checking. Elaboration flatten hierarchical design to an interconnection of

modules described by behaviors. Design automation logic synthesis.

Testbench describe hardware and software that applies inputs to the device under test (DUT) and analyze the outputs for correctness.


Chap 4

7

Analysis Procedure Make sure the logic diagram is combinational. Derive Boolean functions from L.D.

Label and find their Boolean functions all gate outputs that are a function only of true or complemented form of input variables.

Label and find their Boolean functions the gates that are a function of input variables and labeled gates.

Derive truth table Determine the number of input variables in the circuit. Set intermediate observation points and add their values

into truth table. Proceed to previous steps until circuit outputs are

determined. Logic simulation


Chap 4

8

Derivation of Boolean Functions

DBATF

DBDBCBADBADDBACBATTFDBADTTDBADDBADBADTT

CBATATBATCBT

52

431

2524

1321

Level 0 Level 1 Level 2


Chap 4

9

Derivation of the Truth Table

How to set observation points easy to derive the output valueof next gates


Chap 4

10

Logic Simulation

When to read outthe output value?


Chap 4

11

Design Procedure

1. Specification Write a specification for the circuit if one is not

already available2. Formulation

Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification

3. Optimization Apply 2-level and multiple-level optimization Draw a logic diagram or provide a netlist for the

resulting circuit using ANDs, ORs, and inverters


Chap 4

12

Design Procedure

4. Technology Mapping Map the logic diagram or netlist to the

implementation technology selected5. Verification

Verify the correctness of the final design


Chap 4

13

Design Example

1. Specification BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3

code for the decimal digits BCD code words for digits 0 through 9: 4-bit patterns

0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-bit

patterns consisting of 3 (binary 0011) added to each BCD code word

Implementation: multiple-level circuit NAND gates (including inverters)


Chap 4

14

Design Example (continued)

2. Formulation Conversion of 4-bit codes can be most easily

formulated by a truth table Variables

- BCD:A,B,C,D

Variables- Excess-3W,X,Y,Z

Dont Cares- BCD 1010

to 1111

Input BCDA B C D

Output Excess-3WXYZ

0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 0


Chap 4

15


3. Optimizationa. 2-level using

K-mapsW = A + BC + BDX = C + D + BY = CD + Z =

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

11

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

11

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1 1

1

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1 1

1

X X X

X X

X

1

1

w

z y

x

B CDBCD

D


Chap 4

16


3. Optimization (continued)b. Multiple-level using transformations

W = A + BC + BDX = C + D + BY = CD + Z = G = 7 + 10 + 6 + 0 = 23

Perform extraction, finding factor:T1 = C + DW = A + BT1X = T1 + BY = CD + Z = G = 2 + 1 + 4 + 7 + 6 + 0 = 19

B C DBC D

D

B C DCD

D


Chap 4

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Chap 4

18


3. Optimization (continued)b. Multiple-level using transformations

T1 = C + DW = A + BT1X = T1 + BY = CD + Z = G = 19

An additional extraction not shown in the text since it uses a Boolean transformation: ( = C + D = ):W = A + BT1X = T1 + B Y = CD + Z = G = 2 +1 + 4 + 6 + 4 + 0 = 16!

B C DC D

D

B T1

DT1

CD T1


Chap 4

19

Design Example (continued)4. Technology Mapping

Mapping with a library containing inverters and 2-input NAND, 2-input NOR, and 2-2 AOI gates

A

B

C

D

W

X

Y

Z

A

B

CD

W

X

Y

Z


Chap 4

20

BCD-to-Seven-Segment Decoder

CBACBACBADCAgCBADBADCACBAf

DCBDCAeDCBACBADCBCBADCAd

CBADCBDABAcCBACDADCABAbCBADCBBDACAa


Chap 4

21

Iterative Combinational Circuits

Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position

Can design functional block for subfunction and repeat to obtain functional block for overall function

Cell - subfunction block Iterative array - an array of interconnected cells An iterative array can be in a single dimension

(1D) or multiple dimensions


Chap 4

22

Cell n-1Xn-1Yn-1

A n-1Bn-1

Cn-1

XnYn

Cell 1X1Y1

A 1

C1

Cell 0X0Y0

B0

C0

X2Y2

A 0B1

Block Diagram of a 1D Iterative Array

Example: n = 32 Number of inputs = ? Truth table rows = ? Equations with up to ? input variables Equations with huge number of terms Design impractical!

Iterative array takes advantage of the regularity to make design feasible


Chap 4

23

Functional Blocks: Addition

Binary addition used frequently Addition Development:

Half-Adder (HA), a 2-input bit-wise addition functional block,

Full-Adder (FA), a 3-input bit-wise addition functional block,

Ripple Carry Adder, an iterative array to perform binary addition, and

Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance.


Chap 4

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Functional Block: Half-Adder

A 2-input, 1-bit width binary adder that performs the following computations:

A half adder adds two bits to produce a two-bit sum The sum is expressed as a

sum bit , S and a carry bit, C The half adder can be specified

as a truth table for S and C

X 0 0 1 1+ Y + 0 + 1 + 0 + 1C S 0 0 0 1 0 1 1 0

X Y C S0 0 0 00 1 0 11 0 0 11 1 1 0


Chap 4

25

Logic Simplification: Half-Adder

The K-Map for S, C is: This is a pretty trivial map!

By inspection:

and

These equations lead to several implementations.

Y

X0 1

3211

S Y

X0 1

32 1

C

)YX()YX(SYXYXYXS

)(CYXC

)YX(


Chap 4

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Five Implementations: Half-Adder

We can derive following sets of equations for a half-adder:

(a), (b), and (e) are SOP, POS, and XOR implementations for S.

In (c), the C function is used as a term in the AND-NOR implementation of S, and in (d), the function is used in a POS term for S.

YXC)(S)c(

YXC)YX()YX(S)b(

YXCYXYXS)a(

YXC

YXCYXS)e(

)YX(CC)YX(S)d(

C


Chap 4

27

Implementations: Half-Adder The most common half

adder implementation is: (e)

A NAND only implementation is:

YXCYXS

)(CS

)YX(

XY

C

S

X

Y

C

SYX


Chap 4

28

Functional Block: Full-Adder

A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C.

For a carry-in (Z) of 0, it is the same as the half-adder:

For a carry- in(Z) of 1:

Z 0 0 0 0X 0 0 1 1

+ Y + 0 + 1 + 0 + 1C S 0 0 0 1 0 1 1 0

Z 1 1 1 1X 0 0 1 1

+ Y + 0 + 1 + 0 + 1C S 0 1 1 0 1 0 1 1


Chap 4

29

Logic Optimization: Full-Adder

Full-Adder Truth Table:

Full-Adder K-Map:

X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

X

Y

Z

0 1 3 2

4 5 7 61

1

1

1S

X

Y

Z

0 1 3 2

4 5 7 61 11

1C


Chap 4

30

Equations: Full-Adder From the K-Map, we get:

The S function is the three-bit XOR function (Odd Function):

The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as:

The term XY is carry generate. The term XY is carry propagate.

ZYZXYXCZYXZYXZYXZYXS

ZYXS

Z)YX(YXC


Chap 4

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Implementation: Full Adder

Full Adder Schematic Here X, Y, and Z, and C

(from the previous pages)are A, B, Ci and Co,respectively. Also,

G = generate and P = propagate.

Note: This is really a combinationof a 3-bit odd function (for S)) andCarry logic (for Co):

(G = Generate) OR (P =Propagate AND Ci = Carry In)Co G + P Ci

AiBi

Ci

Ci+1

Gi

Pi

Si

Z)YX(YXC


Chap 4

32

Binary Adders

To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors

Example: 4-bit ripple carryadder: Adds input vectors A(3:0) and B(3:0) to geta sum vector S(3:0)

Note: carry out of cell ibecomes carry in of celli + 1

Description Subscript3 2 1 0

Name

Carry In 0 1 1 0 CiAugend 1 0 1 1 AiAddend 0 0 1 1 BiSum 1 1 1 0 Si

Carry out 0 0 1 1 Ci+1


Chap 4

33

4-bit Ripple-Carry Binary Adder

A four-bit Ripple Carry Adder made from four 1-bit Full Adders:

B3 A 3

FA

B2 A 2

FA

B1

S3C4

C0C3 C2 C1

S2 S1 S0

A 1

FA

B0 A 0

FA


Chap 4

34

Carry Propagation & Delay One problem with the addition of binary numbers is

the length of time to propagate the ripple carry from the least significant bit to the most significant bit.

The gate-level propagation path for a 4-bit ripple carry adder of the last example:

Note: The "long path" is from A0 or B0 though the circuit to S3.

A3 B3

S3

B2

S2

B1

S1 S0

B0A2 A1 A0

C4

C3 C2 C1 C0


Chap 4

35

Carry Lookahead

Given Stage i from a Full Adder, we know that there will be a carry generated when Ai = Bi = "1", whether or not there is a carry-in.

Alternately, there will be a carry propagated if the half-sum is "1" and acarry-in, Ci occurs.

These two signal conditions are called generate, denoted as Gi, and propagate, denoted as Pi respectively and are identified in the circuit:

AiBi

Ci

Ci+1

Gi

Pi

Si


Chap 4

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Carry Lookahead (continued)

In the ripple carry adder: Gi, Pi, and Si are local to each cell of the adder Ci is also local each cell

In the carry lookahead adder, in order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells

Defining the equations for the Full Adder in term of the Pi and Gi:

iiiiii BAGBAP iii1iiii CPGCCPS


Chap 4

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Carry Lookahead Development

Ci+1 can be removed from the cells and used to derive a set of carry equations spanning multiple cells.

Beginning at the cell 0 with carry in C0:C1 = G0 + P0 C0

C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1+ P3P2P1G0+ P3P2P1P0 C0

C2 = G1 + P1 C1 = G1 + P1(G0 + P0 C0)= G1 + P1G0 + P1P0 C0

C3 = G2 + P2 C2 = G2 + P2(G1 + P1G0 + P1P0 C0)= G2 + P2G1 + P2P1G0 + P2P1P0 C0


Chap 4

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Group Carry Lookahead Logic Figure 3-29 in the text shows the implementation of these

equations for four bits. This could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible.

Instead, the concept is extended another level by considering group generate (G0-3) and group propagate (P0-3) functions:

Using these two equations:

Thus, it is possible to have four 4-bit adders use one of the same carry lookahead circuit to speed up 16-bit addition

012330

012312323330

PPPPPGPPPGPPGPGG

030304 CPGC

C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1+ P3P2P1G0+ P3P2P1P0 C0


Chap 4

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Development of a Carry Lookahead Adder

c44-bit CLA adder

group srtucture


Chap 4

40

Unsigned Subtraction

Algorithm: Subtract the subtrahend N from the minuend M If no end borrow occurs, then M N, and the result is

a non-negative number and correct. If an end borrow occurs, the N > M and the difference

M N + 2n is subtracted from 2n, and a minus sign is appended to the result. ( (M-N+2n)-2n = -(2n-(M-N+2n) )

Examples: 0 1 1001 0100 0111 0111

0010 110110000 1101

() 0011


Chap 4

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Unsigned Subtraction (continued)

The subtraction, 2n N, is taking the 2s complement of N

To do both unsigned addition and unsigned subtraction requires:

Quite complex! Goal: Shared simpler

logic for both additionand subtraction

Introduce complementsas an approach

A B

Binary adder Binary subtractor

Selective2's complementer

Quadruple 2-to-1multiplexer

Result

Borrow

Complement

S0 1Subtract/Add


Chap 4

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Complements

Two complements (n bits): Diminished Radix Complement of N

(r 1)s complement for radix r 1s complement for radix 2 Defined as (rn Range max: (r(n-1)-1), min: (r(n-1)-1), +0

Radix Complement rs complement for radix r 2s complement in binary Defined as rn N Range max: (r(n-1)-1), min: r(n-1)

Complement(Complement(value)) = value


Chap 4

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Binary 1's Complement

For r = 2, N = 011100112, n = 8 (8 digits):(rn 1) = 256 -1 = 25510 or 111111112

The 1's complement of 011100112 is then:11111111

0111001110001100

Since the 2n 1 factor consists of all 1's and since 1 0 = 1 and 1 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).


Chap 4

44

Binary 2's Complement

For r = 2, N = 011100112, n = 8 (8 digits), we have:(rn ) = 25610 or 1000000002

The 2's complement of 01110011 is then:100000000 100000000

01110011 0110010010001101 10011100

Note the result is the 1's complement plus 1, a fact that can be used in designing hardware


Chap 4

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Subtraction with 2s Complement For n-digit, unsigned numbers M and N, find M N in base 2:

Add the 2's complement of the subtrahend N to the minuend M:

M + (2n N) = M N + 2n If M N, the sum produces end carry 2n which is

discarded; from above, M N remains. If M < N, the sum does not produce an end carry

and, from above, is equal to 2n ( N M ), the 2's complement of ( N M ).

To obtain the result (N M) , take the 2's complement of the sum and place a to its left.


Chap 4

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Unsigned 2s Complement Subtraction Example 1

Find 010101002 01000011201010100 01010100

01000011 + 1011110100010001

The carry of 1 indicates that no correction of the result is required.

12s comp


Chap 4

47


Find 010000112 01010100201000011 01000011

01010100 + 101011001110111100010001

The carry of 0 indicates that a correction of the result is required.

Result = (00010001)

0

2s comp2s comp


Chap 4

48

Subtraction with Diminished Radix Complement For n-digit, unsigned numbers M and N, find M N in

base 2: Add the 1's complement of the subtrahend N to the minuend

M:M + (2n 1 N) = M N + 2n 1

If M N, the result is excess by 2n 1. The end carry 2n when discarded removes 2n, leaving a result short by 1. To fix this shortage, whenever and end carry occurs, add 1 in the LSB position. This is called the end-around carry.

If M < N, the sum does not produce an end carry and, from above, is equal to 2n 1 ( N M ), the 1's complement of( N M ).

To obtain the result (N M) , take the 1's complement of the sum and place a to its left.


Chap 4

49

Unsigned 1s Complement Subtraction -Example 1

Find 010101002 01000011201010100 01010100

01000011 + 1011110000010000

+100010001

The end-around carry occurs.

1

1s comp


Chap 4

50


Find 010000112 01010100201000011 01000011

01010100 + 101010111110111000010001

The carry of 0 indicates that a correction of the result is required.

Result = (00010001)

1s comp

1s comp

0


Chap 4

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2s Complement Adder/Subtractor Subtraction can be done by addition of the 2's

Complement. 1. Complement each bit (1's Complement.)2. Add 1 to the result.

The circuit shown computes A + B and A B: For S = 1, subtract,

the 2s complementof B is formed by usingXORs to form the 1scomp and adding the 1applied to C0.

For S = 0, add, B ispassed throughunchanged

FA FA FA FA

S

B3

C3

S2 S1 S0S3C4

C2 C1 C0

A 3 B2 A 2 B1 A 1 B0 A 0


Chap 4

52

Signed Integers Positive numbers and zero can be represented by

unsigned n-digit, radix r numbers. We need a representation for negative numbers.

To represent a sign (+ or ) we need exactly one more bit of information (1 binary digit gives 21 = 2 elements which is exactly what is needed).

Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit:

s an2 a2a1a0where:s = 0 for Positive numberss = 1 for Negative numbers

and ai = 0 or 1 represent the magnitude in some form.


Chap 4

53

Signed Integer Representations

Signed-Magnitude here the n 1 digits are interpreted as a positive magnitude.Signed-Complement here the digits are interpreted as the rest of the complement of the number. There are two possibilities here:

Signed 1's Complement Uses 1's Complement Arithmetic

Signed 2's Complement Uses 2's Complement Arithmetic


Chap 4

54

Signed Integer Representation Example r =2, n=3

Number Sign -Mag. 1's Comp. 2's Comp.+3 011 011 011+2 010 010 010+1 001 001 001+0 000 000 000 0 100 111 1 101 110 111 2 110 101 110 3 111 100 101 4 100


Chap 4

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Signed-Magnitude Arithmetic If the parity of the three signs is 0:

(+++,+,+,+)1. Add the magnitudes.2. overflow detection check if there is a carry out of the MSB.3. The sign of the result is the same as the sign of the

first operand.

If the parity of the three signs is 1: (++,++,++,)

1. Subtract the second magnitude from the first.2. If a borrow occurs:

take the twos complement of result and make the result sign the complement of the sign of

the first operand.3. Overflow will never occur.


Chap 4

56

Example 1: 0010+0101

0111 Example 2: 0010

+11011101 1011

Example 3: 1010 0101

1111

Sign-Magnitude Arithmetic Examples

2s complement


Chap 4

57

Signed-Complement Arithmetic Addition:

1. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end-around carry (1's Complement).

2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred.

3. The sign of the result is computed in step 1. Subtraction:

Form the complement of the number you are subtracting and follow the rules for addition.


Chap 4

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Example 1: 1101+001110000

Example 2: 1101 11010011 1101

11010

Signed 2s Complement Examples


Chap 4

59

Example 1: 1101+001110000 0001

Example 2: 1101 11010011 +1100

11001 1010

Signed 1s Complement Examples

+


Chap 4

60

Overflow Detection

Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction

Overflow can occur for: Addition of two operands with the same sign Subtraction of operands with different signs

Signed number overflow cases with correct result sign0 0 1 1

+ 0 1 0 + 10 0 1 1

Detection can be performed by examining the result signs which should match the signs of the top operand


Chap 4

61

Overflow Detection Signed number cases with carries Cn and Cn shown for correct result signs:

0 0 0 0 1 1 1 10 0 1 1

+ 0 1 0 + 10 0 1 1

Signed number cases with carries shown for erroneous result signs (indicating overflow):

0 1 0 1 1 0 1 00 0 1 1

+ 0 1 0 + 11 1 0 0

Simplest way to implement overflow V = Cn Cn Detection scheme must also apply to the complementing circuit (complement each bit and add 1) 2s complement minimum negative number (2(n-1))


Chap 4

62

Decimal Adder Add two BCD's

9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out

Design approaches A truth table with 2^9 entries use binary full Adders

the sum


Chap 4

63

BCD Adder: Truth Table


Chap 4

64

BCD Adder

BCD adder Add 0110 when result 1010 BCD carry = 1. What are the characteristics of those values 1010

(10/1010 ~ 18/10010) 1010, 1011, 1100, 1101, 1110, 1111, 10000, 10001, 10010.


Chap 4

65

Binary Multiplication

The binary digit multiplication table is trivial:

This is simply the Boolean AND function.

Form larger products the same way we form larger products in base 10.

(a b) b = 0 b = 1a = 0 0 0a = 1 0 1


Chap 4

66

Example: (101 x 011) Base 2

Partial products are: 101 1, 101 1, and 101 0

Note that the partial productsummation for n digit, base 2numbers requires adding upto n digits (with carries) ina column.

Note also n m digit multiply generates up to an m + n digit result (same as decimal).

1 0 1

0 1 11 0 1

1 0 10 0 0

0 0 1 1 1 1

HAFA


Chap 4

67

Multiplier Arrays Using Adders

An implementation of the 2 2 multiplier array is shown:

C0C3

HA HA

C2 C1

A0

A1B1 B0

B1 B0


Chap 4

68

Multiplier Using Wide Adders

A more structured way to develop an n mmultiplier is to sum partial products using adder trees n multiplicand, m multiplier.

The partial products are formed using an n marray of AND gates

Partial products are summed using m 1 adders of width n bits

Example: 4-bit by 3-bit adder 4 3 = 12 element array of AND gates and two 4-bit

adders


Chap 4

69

4 3 Multiplier


Chap 4

70

Magnitude Comparator The comparison of two numbers

outputs: A>B, A=B, A


Chap 4

71

Algorithm -> logic A = A3A2A1A0 ; B = B3B2B1B0 A=B if A3=B3, A2=B2, A1=B1and A1=B1

equality: xi= AiBi+Ai'Bi', for i = 0, 1, 2, 3 (A=B) = x3x2x1x0

(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

(A>B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

Implementation xi = (AiBi'+Ai'Bi)'

Magnitude Comparator


Chap 4

72

Enabling Function

Enabling permits an input signal to pass through to an output

Disabling blocks an input signal from passing through to an output, replacing it with a fixed value

The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1

When disabled, 0 output When disabled, 1 output

XFEN

(a)

ENX

F

(b)

EN = 0


Chap 4

73

Decoding - the conversion of an n-bit input code to an m-bit output code withn m 2n such that each valid code word produces a unique output code

Circuits that perform decoding are called decoders

Here, functional blocks for decoding are called n-to-m line decoders, where m 2n, and generate 2n (or fewer) minterms for the n input

variables

Decoding


Chap 4

74

1-to-2-Line Decoder

2-to-4-Line Decoder

Note that the 2-4-line ismade up of 2 1-to-2-line decoders and 4 AND gates.

Decoder ExamplesA D0 D1

0 1 01 0 1

(a) (b)

D1 5 AA

D0 5 A

A 1

0011

A 0

0101

D 0

1000

D 1

0100

D 2

0010

D 3

0001

(a)

D 0 5 A 1 A 0

D 1 5 A 1 A 0

D 2 5 A 1 A 0

D 3 5 A 1 A 0

(b)

A 1

A 0


Chap 4

75

EN

A 1

A 0D0

D1

D2

D3

(b)

EN A1 A0 D0 D1 D2 D3

01111

X0011

X0101

01000

00100

00010

00001

(a)

Decoder with Enable


Chap 4

76

Decoder Expansion

3-to-8-line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal

2-to-4-line decoder 1-to-2-line decoder

2-to-4-line decoder Number of output ANDs = 4 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal

Two 1-to-2-line decoders


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Decoder Expansion

Result

3-to-8 Line decoder

1-to-2-Line decoders

4 2-input ANDs 8 2-input ANDs

2-to-4-Linedecoder

D0A 0

A 1

A 2

D1

D2

D3

D4

D5

D6

D7

000

001

010

011

100

101

110

111


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Decoder Expansion

Using two 2-to-4 decoders with enable


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Combinational Circuit Design by Decider Implement m functions of n variables with:

Sum-of-minterms expressions One n-to-2n-line decoder m OR gates, one for each output

Approach 1: Find the truth table for the functions Make a connection to the corresponding OR from

the corresponding decoder output wherever a 1 appears in the truth table

Approach 2 Find the minterms for each output function OR the minterms together


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Decoder and OR Gates Example

Design a binary adder by decoderS(X,Y,Z) = m(1,2,4,7)C(X,Y,Z) = m(3,5,6,7)


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Decoder and OR Gates Example Implement the following set of odd parity functions of

(A7, A6, A5, A3)P1 = A7 A5 A3P2 = A7 A6 A3P4 = A7 A6 A5

Finding sum ofminterms expressionsP1 = m(1,2,5,6,8,11,12,15)P2 = m(1,3,4,6,8,10,13,15)P4 = m(2,3,4,5,8,9,14,15)

Find circuit Is this a good idea?

+++

+++

0123456789

101112131415

A7A6A5A4

P1

P4

P2


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Encoding Encoding - the opposite of decoding - the conversion

of an m-bit input code to a n-bit output code with n m 2n such that each valid code word produces a unique output code

Circuits that perform encoding are called encoders An encoder has 2n (or fewer) input lines and n output

lines which generate the binary code corresponding to the input values

Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.


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Octal-to-Binary Encoder

76542

76321

75310

DDDDADDDDADDDDA


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Decimal-to-BCD Encoder

A decimal-to-BCD encoder Inputs: 10 bits corresponding to decimal

digits 0 through 9, (D0, , D9) Outputs: 4 bits with BCD codes Function: If input bit Di is a 1, then the

output (A3, A2, A1, A0) is the BCD code for i, The truth table could be formed, but

alternatively, the equations for each of the four outputs can be obtained directly.


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Decimal-to-BCD Encoder

Input Di is a term in equation Aj if bit Aj is 1 in the binary value for i.

Equations:A3 = D8 + D9A2 = D4 + D5 + D6 + D7A1 = D2 + D3 + D6 + D7A0 = D1 + D3 + D5 + D7 + D9

F1 = D6 + D7 can be extracted from A2 and A1. Is there any cost saving?


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Priority Encoder

If more than one input value is 1, then the encoder just designed does not work.

One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.

Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.


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Priority Encoder Example I

3210

321

2130

DDDDVDDADDDA


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Priority Encoder Example II

No. of Min-terms/Row

Inputs Outputs

D4 D3 D2 D1 D0 A2 A1 A0 V0 0 0 0 0 0 X X X 01 0 0 0 0 1 0 0 0 12 0 0 0 1 X 0 0 1 14 0 0 1 X X 0 1 0 18 0 1 X X X 0 1 1 1

16 1 X X X X 1 0 0 1


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Priority Encoder Example II (continued)

Could use a K-map to get equations, but can be read directly from table and manually optimized if careful:A2 = D4A1 = D3 + D2 = F1, F1 = (D3 + D2)A0 = D3 + D1 = (D3 + D1)V = D4 + F1 + D1 + D0

D4 D3D4 D4D4 D3D4 D2 D4 D2


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Selecting of data or information is a critical function in digital systems and computers

Circuits that perform selecting have: A set of information inputs from which the selection

is made A single output A set of control lines for making the selection

Logic circuits that perform selecting are called multiplexers

Selecting can also be done by three-state logic or transmission gates

Selecting


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Multiplexers

A multiplexer selects information from an input line and directs the information to an output line

A typical multiplexer has n control inputs (Sn 1, S0) called selection inputs, 2ninformation inputs (I2n 1, I0), and one output Y

A multiplexer can be designed to have minformation inputs with m 2n as well as n selection inputs


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2-to-1-Line Multiplexer

Since 2 = 21, n = 1 The single selection variable S has two values:

S = 0 selects input I0 S = 1 selects input I1

The equation:Y = I0 + SI1

The circuit:S

S

I0

I 1

DecoderEnablingCircuits

Y


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2-to-1-Line Multiplexer (continued)

Note the regions of the multiplexer circuit shown: 1-to-2-line Decoder 2 Enabling circuits 2-input OR gate

To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a (2,1)AND-OR circuit:

1-to-2-line decoder (2,1) AND-OR

In general, for an 2n-to-1-line multiplexer: n-to-2n-line decoder (2n,1) AND-OR


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Example: 4-to-1-line Multiplexer

2-to-22-line decoder (22,1) AND-OR

S1Decoder

S0

Y

S1Decoder

S0

Y

S1Decoder

4 3 2 AND-ORS0

Y

I2

I3

I 1

I 0D0

D1

D2

D3

4x1Mux


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Multiplexer Width Expansion

Select vectors of bits instead of bits

Example:quadruple 2-to-1 linemultiplexer

Consist of 4 2-to-1 muxs.


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Combinational Circuit Design by MUX

F = Z

F = 0

F = 1

F = Z

Implement F(X,Y,Z) = m(1,2,6,7)


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Combinational Circuit Design by MUX Implement F(A,B,C,D) = m(1,3,4,11,12,13,14,15)

F = D

F = D

F = D

F = D

F = 0

F = 0

F = 1

F = 1


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Demultiplexer

Demultiplexer Inverse operation of multiplexing. Receive information from a single line and transmit it

to one of 2n possible output lines.Decoder with enable input

2004 Pearson Education, Inc. Modified by Y. L. Li, CS/NCTU Logic & Computer Design Fundamentals

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