Lattice Verilog Training Part II Jimmy Gao

© LATTICE SEMICONDUCTOR CORPORATION

Verilog TrainingFeb. 19981

Lattice Verilog Training

Part II

Jimmy Gao



Lattice Specific Design

by Verilog



Global OE PolarityGlobal OE

Lattice Single Global OE CPLD Architecture

Multi-Polarity OEs Design not fit for Single-OE

Lattice CPLD Architecture; All Global OE must has the same Polarity

assign q1 = oe1? qint1 : 8’bZZZZZZZZ;

// q2 = (!oe2)? qint2 : 8’bZZZZZZZZ;assign q2 = oe1? qint2 : 8’bZZZZZZZZ;

GLB # 0

GLB # 16



Lattice Specific - Global OE

• For Lattice 1K, 2K, 3K and 6K single Global OE architecture device, simply lock the OE signal to the Global OE pin in the Fitter in order to use the Global OE available in the CPLD.

• If the OE controls several different outputs in the design, ensure that the polarity of OE controls are the same and identical to the polarity of Global OE in the Lattice CPLD.



Global Reset Polarity

reset

Lattice Single Global Reset CPLD Architecture

Multi-Polarity Resets Design not fit for Single-Reset Lattice CPLD Architecture. All Global reset must has the same polarity.

always @ (posedge clk or posedge reset) begin

if ( reset)qint1 = 8’h00;

else if ( clk )qint1 = d;

end

// wire reset = ! input_reset;// Negative Asserted Reset

always (posedge clk or posedge reset ) begin

if ( reset )qint2 = 8’h00;


end

GLB # 0

GLB # 16



Lattice Specific - Global Reset

• To use the Global Reset pin in the Lattice 1K, 2K, 3K and 6K CPLD, ensure that ALL reset signals in the ENTITY have the same reset name.

• Keep in mind that ALL registers have implied resets that connect to the Global Reset pin. If you specify a reset signal in your design, then you need to specify a reset signal for EVERY register and latch used. Otherwise, the Fitter will assign it to a PT reset.

• In the Fitter, you must specify to “use Global Reset”



Global Reset and PT Reset

Global resetLattice CPLD PT Reset and Global Reset

Lattice CPLD Architecture has both PT reset and Global reset.

always @ (posedge clk ) begin

qint1 = d;// Tired to Default Global Reset

end

always (posedge clk or posedge reset ) begi

if ( reset )qint2 = 8’h00;


end

GLB # 0

GLB # 16

PT reset

“reset” is PT reset if it not assigned to Global reset.

“reset” can be assigned to Global reset in the fitter.



Lattice Specific - Lattice Macros

• Lattice Macros are “hard” macros, which are optimized to the CPLD architecture and will give the best area utilization and best speed performance.

• Verilog synthesis, without the use of Lattice Macros, will produce functionally correct models. However, may not yield optimum performance.

• Lattice Verilog Macros Library for Synplicity Design

File Lattice .v is located in the <synplcty>\lib\cpld directory



Lattice Specific - Wide XORs// This design example shows 8-input XOR gatemodule widexor(a, yout);

input [7:0] a;output yout;

assign yout = a[0]â[1]â[2]â[3]â[4]â[5]â[6]â[7];endmodule

// include the Lattice Verilog Library // c:\synplcty\lib\cpld\lattice.v in the synthesizing list// refer to Lattice Hard Macro XOR8

// module XOR8(Z0,A0,A1,A2,A3,A4,A5,A6,A7); //synthesis black_box

// input A0, A1, A2, A3, A4, A5, A6, A7; output Z0; endmodule

module widexor(a, yout);input [7:0] a;output yout;

XOR8 x1(yout, a[0],a[1],a[2],a[3],a[4],a[5],a[6],a[7]);endmodule

• The above design works, but uses 2 GLB levels. Using the Lattice “hard” Macro for an 8-input XOR gate (xor8) results in 1 GLB level.



Lattice Specific - IO Cell as a Register• Verilog file is similar to any Register descriptionmodule ioreg (…); …………

always @ (posedge clka or posedge rset)begin

if (rset ) qout = 1’b0;

else begin if (clka)

qout = qin; end

end

endmodule

• A “property file” is created to direct the Register to the IO Cell and is used in the Fitter

# This is a property file to go with a Verilog design with entity IOREG# It assigns a register to a IO Cell Register# The instance name “qoutFD21” is taken from the EDIF netlist

PROPERTY IOREG INST qoutFD21 REGTYPE IOC ENDPROPERTY

(edif IOREG (edifVersion 2 0 0) (edifLevel 0) ……………… (instance qoutFD21 (viewRef prim

(cellRef FD21 (libraryRef lattice))))

………………



Lattice Specific - IO Cell as a Register

• Verilog file is similar to any Register descriptionUse Lattice Hard Macro “ID21”.// module ID21 (Q0, XI0, CLK);// output Q0;// input XI0, CLK;// endmodule

module ioreg (qout, qin, clock); output qout; input qin, clock;

ID21 reg1 (.Q0(qout), .XI0(qin), .CLK(clock));

endmodule

• Use Lattice input register hard macro ID11, ID14, ID18, ID21, ID24 and ID28 to implement the IO Cell register.



Lattice Specific - Input Reg or Bi-directional Input Reg

D Q

XB0

A

OE

CLK

D Q

CLK

XI0

Bi-Directional Input Register

BIID11, BIID14, …. BIID88

Input RegisterID11, ID14, … ID28

module BIID11 ( Q0, XB0, A, CLK, OE);

inout XB0;

input A, CLK, OE;

output Q0;

endmodule

module ID11 ( Q0, XI0, CLK);

input XI0, CLK;

output Q0;

endmodule

Q0

Q0



Lattice Specific - IO Cell as a Latch

• Verilog file is similar to any D-type Latch descriptionUse Lattice Hard Macro “IL21”.// module IL21 (Q0, XI0, G);// output Q0;// input XI0, G;// endmodule

module iolatch (qout, qin, le); output qout; input qin, le;

IL21 Latch1 (.Q0(qout), .XI0(qin), .G(le));

endmodule

• Use Lattice input latch hard macro IL11, IL14, IL18, IL21, IL24 and IL28 to implement the IO Cell Latches.



Lattice Specific - Input Latch or Bi-dir Input Latch

D Q

XB0

A

OE

G

D Q

G

XI0

Bi-Directional Input Latch

BIIL11, BIIL14, …. BIIL88

Input LatchIL11, IL14, … IL28

module BIIL11 ( Q0, XB0, A, G, OE);

inout XB0;

input A, OE, G;

output Q0;

endmodule

module IL11 ( Q0, XI0, G);

input XI0, G;

output Q0;

endmodule

Q0

Q0



Lattice Specific - Pin Numbers

• Pin numbers can be assigned in a PIN file (.ppn) or a PROPERTY file (.prp) or directly in the Fitter.

• PIN file is attached to the design during compilation with the Lattice fitter.

• PIN file syntax:<pin_name> <pin_direction> <pin_number>

• Example of PIN file (example.ppn) :oe out 15

clk in 21enable in 7bus0 bidi 2bus1 bidi 3bus2 bidi 4



Lattice Specific - Pin Numbers (cont’d)

• PROPERTY file is attached to the design in the Fitter

• PROPERTY file syntax:PROPERTY <cell_name> PIN <pin_name> LOCK <pin_number> ENDPROPERTY

• PROPERTY file example (example.prp) :

PROPERTY mux PIN A0 LOCK 7 ENDPROPERTYPROPERTY mux PIN A1 LOCK 21 ENDPROPERTYPROPERTY mux PIN A2 LOCK 22 ENDPROPERTYPROPERTY mux PIN B0 LOCK 32 ENDPROPERTYPROPERTY mux PIN B1 LOCK 2 ENDPROPERTYPROPERTY mux PIN B2 LOCK 3 ENDPROPERTYPROPERTY mux PIN clk2 LOCK 10 ENDPROPERTY



Synplicity/Lattice Specific Design Attributes• Pin/Port Attribute

Example:

module demo ( sysioclk, rst, I, …);

//Set IO Cell Clock

input sysioclk; /* synthesis clk=ioclk0 */

input rst;

input [0:1] I;

…………

…………

endmodule

sysioclk

Signal Attribute: clk=“ioclk0”



Synplicity/Lattice Specific Design Attributes• Symbol Attribute

module demo (………);

………

wire [0:1] iregs_bk;

…………

// Lock Registers as IO Cell Registers

FD21 u_ioclk0(iregs_bk(0),i(0),sysioclk,clr); /*synthesis regtype=ioc*/

FD21 u_ioclk1(iregs_bk(1),i(1),sysioclk,clr); /*synthesis regtype=ioc*/

… …

endmodule

u_ioclK0

u_ioclK1

Symbol Attribute: Regtype=“IOC”

Symbol Attribute: Regtype=“IOC”



Lab Three - Input Registers & Property File

Please Turn to your Verilog Lab Book for the Verilog Design Lab No. Three



Lattice Attributes

& Property File



External Pin Attributes

Attribute Type Attribute Value Attribute Description

CRIT (none) Assign ORP Bypass tobe used for specifiedoutputs.

LOCK PIN_NUMBER Assigns device I/O pinsto signal names.

OPENDRAIN ON Assigns specificoutputs to use opendrain.

PULLUP ON Assigns specific IOCsto use pullup.

SLOWSLEW ON Assigns specificoutputs to use slowslew rate.



Net Attributes

Attribute Type Attribute Value Attribute Description

CLK CLK0/CLK1/CLK2/IOCLK0/IOCLK1/FASTCLK/SLOWCLK

Assigns clock signals tospecific clock lines of GLBsor IOCs.

GROUP GROUP_NAME Identifies GLB outputs whichare to be grouped togetherwhen forming GLBS.

PRESERVE (NONE) Prevents removal of a logicnet during minimization andforces the net to a GLB or IOCoutput.

SAP/EAP PATH_NAME Specifies the Start and End ofan Asynchronous Path.

SCP/ECP PATH_NAME Specifies the Start and End ofa Critical Path.

SNP/ENP PATH_NAME Specifies the Start and End ofa No-Minimize Path.



Symbol or Instance Attributes

AttributeType

Attribute Value Attribute Description

OPTIMIZE ON Allows the compiler tooptimize a hard macro bychanging it to a softmacro.

PROTECT (none) Prevents removal of aprimitive duringminimization.

REGTYPE GLB/IOC Determines whether aregister is placed in a GLBor IOC.

LXOR2 (none) Enforces implementationof a two-input exclusive-orfunction using a hardware,two-input exclusive-or.



Pin Attribute in Property File

• CRIT

PROPERTY cell_name PIN pin_name CRIT ENDPROPERTY

• LOCK

PROPERTY cell_name PIN pin_name LOCK pin_number ENDPROPERTY

• PULLUP

PROPERTY cell_name PIN pin_name PULLUP ON ENDPROPERTY

• OPENDRAIN

PROPERTY cell_name PIN pin_name OPENDRAIN ON ENDPROPERTY

• SLOWSLEW

PROPERTY cell_name PIN pin_name SLOWSLEW ON ENDPROPERTY



Net Attributes in Property File

• CLK

PROPERTY cell_name NET net_name CLK CLK0|CLK1|CLK2|IOCLK0|IOCLK2|FASTCLK|SLOWCLK ENDPROPERTY

• GROUP

PROPERTY cell_name NET net_name GROUP group_name ENDPROPERTY

• PRESERVE

PROPERTY cell_name NET net_name PRESERVE ENDPROPERTY

• SAP/EAP

PROPERTY cell_name NET net_name SAP path_name ENDPROPERTY

PROPERTY cell_name NET net_name EAP path_name ENDPROPERTY

• SCP/ECP

PROPERTY cell_name NET net_name SCP path_name ENDPROPERTY

PROPERTY cell_name NET net_name ECP path_name ENDPROPERTY

• SNP/ENP

PROPERTY cell_name NET net_name SNP path_name ENDPROPERTY

PROPERTY cell_name NET net_name ENP path_name ENDPROPERTY



Symbol or Instance Attributes in Property File

• OPTIMIZE

PROPERTY cell_name INST instance_name OPTIMIZE ON ENDPROPERTY

PROPERTY cell_name SYM OPTIMIZE ON ENDPROPERTY

• PROTECT

PROPERTY cell_name INST instance_name PROTECT ENDPROPERTY

PROPERTY cell_name SYM PROTECT ENDPROPERTY

• REGTYPE

PROPERTY cell_name INST instance_name REGTYPE GLB|IOC ENDPROPERTY

PROPERTY cell_name SYM REGTYPE GLB|IOC ENDPROPERTY

• LXOR2

PROPERTY cell_name INST instance_name LXOR2 ENDPROPERTY

PROPERTY cell_name SYM LXOR2 ENDPROPERTY



State Machine Design Example



State Machine Example

idle

ready bus_id=8’hF3?

ready

ready

ready

write

decision

read1

read2

read3

read4

ready.burst

ready.burst

read_writeread_write



State Machine Example

//state machine example

module exstate(clock,rst,bus_id,ready,read_write,burst,next_state);

input clock, rst, ready, read_write, burst;

input [7:0] bus_id;

output [7:0] next_state;

reg [7:0] next_state;

parameter // these parameters represent state names and state encoding

// The state encoding style is one-hot encoding

idle = 8’h01,

decision = 8’h02,

read1 = 8’h04,

read2 = 8’h08,

read3 = 8’h10,

read4 = 8’h20,

write = 8’h40;



State Machine Example(cont'd)

always@(posedge clock or posedge rst)

begin

if (rst)

next_state = idle;

else

begin

case (next_state)

idle: if (bus_id == 8’b11110011)

next_state = decision;

else

next_state = idle;

decision:if (read_write == 1’b1)

next_state = read1;

else

next_state = write;

read1: if (ready == 1’b1 && burst == 1’b0) next_state = idle;

else if (ready == 1’b1 && burst == 1’b1) next_state = read2;

else

next_state = read1;



State Machine Example(cont'd)

read2: if (ready == 1’b1)

next_state = read3;

else

next_state = read2;


next_state = read4;

else

next_state = read3;


next_state = idle;

else

next_state = read4;

write: if (ready == 1’b1)

next_state = idle;

else

next_state = write;

default: next_state = idle;

endcase

end // end Else block

end // end always block

endmodule



State Encoding

parameter

Idle= xx, Decision= xx, Read= xx, Write= xx;

State Name Binary Gray One Hot

Idle 2’b00 2’b00 4’b1000

Decision 2’b01 2’b01 4’b0100

Read 2’b10 2’b11 4’b0010

Write 2’b11 2’b10 4’b0001



CPLD Optimization - State Encoding

• Many FPGA Verilog implementations use “one-hot” encoding. “One-hot” uses a register for each device state (state-per-bit), with only one register active (or “hot”) at a time.

• Use “maximal” encoding for CPLDs it is typically faster and results in better device utilization

• Don’t leave optimization solely to your tools; understand your device-architecture characteristics and tailor your design accordingly



CPLD Optimization - State Encoding (cont’d)

• Many tool sets, both silicon-vendor-supplied and third-party-developed support not only Mealy and Moore but also “one-hot” state-machine generation.

• Some tools automatically select an optimum state machine in response to your circuit implementation, guidance, or both (for example, prioritizing performance to the compiler), whereas other tools always default to one method unless you override them



CPLD Optimization - Undefined States

• When all values are not explicitly defined, synthesis results may be unexpected.

• Whether using if-else or case statements, not defining all possible values or states can result in unwanted “Latches”

Example:parameter // these parameters represent state names

idle = 3’b000, decision = 3’b001, read1 = 3’b010,

read2 = 3’b011, read3 = 3’b100, read4 = 3’b101,

write = 3’b110;

Binary Encoding:

Idle Decision Read1 Read2 Read3 Read4 Write

3b’000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110

Undefined State: 3’b111 Action: Use else or Default



Lab Four - State Machine Design, GDX Design & Design Projects

Please Turn to your Verilog Lab Book for the Verilog Design Lab No. Four



More on Verilog



initial block

initial block : The sequential block similar to always block

syntax: initial begin

<statements>; end

initial block is executed only once in simulation, but always block is executed all the time.

• initial block is used in Verilog Simulation Test Bench.



Loops - While, For, Repeat, Forever

• All loop statements must be grouped inside the always or initial block.

integer counter; integer count;

initial initialbegin count = 0; begin

while ( count < 128 ) for(count=0; count <128; count = count+1) // execute loop till 127. begin // Exit at count 128 $display(“count =%d”, count); begin end

$display(“count = %d”, count); end end

end

While Loop For Loop



Loops - While, For, Repeat, Forever

• All loop statements must be grouped inside the always or initial block.

integer counter; reg clock;

initial initialbegin count = 0; begin

repeat ( 128) clock = 1’b0; // execute loop 128 times. forever #10 clock = ~clock; begin $display(“count = %d”, count); end end

end

Repeat Loop Forever Loop



Task

• Commonly used Verilog routine that is defined in a Verilog module and also local to the module.

• Task can pass multiple values through output and inout argument.

module operation; …………. reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR;

always @( A or B ) begin // invoke the task bitwise_oper

bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end …………… //define Task bitwise_oper task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; // outputs from the task input [15:0] a, b; // input to the task begin

#10 ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask……………..endmodule

bitw

ise_

oper

a[15:0]

b[15:0]

ab_and[15:0]

ab_or[15:0]

ab_xor[15:0]

Task



Function

• Commonly used Verilog routine that is defined in a Verilog module and also local to the module.

• Function always return a single value.

module parity; …………. reg [31:0] addr; reg parity;

always @( addr ) begin // invoke the function calc_parity twice

parity = calc_parity(addr);$display(“Parity calculated= %b”, calc_parity(addr));

end …………… //define Function calc_parity function calc_parity; input [31:0] address; begin // return the xor of all address bits.

calc_parity = ^address; end endfunction……………..endmodule

ca

lc_p

arit

y

address[31:0] parity

Function



Verilog

Compiler Directive



`timescale

• Use to define time delay values by using certain time unit in Verilog Simulation.

• Format: `timescale <reference_time_unit> / <time_precision>

• Example://Define a time scale for the module dummy_test_bench//Reference time unit is 100 nanoseconds and precision is 1 ns`timescale 100 ns / 1 ns

module dummy_test_bench;reg toggle; wire clk_out;

clk_bk myclk (.clkin(toggle), .clkout(clk_out); initial toggle = 1’b0; always #5 // Flip toggle every 5 time units toggle = ~toggle; // 5 time units = 500 ns = 0.5 usendmodule



`define

• Use to define text macro in Verilog like `define <macro_name>. • The Verilog Compiler substitutes the text of the macro wherever it

encounters a `<macro_name>.

• Example: // define text marco

`define WORD_SIZE 32`define WORD_REG reg [31:0]

module dummy (d, clk, myreg32); input [`WORD_SIZE - 1 : 0] d; // declare d[32-1:0] input clk; output [`WORD_SIZE - 1 : 0] myreg32; // declare myreg[32-1:0]

`WORD_REG myreg32; // reg [31:0] myreg32;

always @ ( posedge clk ) myreg32 = d;

endmodule



`include

• Allows to include entire contents of a Verilog source file in another Verilog file during compilation.

• Example:

module clk_bk (clkin, clkout); input clkin; output clkout;

assign clkout = ~clkin;endmodule

`include “c:\test\clk_bk.v” // use file clk_bk.v`timescale 100 ns / 1 nsmodule dummy_test_bench;

reg toggle; wire clk_out; clk_bk myclk (.clkin(toggle), .clkout(clk_out); initial toggle = 1’b0; always #5 toggle = ~toggle;endmodule

File C:\test\clk_bk.v

File C:\test\tstbch.v



Conditional Compilation Directive

• Conditional Compilation Directive: ìfdef èlse èndif

• Use to specify that the particular portion of the source code be compiled only if a certain flag is set.

• Example:

`define TEXT

ìfdef TEXT module test1 ……….endmodule

èlsemodule test2 ……….endmodule

èndif



Verilog Simulation



pDS+ Viewlogic Verilog Simulation Flow Example

Verilog

Verilog Synthesizer

ispDS+ Fitter

ViewLogic VCSi Verilog

Simulator

EDIF

Verilog

.JED

Verilog Test Bench

Verilog Test Bench

Behavior Verilog Simulation

Gate Level Verilog Netlist Timing Simulation



• Simulation Goals

Debug Verilog source

Verify performance of CPLD implementation

• Two Stages of Simulation:

Register transfer level Verilog functional simulation

• (Design Entry Level)

Gate-level Verilog timing Simulation

• (Post-fitting Gate-level)

• Simulation Goals

Debug Verilog source

Verify performance of CPLD implementation

• Two Stages of Simulation:

Register transfer level Verilog functional simulation

• (Design Entry Level)

Gate-level Verilog timing Simulation

• (Post-fitting Gate-level)

Simulation



Simple Verilog test-bench

Stimulus block is the top-level block

Stimulus block drives signals in design block

Sophisticated Verilog test-bench

Top-level block instantiates both Stimulus block & Design block

Stimulus block interacts with design block through interface

Simple Verilog test-bench

Stimulus block is the top-level block

Stimulus block drives signals in design block

Sophisticated Verilog test-bench

Top-level block instantiates both Stimulus block & Design block

Stimulus block interacts with design block through interface

Verilog Functional Simulation & Verilog TestBench

(Stimulus Block) Verilog Test-Bench

(Design Block)

Verilog Design to be verified

Stimulus

(Top-Level Block) Verilog TestBench

(Design Block)

Verilog Design to be verified

(Stimulus Block)



Verilog Design “my_design”to be verified:

module my_design ( a, b, x, y); output x, y; input a, b;

// module items assign x = a & b; assign y = a | b;

endmodule

Verilog TestBench Concept

x

y

a

b

my_design

a

b

x

y

test_my_design



`timescale 100 ns / 1 nsmodule test_my_design;

reg a, b; wire x, y;

my_design dut (.a(a),.b(b),.x(x),.y(y));

initial a = 1’b0;

always #50 a = ~a;

always begin #75 b = 1’b1; #25 b = 1’b0; end endmodule

Verilog TestBench Concept - Cont’d

•Verilog module without interface

•Test-bench block registers/wires declaration

•instantiates design block under test bench

•Initialize registers

a

b



`timescale 100 ns / 1 nsmodule test_my_design;

reg a, b;

……………

initial a = 1’b0;

always #50 a = ~ a;

always begin #75 b = 1’b1; #25 b = 1’b0; end

endmodule

• Constant on/off delay

• Variable on/off delay

• Constant on/off delay

• Variable on/off delay

Verilog TestBench - Waveform Generation

a

b

50 100



`timescale 100 ns / 1 nsmodule testbench;

reg [7:0] A_BUS;

……………

initial begin

#10 A_BUS = 8’h00;#10 A_BUS = 8’h01;

end

endmodule

Verilog TestBench - Relative Timing Stimulus

00000000 00000001

10 20 30



`timescale 100 ns / 1 nsmodule testbench;

reg [7:0] A_BUS;

……………

initial begin

#10 A_BUS <= 8’h00;#20 A_BUS <= 8’h01;

end

endmodule

Verilog TestBench - Absolute Timing Stimulus

00000001 00000010

10 20 30



System Tasks

and Verilog Simulation



System Tasks for displaying information

• $display; $write

For displaying values of variables or strings or expressions.

Format: $display ( p1, p2, ….. p3); where p# can be quoted strings or variables or expression. Same as $write.

Display Format:• %d or %D Display variable in decimal• %b or %B Display variable in binary• %s or %S Display string• %h or %H Display variable in hex• %c or %C Display ASCII Character• %m or %M Display hierarchical name (no argument required)• %v or %V Display strength• %o or %O Display variable in octal• %t or %T Display in current time format• %e or %E Display real number in scientific format (e.g., 3e10)• %f or %F Display real number in decimal format (e.g., 2.13)• %g or %G Display real number in scientific or decimal, whichever is

shorter



System Tasks for displaying information

• $strobing Similar to $display, but provide a synchronization mechanism to ensure that data

is display only after all other assignment statements, which change the data in that time step, have executed.

Format: $strobing ( p1, p2, ….. p3); where p# can be quoted strings or variables or expression. Same display format as $display.

• $monitor For continuously monitoring the values of the variables or signals specified in the

parameter list and displays all parameters in the list whenever the value of any one variable or signal changes.

Format: $monitor ( p1, p2, ….. p3); where p# can be variables, signal names, or quoted strings. Same display format as $display.

• $monitoron enables monitoring

• $monitoroff disables monitoring



System Tasks for timing Control

• $time For getting the current simulation time.

• $stop Puts the simulation in an interactive mode. Used whenever you want to suspend

the simulation and examine the values of signals in the design.

• $finish Terminates the simulation.



Examples// Display bus value in binary reg [3:0] bus;$display(“At time %d, bus value is %b”, $time, bus);// Result: At time 10 bus value is xxxx

// monitor signals of clock, reset and display their value // only when either clock or reset change its valueinitial begin

$monitor(“value of signals clock = %b reset = %b”, clock, reset ); end

// strobing - Displaying value of signal “a” and “c” at the same time // when assignments are executed.always @(posedge clock) begin a = b; c = d; end ;always @(posedge clock) $strobe(“Displaying a = %b, c = %d”, a, c );

// simulation suspension and terminationinitial begin clock = 1’b0; reset = 1’b1; #100 $stop; // suspend the simulation at time = 100 #900 $finish; // terminate the simulation at time = 1000 end



System Tasks for disk file handling

• $fopen Open a disk file. Format1: $fopen (“<name_of_file>”); Format2: <file_handle> = $fopen (“<name_of_file>”);

• $fclose Close a disk file. Format: $fopen (<file_handle>);

• $fdisplay; $fmonitor; $fwrite; fstrobe Used to write to files.



Other System Tasks

• $random For generating a random number.

• $readmemb; readmemh For initializing memories from a data file by reading numbers in binary or

hexadecimal format.

• $dumpvars; $dumpfile; $dumpall For selecting instances or module instance signal, file, even all modules to dump.

• $dumpon; $dumpoff Enable or disable dump process.

• $setup; $hold Used to check the setup and hold constraints for a sequential element in the design.

• $width Used to check the width of a pulse.



Examples`timescale 100 ns / 1 nsmodule vec_gen;integer handle1; integer I; reg Cin; reg [2:0] A, B;reg [2:0] Exp_Sum; reg Exp_Cout;

<Instantiation of Design Module>;

initial begin handle1 = $fopen(“adder3.vec”); for ( I = 0; I <= 19; I = I + 1 ) begin

Cin = $random;A = $random;B = $random;{Exp_Cout, Exp_Sum} = Cin + A + B;$fwrite(handle1, “%b_%b_%b_%b_%b”,

A, B, Cin, Exp_Cout, Exp_Sum); end

$fclose(handle1);end

endmodule



Verilog Simulator Model



Programming Language Interface (PLI)

• The Programming Language Interface (PLI) of Verilog Hardware Design Language provides a set of interface routines to read internal data representation, write to internal data representation, and extract information about the simulation environment.

Verilog has already provides a set of standard system tasks and functions and compiler directives, which we have just discussed, for the Hardware Designers.

To customize the capability of the Verilog language by defining your own system tasks and functions, you can create your own Verilog PLI routines.



Verilog Simulator Model

Verilog Source orVerilog Netlist

Verilog Source orVerilog Netlist

User-defined VerilogStimulus Test BenchUser-defined VerilogStimulus Test Bench

Standard &User-defined System Tasks

Standard &User-defined System Tasks

User-Defined System Task #1User-Defined System Task #1

Verilog CompilationVerilog Compilation

Internal DesignData Structure

Internal DesignData Structure

SimulationSimulation

Simulation outputSimulation output

User-Defined C routine # 1User-Defined C routine # 1

PLI LibraryRoutines

PLI LibraryRoutines


User-DefinedC routine # 2User-DefinedC routine # 2

User-DefinedC routine # 3User-DefinedC routine # 3

PLI Library Routinesto do miscellaneousOperations

PLI Library Routinesto do miscellaneousOperations


PL

I L

ibra

ry

Rou

tine

s

Access internal structures

Pass data

Invoke User-Defined System Task

Invoke user-defined C routine

ArchitectureSpecific Verilog

Library

ArchitectureSpecific Verilog

Library



Back-Annotation of Standard Delay File

Post-layoutTiming Verilog

Netlist

Post-layoutTiming Verilog

Netlist

SDFSDF

User-Defined Verilog Test-Bench:

module ……………….initial begin $sdf_annotate( “<sdf_file>”,

<module_instance>,“<sdf_configuefile>”,“<sdf_logfile>”,“<mtm_spec>”,“<scale_factors>”,“<scale_type>”);

endendmodule

User-Defined Verilog Test-Bench:

module ……………….initial begin $sdf_annotate( “<sdf_file>”,

<module_instance>,“<sdf_configuefile>”,“<sdf_logfile>”,“<mtm_spec>”,“<scale_factors>”,“<scale_type>”);

endendmodule

User-Define PLI Table File:

$sdf_annotate call=sdf_annotate_call acc+=mp,prx:%CELL%

User-Define PLI Table File:

$sdf_annotate call=sdf_annotate_call acc+=mp,prx:%CELL%

Note:

Check VCS Reference Guide Chapter 3 & 4 for Detail about PLI and SDF usage.

Verilog SimulatorVerilog Simulator



Wrapped Up Example

module prep5(Q, CLK, MAC, RST, A, B);output [7:0] Q; input CLK, MAC, RST;input [3:0] A, B; reg [7:0] Q;

wire [7:0] mlt_o = A * B; // Multiplierwire [7:0] adr_o = MAC ? mlt_o + Q : mlt_o; // Adder

// register with asynchronous resetalways @(posedge CLK or posedge RST)begin if (RST) Q = 0;

else Q = adr_o;endendmodule

A[3:0]

B[3:0]

MAC

RST

CLK

Q[7:0]

mlt_o[7:0]adr_o[7:0]



Wrapped Up Example

a[3:0]

b[3:0]

mac

rst

clk

q[7:0]mlt_o[7:0]

adr_o[7:0]

MACA[3:0]

B[3:0]

CLK

RST

Q[7:0]

mac

cntl

ina

inb

outvec

=

test

prep5



Wrapped Up Example timescale 100 ps/100 psmodule test;reg clk, mac, rst; reg [3:0] a, b; wire [7:0] q;

prep5 inst1 (.CLK(clk),.MAC(mac), .RST( rst),.A(a), .B(b), .Q( q));

parameter numvecs = 6; // actual number of vectorsreg [1:0] cntl[0:numvecs-1]; reg [3:0] ina [0:numvecs-1];reg [3:0] inb [0:numvecs-1]; reg [7:0] outvec [0:numvecs-1];integer i; integer numerrors;

initialbegin// sequential test patterns entered at neg edge clk// rst, mac; a, b, q // just before next pos edgecntl[0] = 2'b10; ina[0] = 4'd4; inb[0] = 4'd3; outvec[0] = 8'd0;cntl[1] = 2'b00; ina[1] = 4'd4; inb[1] = 4'd3; outvec[1] = 8'd12;cntl[2] = 2'b00; ina[2] = 4'd10; inb[2] = 4'd3; outvec[2] = 8'd30;cntl[3] = 2'b01; ina[3] = 4'd6; inb[3] = 4'd2; outvec[3] = 8'd42;cntl[4] = 2'b01; ina[4] = 4'd11; inb[4] = 4'd5; outvec[4] = 8'd97;cntl[5] = 2'b11; ina[5] = 4'd10; inb[5] = 4'd3; outvec[5] = 8'd0;end



Wrapped Up Example // set up clk with 1000 ns period; 10000=1000 100ps units=1000 ns period parameter clkper = 10000; initial clk = 1; always begin #(clkper / 2) clk = ~clk; end

reg invec_temp;

initialbegin numerrors = 0;

$display("\nBeginning Simulation..."); //skip first rising edge

@(posedge clk);for (i = 0; i <= numvecs-1; i = i + 1)begin @(negedge clk); // apply test pattern at neg edge

{rst, mac} = cntl[i]; a = ina[i]; b = inb[i];

@(posedge clk) #4500; //450 ns later// check result at posedge + 450 nsif ( q !== outvec[i] )begin $display( "\t\t ERROR pattern#%d t%d: rst, mac=%b

a= %d, b= %d Expected q: %d; Actual q: %d", i, $stime,{rst, mac}, a, b, outvec[i], q);

numerrors = numerrors + 1;end

end



Wrapped Up Example

if (numerrors == 0)

$display("Good! End of Good Simulation.");else

if (numerrors > 1)

$display("%0d ERRORS! End of Faulty Simulation.",numerrors);

else$display("1 ERROR! End of Faulty

Simulation.");

#1000 $finish; // after 100 ns laterend

endmodule



Verilog Simulation Lab

Section 1: Verilog Functional Simulation

Section 2: Verilog Timing Simulation

Please Turn to your Verilog Lab Book for the Verilog Simulation Lab one



Contact: Jeffery, Hawking , Nick

Telephone:0755-3273333

0755-3273550/8/3/4

Mobil:13823378853

E-mail:[email protected]

Lattice Verilog Training Part II Jimmy Gao

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