Latest Update for USB 3.1, Thunderbolt, and Type-C

Jit Lim

USB and Thunderbolt

Keysight Technologies

Jan 12-13, 2016

USB 3.1、Thunderbolt™及Type-C最新進展及測試解決方案

– Type-C Overview

– Type-C PD Solutions

– USB 3.1 Overview

– USB 3.1 Simulation Solutions

– USB 3.1 TX Solutions

– USB 3.1 RX Solutions

– USB 3.1 Cable/Connector Solutions

– Thunderbolt 3 Solutions

– PCB Channel Characterization Solutions

– Summary

Agenda

2

Standards ExpertiseMeet Your Keysight Experts

Memory

Perry Keller

Board of

Directors

JEDEC

Compliance

Chair

UFSA

Computer

Rick Eads

Contributor

PCI-SIG

Optical

Greg

LeCheminant

Contributor

IEEE

HDMI

Stefan

Friebe

Contributor

HDMI

Storage

Matthew

Woerner

Contributor

SATA-IO,

T10 SAS

DisplayPort

Brian Fetz

Contributor

VESA

USB-IF

HDMI Forum

Mobile

Roland

Scherzinger

TSG Member

UniPro Vice

Chair

MIPI Alliance

LPDDR4, UFS PCIe G3, G4 802.3 HDMI 2.0 SAS-3USB 3.1, DP

1.3

D/M/C–PHY,

UniPro

USB

Jit Lim

Contributor

USB-IF

Thunderbolt

USB3.1

Fiber Channel

Joachim Vobis

Contributor

T11 FC

OIF-CEI

Contributor

OIF- CEI, T11-

FC

FCPI, MSQS

OIF-CEI

Steve Sekel

3

Type-C Overview

4

Industry Drivers for Type-C– New form-factor

• Smaller size

• Reversible plug orientation

• Reversible cable direction

– Establishes power delivery

• Scalable charging to 100W

• Power direction, data direction,

Vconn swap

– Enables adoption by other

standards

• ALT mode

• Future scalability

– Legacy Compatibility

• USB 2.0, USB 3.1 Gen 1, BC 1.2

• 5V Vbus start

5

USB Type C-Signal Plan

6

Type-C Power Delivery

7

USB-PD CC Challenges

8

Chapter 5: Physical Layer

• Keysight Infiniium S-Series Oscilloscope

o N2873A Standard Passive Probes for CC and VBUS

• 1147B Current Probe for Load Current

• GRL-USB-PD Power Delivery SW

• USB-PD Coupon(s) from Wilder-Tech or Luxshare-ICT

(USB3.1-C-PDC or TF21-215G USB-PD Coupon)

• GRL-USB-PD-C1 Controller

• Keysight Power Supply and Load

9

Type-C PD Chapter 7

• Chapter 7: Power Supply

- Depending on Power Profile 1-5

- Source or Load Requirements

- Considering explicit Watts and Voltage

10

N7020A Power Rail Probe

Characteristics and Specifications: N7020A Power Rail Probe

Probe Bandwidth (-3dB) 2GHz

Attenuation Ratio 1:1

Offset Range ± 24V

* Input Impedance @ DC 50kΩ +/-2%

Active Signal Range ± 850mV about offset voltage

Probe Noise 10% increase to the noise of the connected oscilloscope

Probe Type Single-ended

Included accessoriesN7021A—Coaxial Probe Head (qty 3) ($175 us)

N7022A –Main Cable ($240)

Maximum non-destructive input voltage +/-30V (DC + peak AC)

Output impedance 50Ω

Cable length N7021A Main Cable: 48”

N7022A Coaxial Probe Head: 8”

Ambient operating temperature Probe Pod: 0 – 40°C,

N7021A main cable, N7022A coaxial probe head: 0 – 85° C

11

N7016A Type-C low speed signal access and control fixture • Acess to CC1, CC2, SBU1, SBU2, VBUS

and GND

• Controls to terminate CC1, CC2

independently (Ra, Rp, Rd)

• Control to load Vconn

• External power for power consumers

• Type C receptacle to plug into other

devices or cables (port 2)

• USB2.0 interface for external control from

application or standalone SW on a PC

12

N8837A USB-PD Protocol Trigger and Decode

• Support for the USB-PD CC

4b/5b BMC encoded protocol.

• On-screen serial decode

synchronized with the serial

waveform

• 4b, 5b or Label display formats

• Unique listing-window view of

data transfer information with an

automatic click and zoom and

column sort.

• Serial packet search with

navigation controls

• Software trigger on search for

orders Sets, Control Packets,

Data Packets, and Errors.

USB 3.1 Overview

14

USB 3.1 Gen1 and Gen2

1

5

• CTS in final stages

• Gen 2, Type-C FYI testing performed in 2 workshops

• Gen 2 and Type-C fixture sets in final evaluation

• Silicon and some DUTs passing with excellent margins

USB 3.1 Compliance Patterns

16

USB3.1 Channel Budget

Host Device

Ic pinsConnector

TypeIc pins

chip chipHost Routing Device routingCable characteristics

Connector

Type

Loss at Nyquist is

identified here.

Channel Models

(s-parameters)

required.

SSS

17

Typical USB 3.1 Link Turn-on Sequence

Power-

up

Rx.

Detect.

Reset

Rx.

Detect.

Active

Polling.

LFPS

Polling.

RxEQ

Polling.

Active

Polling.

Config-

uration

Polling.

Idle

Polling.

Config-

uration

Polling.

Idle

Loop-

back

Loop-

back

warm

reset

warm reset

de-assert

termination

detected

SCD1 LFPS

handshake

TSEQ

transmitted

TS1

received

TS2

receivedif directed

multiple states

LTSSM states:

Comp-

liance

Rx.

Detect.

Reset

Rx.

Detect.

Active

Polling.

LFPS

Polling.

RxEQ

Polling.

Active

Power-

up

Polling.

LFPS

Plus

SCD2 LFPS

handshake

Polling.

LFPS

Plus

Polling.

Port-

match

PHY

Capability

LBPM

handshake

Polling.

Port-

match

Polling.

Port

Config

PHY

Ready

LBPM

handshake

Polling.

Port

Config

18

USB 3.1 Design Simulation

19

Danger of Disparate Compliance Tests…1) from EDAco:

…and 2) from ScopeCo:

Bridging script generates reportDesign and simulate

Prototype in lab

≠

20

USB3.1 Compliance Test BenchRun the Same Keysight Compliance App on Your Simulation and Your

Prototype

Design and simulate…

ADS “Waveform

Bridge”: Script that

writes file format

that ‘scope

compliance app

understands

…then fabricate with confidence…

Physical test bench with prototype Keysight Infiniium

oscilloscope with

compliance app 21

USB 3.1 TX Solutions

22

U7243B Tx Compliance Test SW

23

Type C

receptacleIc pins

chipHost Routing

Ic pinsType C

Receptacle

chipHost Routing

OR

Tx Test Configuration

C cableMathematically Embed

CTLE and DFE

Mathematically Embed

Channel Model + CTLE

and DFE

24

N7015A Type-C Test Fixture

– High speed (TX/RX) and

D+/D- lanes to scope

through coax cables

– N7015A de-embedding

models available and will

be integrated into

compliance applications

and Infiniium baseline

software

– Power and Control

signals to low speed

N7016A fixture though

type C cable

– View SBU1/2 signals

Vbus and CC lines to

N7016A fixture via USB

Type C (plug style) cableHigh speed coax

cables, Matched pairs

for TX2+, TX2-, RX2+,

RX2-

2 pin header for

SBU1 and SBU2 test

points

Type C plug

connection to DUT

(receptacle)

USB2.0 D+

and D-

High speed coax

cables, Matched

pairs for TX1+, TX1-,

RX1+, RX1-

25

N8821A/B USB 3.1 Gen1/Gen2 Protocol Trigger and Decode

• USB 3.1 Gen1 and Gen 2 protocol

decode in less than 30 seconds

• Integrated software-based protocol-level

triggers

• Save time and eliminate errors by

viewing packets at the protocol level

• Use time-correlated views to quickly

troubleshoot serial protocol problems

back to their timing or signal integrity

root cause

USB 3.1 Gen 2 10 Gbps Test Results

27

USB 3.1 RX Solutions

28

Typical USB 3.1 Link Turn-on Sequence

J-BERT’s sequence trigger can be used to trigger scope captures for

each training step very helpful for debugging a trainings sequence

Power-

up

Rx.

Detect.

Reset

Rx.

Detect.

Active

Polling.

LFPS

Polling.

RxEQ

Polling.

Active

Polling.

Config-

uration

Polling.

Idle

Polling.

Config-

uration

Polling.

Idle

Loop-

back

Loop-

back

warm

reset

warm reset

de-assert

termination

detected

SCD1 LFPS

handshake

TSEQ

transmitted

TS1

received

TS2

receivedif directed

multiple states

LTSSM states:

Comp-

liance

Rx.

Detect.

Reset

Rx.

Detect.

Active

Polling.

LFPS

Polling.

RxEQ

Polling.

Active

Power-

up

Polling.

LFPS

Plus

SCD2 LFPS

handshake

Polling.

LFPS

Plus

Polling.

Port-

match

PHY

Capability

LBPM

handshake

Polling.

Port-

match

Polling.

Port

Config

PHY

Ready

LBPM

handshake

Polling.

Port

Config

29

LFPS – SCD1 & SCD2 – tRepeat Modulation

• tRepeat is modulated to express 0

(short) and 1 (long)

• SCD1 0010

SCD2 1101

• LSb first

• SCD1.LFPS (4’b0100), and

SCD2.LFPS (4’b1011)

• SuperSpeed+ identity check

30

1. Measure EH for all three CLBs at -3.1dB de-emphasis (all impairments set to nominal)

2. Select the CLB where EH is closest to 70mV

3. Measure EW vs. de-emphasis and select the de-emphasis value which gives an EW value

as close as possible to 48ps. If necessary change SJ to adjust EW

4. Adjust Vdiff for 70mV EH

Calibration Method for USB3.1 Calibration

45

50

55

60

65

70

75

-5 -4 -3 -2 -1

Measure

d E

ye-H

eig

ht

[mV

]

Set de-emphasis [dB]

Cal_10G_PreEyeHeigth

5.6" CLB

7.1" CLB

8.1" CLB

61 mV

59 mV

68 mV

40

41

42

43

44

45

46

47

48

49

50

-5 -4 -3 -2 -1

Measure

d E

ye-W

idth

[ps]

Set de-emphasis [dB]

Cal_10G_PreEyeWidth

5.6" CLB

-2.2 dB

31

USB 3.1 gen2 10Gb/sUSB 3.1 Type C 23dB Cal Channel

J-BERT

Scope

32

USB 3.1 gen2 10Gb/sUSB 3.1 Type C 14.5dB Test Channel

J-BERT

DUT

33

USB 3.1 gen2 10Gb/sRX Cal Targets

Parameter Min Nominal Max Unit SigTest

Technology Template

Calibration channel 22.5 23 23.5 dB@5GHz N/A N/A

Test 14 14.5 15 dB@5GHz N/A N/A

Vpp800 mV N/A N/A

Pre-shoot 2.1 2.2 2.3 dB N/A N/A

De-emphasis -3.0 -3.1 -3.2 dB N/A N/A

RJ (Random Jitter) 0.9 1.0 1.0 ps RMS usb_3_10gb USB_3_10Gb_Rj_Sj_CAL

SJ (Sinusoidal Jitter)

500kHz

1MHz

2MHz

4MHz

7.5MHz

10MHz

20MHz

33MHz

50MHz

100MHz

4.284

1.827

0.873

0.333

0.153

0.153

0.153

0.153

0.153

0.153

4.76

2.03

0.87

0.37

0.17

0.17

0.17

0.17

0.17

0.17

4.76

2.03

0.87

0.37

0.17

0.17

0.17

0.17

0.17

0.17

UI pp usb_3_10gb USB_3_10Gb_Rj_Sj_CAL

Eye Height 70 (10-6) 70 (10-6) 75 (10-6) mV usb_3_10gb USB_3_10_CP9_RX_CAL_CTLE_N5dB

Eye Width 48 (10-6) 48 (10-6) 50 (10-6) ps usb_3_10gb USB_3_10_CP9_RX_CAL_CTLE_N5dB

34

Loopback Training – USB 3.1 LTS tool• USB Link Training

Suite is a trainings sequence generation tool for USB3.1 Gen1/2

• Easy manipulation of

• SCD1/SCD2/LBPM cycles

• TSEQ count

• TS1 count

• TS2 count

• LFPS parameters adjustment:

• tPeriod, tBurst, tRepeat, tPWM….

• Choice of:

• Power On sequence

• Warm Reset sequence

35

USB 3.1 Gen1/Gen2 Receiver Test Setup

Key capabilities:

• Analysis of coded & retimed data

• Support of 8b/10b and 128b/132b HW coding and decoding as well as HW scrambling

• Generates calibrated stress conditions for RX test (SSC, SJ, RJ, De-emphasis, ISI)

• Emulate LFPS 3-level signals with built-in electrical idle for loopback training and via channel

• Integrated Link Training, Tx Eq, Noise Impairment, Variable ISI, Receiver

Equalizer/Eye Opener

36

JTOL Margining Test Results

37

USB 3.1 Cable and Connector Test Solutions

38

Input the expected worst

case performance of the

transmitter as the “stressed”

signal to the cable

assembly…

New Compliance MethodologyStressed Eye Diagram Analysis of Interconnects

… apply equalization and

evaluate the eye diagram at

the output of the cable

assembly.

Cable

39

New Compliance MethodologyChannel MetricsThere are three signal integrity impairments that impact the end-to-end link

performance: attenuation, reflection and crosstalk.

Reference: USB-IF Technical White Papers http://www.usb.org/developers/docs/whitepapers/

“Methodology Used to Determine SuperSpeed USB 10 Gbps (USB 3.1) - Gen2 Channel and Cable Assembly High Speed Compliance”

The channel metrics represents these three

impairments:

• Insertion loss fit at Nyquist frequency (ILfitatNq)

• Integrated multi-reflection (IMR)

• Integrated crosstalk (IXT)

40

USB 3.1 Cable/Connector Compliance TestTypical Configuration

Test Fixtures•Method of

Implementation (MOI)

document and

instrument setup file are

available for free

download on

Keysight.com

•ENA Mainframe [1]

•E5071C-4D5: 4-port, 300 kHz to 14 GHz

•E5071C-4K5: 4-port, 300 kHz to 20 GHz

•Enhanced Time Domain Analysis Option (E5071C-TDR)

•ECal Module (N4433A)

[1] 20 GHz option is recommended, since the Type-C cable/connector requires measurements up to 15 GHz.

[2] The list above includes the major equipment required. Please contact our sales representative for configuration details.

www.keysight.com/find/ena-tdr_compliance

Fixtures for testing USB 3.1 /

Type-C connectors and cable

assemblies are available for

purchase through Luxshare-ICT.

http://web.luxshare-ict.com/en/

Automated USB Cable and

Connector Test

41

Thunderbolt 3 Solutions

42

– Announced in Q2 2015

– Uses the Type-C connector

– Channel aggregation: two independent 20Gbps links into one logical

40Gbps link

– Supports other standards through ALT mode

– Cost competitive vs mult—chip, discrete, mux solutions

Thunderbolt 3 Overview

43

– PHY testing approach will be similar to Thunderbolt 2

– Tx, Rx, and Return Loss

– Today, customers with Thunderbolt DUTs need to work with their

Intel PAE

– Keysight can help with pre-compliance testing

Testing Methodology

44

Thunderbolt 2/3 Transmitter Test

25GHz BW required for

compliance testing

Silicon 20/80 risetime can be

<15ps

Imaginarium FW

TenLira SW

TCL and Alpine Ridge scripts

Crosstalk generator

Type-C test fixture

Controller for Devices

New preset testing and

optimization for 10.3G and

20.6G

45

Thunderbolt 2/3 Receiver Test

Calibration and testing for 10.3G and

20.6G

Crosstalk generator

Type-C Plug Fixture

Microcontroller

Optimizing preset for BER

Scripts for querying errors in internal

error detector

46

– DUT output PRBS31 on all lanes with SSC turned on

– Setup the Network Analyzer with automated measurements

Thunderbolt 2/3 Return Loss Test

47

PCB Channel Characterization Solutions

48

Signal Integrity Solutions for Type-C PCB Channel Characterization

N5225A PNA Vector Network

Analyzer, 10MHz – 50GHzDCA-X + N1055A Time Domain

Reflectometer, DC-50GHz

N1930B Physical Layer Test System

(PLTS) Analysis Software

• Time Domain

to/from Frequency

Domain conversion

• De-embedding

• Automatic Fixture

Removal (AFR)

49

Summary

50

Keysight USB 3.1 Total Test Solution

Receiver TestTransmitter Test Interconnect Test

DSAV254A

Infiniium

Scope

SW

HW

Fixture

DUT

M8020A J-BERT High-

Performance Serial BERT

N5990A

USB Compliance

Test Software

E5071C ENA Option TDR

U7243B

USB Compliance

Test Software

N7015A/16A

Tx Test Fixture

Cable/Connector

Test Fixture

Tx

Rx Test Fixture

from USB-IF

Tx

RxCable

51

52