Latches, Flip-Flop and Pewaktu (Timer) -...

Latches, Flip-Flop andPewaktu (Timer)

Program Studi T. ElektroFT - UHAMKA

Slide - 8 1

Endy Sjaiful AlimEndy Sjaiful AlimProgram Studi Teknik Elektro

Fakultas TeknikUniversitas Muhammadiyah Prof. Dr. HAMKA

Latches

The output of a latch depends on its current inputs and on itsprevious output and its change of state can happen at any timewhen its inputs change


Slide - 8 2

The output of a latch depends on its current inputs and on itsprevious output and its change of state can happen at any timewhen its inputs change

S-R (Set-Reset) Latch Gated S-R Latch Gated D Latch

S-R Latch


Slide - 8 3

S-R Latch


Slide - 8 4

Negative-OR Equivalent of theNAND gate /S-/R Latch

11

0

1 SET state

When /R is LOW and/S is HIGH


Slide - 8 5

1

10

0 When /R is LOW and/S is HIGH

Q is LOW and thisCondition We call itRESET state

Example:

Determine thewaveform that will beobserved on the Qoutput. Assume that Qis initially LOW


Slide - 8 6

The Gated S-R LatchA gated latch requires an Enable input, EN (G is also used todesignated an enable input). The S and R inputs control thestate to which the latch will go when a HIGH level is applied tothe EN input. The latch will not change until EN is HIGH.


Slide - 8 7

Initially RESET

Truth Table for Gated S-R Latch

S R EN Q Q’

0 0 0 Q Q’ Hold

1 0 0 Q Q’ Hold

0 1 0 Q Q’ Hold

1 1 0 Q Q’ Hold

0 0 1 Q Q’ Hold

1 0 1 1 0 Set

0 1 1 0 1 Reset

1 1 1 0 0 not allowedProgram Studi T. ElektroFT - UHAMKA

Slide - 8 8

S R EN Q Q’

0 0 0 Q Q’ Hold

1 0 0 Q Q’ Hold

0 1 0 Q Q’ Hold

1 1 0 Q Q’ Hold

0 0 1 Q Q’ Hold

1 0 1 1 0 Set

0 1 1 0 1 Reset

1 1 1 0 0 not allowed

The Gated D LatchOnly has one input in addition to EN. This input is called the D (data) input.

-When the D input is HIGH and the EN input is HIGH, the latch will SET.

-When the D input is LOW and EN is HIGH, the latch will RESET.

-Another way, the output Q follows the input D when EN is HIGH


Slide - 8 9

Initially RESET

Edge-Triggered Flip-Flops

Edge-triggered S-R flip-flop Edge-triggered D flip-flop Edge-triggered J-K flip-flop


Slide - 8 10

Edge-triggered S-R flip-flop Edge-triggered D flip-flop Edge-triggered J-K flip-flop

Edge-Triggered Flip-Flop Logic Symbols (Top: PositiveEdge-Triggered; Bottom: Negative Edge-Triggered).


Slide - 8 11

The Edge-Triggered S-R Flip-FlopThe S and R inputs of the S-R flip-flop are called synchronous input because dataon these inputs are transferred to the flip-flop’s output only on the triggering edgeof the clock pulse.


Slide - 8 12

OperationOperation

Operation of a positive edge-triggered S-Rflip-flop


Slide - 8 13

ExampleExample

Example:

Determine the Q and /Q output waveforms of the flip-flop (Assume isinitially RESET)


Slide - 8 14

Exercise:

Determine the Q and /Q output waveforms of the flip-flop (Assume isinitially RESET) and it is a negative edge-triggered device


Slide - 8 15

The Edge-Triggered D Flip-Flop

The D flip-flop is useful when a single data bit (1 or 0) is to be stored.


Slide - 8 16

ExampleExample

Example:

Determine the Q output waveform if the flip-flop starts out RESET


Slide - 8 17

Try This: Determine the Q output for the D flip-flop if the Dinput is inverted

Answer for related question


Slide - 8 18

The Edge-Triggered J-K Flip-FlopThe J-K flip-flop is versatile and is widely used type of flip-flop. Thedifference is that he J-K flip-flop has no invalid state as does the S-R flip-flop.


Slide - 8 19

ExampleExample

Example:

Determine the Q output, assuming that the flip-flop is initially RESET


Slide - 8 20

Exercise:

Determine the Q output, starting in the RESET state.


Slide - 8 21

Asynchronous Preset and ClearInputs

The state of the flip-flop independent of the clock. These preset and clearinputs must both be kept HIGH for synchronous operation.

Active-LOW preset and clear inputs


Slide - 8 22

Active-LOW preset and clear inputs

Example:

Determine the Q output for the inputs shown in the timing diagram. Q isinitially LOW.


Slide - 8 23

SET Toggle RESET

Exercise:

Interchange the /PRE and /CLR waveforms, what will the Q outputlook like?


Slide - 8 24

Flip-Flop Applications

Parallel Data Storage Frequency Division Counting


Slide - 8 25

Parallel Data Storage Frequency Division Counting

Parallel Data StorageA common requirement in digitalsystems is to store several bits ofdata from parallel linessimultaneously in a group of flip-flops.


Slide - 8 26

Frequency Division2n: n is number of flip-flops. Example: 2 flip-flop will divided frequencyby 4 (22)


Slide - 8 27

Example: Develop the fout waveform for the circuit below when the 8kHz square wave input is applied to the clock input of flip-flop A


Slide - 8 28

Counting


Slide - 8 29

The 555 Timer


Slide - 8 30

Monostable (one-shot) operation Astable operation

Monostable (one-shot) operation


Slide - 8 31

ttww=1.1R=1.1R11CC11

Astable operation


Slide - 8 32

Thank YouJangan sangka kita adalah yang terbaikkerana kita belum kecapi kejayaan yangorang lain capai. Penghalang kejayaan

adalah fikiran sendiri, bukan kecacatan ataukekurangan


Slide - 8 33

Jangan sangka kita adalah yang terbaikkerana kita belum kecapi kejayaan yangorang lain capai. Penghalang kejayaan

adalah fikiran sendiri, bukan kecacatan ataukekurangan

Latches, Flip-Flop and Pewaktu (Timer) -...

Documents

Transcript of Latches, Flip-Flop and Pewaktu (Timer) -...