Lark Board REV DATE PAGES DESCRIPTION Development Kit ...€¦ · Development Kit Board for Cyclone...
34
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Doc Name Ver. Date Sheet of Design Review Standardize Authorize 130602 <RevCod 01-Title & Block Diagram B 1 34 Friday, July 11, 2014 Harris Li <review> <authorize> <standardize> Embest Technology Co., Ltd Copyright (c) 2013, Embest Corporation. All Rights Reserved. Title Size Doc Name Ver. Date Sheet of Design Review Standardize Authorize 130602 <RevCod 01-Title & Block Diagram B 1 34 Friday, July 11, 2014 Harris Li <review> <authorize> <standardize> Embest Technology Co., Ltd Copyright (c) 2013, Embest Corporation. All Rights Reserved. Title Size Doc Name Ver. Date Sheet of Design Review Standardize Authorize 130602 <RevCod 01-Title & Block Diagram B 1 34 Friday, July 11, 2014 Harris Li <review> <authorize> <standardize> Embest Technology Co., Ltd Copyright (c) 2013, Embest Corporation. All Rights Reserved. Development Kit Board for Cyclone V SoC FPGA Lark Board DESCRIPTION REV DATE PAGES 12/27/2013 All V1.0 RELEASE MISC LED/BUTTON/RTC/RESET 29 26 27 34 On-Board USB Blaster II PAGE DESCRIPTION 30 CV SoC Powers Decoupling FPGA ADC Sampling FPGA SDI Xcvr HPS Extend IF Power 1.1V/1.8V HPS Gig Ethernet 31 32 Power IN/5V/12V CV SoC Bank 3B/4A/5B/8A CLKs CV SoC Bank 3A/5A/9A Config DDR3 HPS HPS USB PHY/HUB FPGA VGA/HDMI FPGA Camera Power 1.5V/VTT HPS eMMC/TF_Card CV SoC GND FPGA LCD 5 6 FPGA Extend IF HISORY 33 28 I/O Bank Usage Power 2.5V/3.3V PAGE DESCRIPTION 2 PCIe Connector CV SoC Bank 5A/5B/6A/6B CV SoC Bank 3A/3B/4A CV SoC Bank GXB L0/L1/L2 Title & Block Diagram 1 3 4 7 8 CV SoC Bank 7A/7B/7C/7D 9 CV SoC Bank 8A 10 11 12 13 14 15 16 PLLs 17 DDR3 FPGA 18 19 20 21 FPGA ADC Pre-AMP 22 23 24 25 04/15/2014 All V2.0 RELEASE 05/21/2014 All V3.0 RELEASE 07/11/2014 All V3.1 RELEASE
Transcript of Lark Board REV DATE PAGES DESCRIPTION Development Kit ...€¦ · Development Kit Board for Cyclone...
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
01-Title & Block Diagram
B
1 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
01-Title & Block Diagram
B
1 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
01-Title & Block Diagram
B
1 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
Development Kit Board for Cyclone V SoC FPGALark Board DESCRIPTIONREV DATE PAGES
12/27/2013 All V1.0 RELEASE
MISC LED/BUTTON/RTC/RESET
29
2627
34
On-Board USB Blaster II
PAGE DESCRIPTION
30CV SoC Powers
Decoupling
FPGA ADC SamplingFPGA SDI Xcvr
HPS Extend IF
Power 1.1V/1.8V
HPS Gig Ethernet
3132
Power IN/5V/12V
CV SoC Bank 3B/4A/5B/8A CLKs
CV SoC Bank 3A/5A/9A Config
DDR3 HPS
HPS USB PHY/HUB
FPGA VGA/HDMI
FPGA Camera
Power 1.5V/VTT
HPS eMMC/TF_Card
CV SoC GND
FPGA LCD
56
FPGA Extend IF
HISORY33
28
I/O Bank Usage
Power 2.5V/3.3V
PAGE DESCRIPTION
2PCIe Connector
CV SoC Bank 5A/5B/6A/6BCV SoC Bank 3A/3B/4A
CV SoC Bank GXB L0/L1/L2
Title & Block Diagram1
34
78
CV SoC Bank 7A/7B/7C/7D
9
CV SoC Bank 8A
10111213141516
PLLs
17
DDR3 FPGA
181920
21
FPGA ADC Pre-AMP
22232425
04/15/2014 All V2.0 RELEASE05/21/2014 All V3.0 RELEASE07/11/2014 All V3.1 RELEASE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
02-I/O Bank Usage
B
2 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
02-I/O Bank Usage
B
2 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
02-I/O Bank Usage
B
2 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
02-I/O Bank Usage
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_SMBCLKPCIE_SMBDAT
PCIE_TX_C_N0
PCIE_REFCLK_SYN_PPCIE_TX_C_P0 PCIE_REFCLK_SYN_NPCIE_TX_P0
PCIE_TX_N0
PCIE_TX_C_N1PCIE_TX_C_P1PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_C_N2PCIE_TX_C_P2PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_C_N3PCIE_TX_C_P3PCIE_TX_P3
PCIE_TX_N3
PCIE_RX_P0PCIE_PRSNT2_X1
PCIE_PRSNT2_X4
PCIE_RX_N0
PCIE_RX_P1PCIE_RX_N1
PCIE_RX_P2PCIE_RX_N2
PCIE_RX_P3PCIE_RX_N3
PCIE_WAKEn PCIE_PERSTn
PCIE_RX_N[3:0]
PCIE_TX_N[3:0]
PCIE_TX_P[3:0]
PCIE_RX_P[3:0]
PCIE_REFCLK_SYN_PPCIE_REFCLK_SYN_N
PCIE_WAKEn
PCIE_SMBCLKPCIE_SMBDAT
PCIE_PRSNT2_X1
PCIE_PRSNT2_X4
PCIE_PERSTn
12V_EXP 12V_EXP
3.3V_EXP
12V_EXP
3.3V_EXP
3.3V_EXP
3.3V_EXP 3.3V_VDD
12V_EXP 12V_VDD
3.3V_EXP
3.3V_EXP
PCIE_TX_P[3:0]
PCIE_TX_N[3:0]
PCIE_RX_N[3:0]
PCIE_RX_P[3:0]
PCIE_REFCLK_SYN_PPCIE_REFCLK_SYN_N
PCIE_WAKEn
PCIE_SMBDATPCIE_SMBCLK
PCIE_PERSTn
PCIE_PRSNT2_X1
PCIE_PRSNT2_X4
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 V1.0
03-PCIe Connector
B
3 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 V1.0
03-PCIe Connector
B
3 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 V1.0
03-PCIe Connector
B
3 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
03-PCIe Connector
T73T73
C2 100nFC2 100nF
C6 100nFC6 100nF
R3 4.7KR3 4.7K
T72T72
C11
22uF
C11
22uF
C728
22uF
C728
22uF
FB2
180R,FB
FB2
180R,FB
C1 100nFC1 100nF
C16
47uF
C16
47uF
C5 100nFC5 100nF
C14
47uF
C14
47uF
T74T74
C4 100nFC4 100nF
C8 100nFC8 100nF
R5 0RR5 0R
R2 4.7KR2 4.7K
C727
22uF
C727
22uF
FB1
180R,FB
FB1
180R,FB
C729
22uF
C729
22uF
T71T71
KEY
X4
X1
J1
PCIE_X4
KEY
X4
X1
J1
PCIE_X4
+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3_3VB8JTAG_TRSTNB9+3_3VAUXB10WAKE_NB11
RSVD1B12GNDB13PET0PB14PET0NB15GNDB16PRSNT2_N_X1B17GNDB18
PET1PB19PET1NB20GNDB21GNDB22PET2PB23PET2NB24GNDB25GNDB26PET3PB27PET3NB28GNDB29RSVD3B30PRSNT2_N_X4B31GNDB32
PRSNT1_N A1+12V A2+12V A3GND A4
JTAG_TCK A5JTAG_TDI A6
JTAG_TDO A7JTAG_TMS A8
+3_3V A9+3_3V A10
PERST_N A11
GND A12REFCLK+ A13REFCLK- A14
GND A15PER0P A16PER0N A17
GND A18
RSVD2 A19GND A20
PER1P A21PER1N A22
GND A23GND A24
PER2P A25PER2N A26
GND A27GND A28
PER3P A29PER3N A30
GND A31RSVD4 A32
R4 0RR4 0R
C3 100nFC3 100nF
C7 100nFC7 100nF
C13
47uF
C13
47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI0_FPGA_CLK
DDR3_FPGA_DQ20
DDR3_FPGA_DQS_P[3:0]
DDR3_FPGA_CKE
SPI0_FPGA_MOSI
DDR3_FPGA_CLK_P
DDR3_FPGA_DM2DDR3_FPGA_DQ23
DDR3_FPGA_CLK_N
RZQIN
CAM_D7FPGA_I2C1_SCL
DDR3_FPGA_DQ26
CAM_STROBE
DDR3_FPGA_DQ25DDR3_FPGA_DQ24
DDR3_FPGA_DQ2
LCD_PWM
DDR3_FPGA_DQS_P3
USB_RESETn
FPGA_I2C1_SDA
USER_FPGA_PB0
DDR3_FPGA_DQS_N3
DDR3_FPGA_A[14:0]
USB_OEn
DDR3_FPGA_ODT
DDR3_FPGA_DQ1
DDR3_FPGA_CSn
DDR3_FPGA_DQ27
DDR3_FPGA_DQ[31:0]
CAM_HSDDR3_FPGA_DQ0CAM_D9
DDR3_FPGA_DQ30
DDR3_FPGA_DQS_P0LCD_PWR_EN
DDR3_FPGA_CSn
DDR3_FPGA_A12
SPI0_FPGA_CLK
DDR3_FPGA_DQ29
SPI0_FPGA_MOSI
SPI0_FPGA_MISO
USB_RDn
USB_RESETn
DDR3_FPGA_DQS_N0
USB_OEnUSB_RDnUSB_WRn
DDR3_FPGA_RASn
BL_PWR_EN
DDR3_FPGA_CASn
USB_WRn
SPI0_FPGA_MISO DDR3_FPGA_ODT
DDR3_FPGA_DQ28
DDR3_FPGA_A13
DDR3_FPGA_WEn
DDR3_FPGA_BA0
DDR3_FPGA_DQ3
DDR3_FPGA_DM3
SPI0_FPGA_CSn1
DDR3_FPGA_A10
DDR3_FPGA_WEn
DDR3_FPGA_DQ6
DDR3_FPGA_A11
DDR3_FPGA_DQ31
DDR3_FPGA_BA1
DDR3_FPGA_DQ4DDR3_FPGA_DM0DDR3_FPGA_DQ7DDR3_FPGA_DQ10
DDR3_FPGA_DQ9
DDR3_FPGA_A8
DDR3_FPGA_DQ8
USB_DATA0
TSP_FPGA_INTn
DDR3_FPGA_BA2
DDR3_FPGA_A14
DDR3_FPGA_CLK_PUSB_DATA1
SPI0_FPGA_CSn0
DDR3_FPGA_A9
DDR3_FPGA_CLK_N
DDR3_FPGA_RASn
USB_DATA2
DDR3_FPGA_DM[3:0]
DDR3_FPGA_A6
DDR3_FPGA_DQS_P1DDR3_FPGA_DQS_N1
DDR3_FPGA_DQ11DDR3_FPGA_DQ14DDR3_FPGA_CKEDDR3_FPGA_DQ13
USB_DATA3
DDR3_FPGA_A7
DDR3_FPGA_DQ12DDR3_FPGA_DM1DDR3_FPGA_DQ15DDR3_FPGA_DQ18
DDR3_FPGA_DQ17DDR3_FPGA_DQ16
USB_DATA4
DDR3_FPGA_A4DDR3_FPGA_DQS_P2DDR3_FPGA_DQS_N2DDR3_FPGA_RESETnDDR3_FPGA_DQ19DDR3_FPGA_DQ22
DDR3_FPGA_A5USB_DATA5
DDR3_FPGA_CASn
DDR3_FPGA_A0
DDR3_FPGA_DQ5
USB_DATA6
DDR3_FPGA_A1 USB_DATA7
DDR3_FPGA_BA[2:0]
nPERSTL0DDR3_FPGA_DQ21
DDR3_FPGA_DQS_N[3:0]
DDR3_FPGA_RESETn
SPI0_FPGA_CSn0SPI0_FPGA_CSn1
CAM_HSCAM_D7CAM_D9
USER_FPGA_PB0
CAM_STROBE
TSP_FPGA_INTn
LCD_PWM
USB_DATA[7:0]
ADC_Dp10ADC_Dn10ADC_Dp7ADC_Dn7
ADC_D0BADC_D1BADC_D2BADC_D3B
ADC_Dp10ADC_Dn10
ADC_Dp7ADC_Dn7
ADC_D0BADC_D1BADC_D2BADC_D3B
FPGA_ADC_SPICSn
FPGA_ADC_SPIMOSI
FPGA_ADC_SPICLK
FPGA_ADC_SPIMOSIFPGA_ADC_SPICLKFPGA_ADC_SPICSn
nPERSTL0
FPGA_I2C1_SCLFPGA_I2C1_SDA
SPI0_FPGA_CLKSPI0_FPGA_MOSI
SPI0_FPGA_MISO
SPI0_FPGA_CSn0SPI0_FPGA_CSn1
TSP_FPGA_INTn
LCD_PWM
USER_FPGA_PB0
CAM_STROBECAM_HSCAM_D7CAM_D9
DDR3_FPGA_DQS_P[3:0]DDR3_FPGA_DQS_N[3:0]
DDR3_FPGA_DQ[31:0]
DDR3_FPGA_A[14:0]
DDR3_FPGA_DM[3:0]
DDR3_FPGA_BA[2:0]
DDR3_FPGA_CKEDDR3_FPGA_ODTDDR3_FPGA_CSn
DDR3_FPGA_WEnDDR3_FPGA_RASnDDR3_FPGA_CASn
DDR3_FPGA_RESETn
DDR3_FPGA_CLK_PDDR3_FPGA_CLK_N
USB_RESETnUSB_OEnUSB_RDnUSB_WRn
USB_DATA[7:0]
ADC_Dp7ADC_Dn7
ADC_Dp10ADC_Dn10
ADC_D3BADC_D2BADC_D1BADC_D0B
FPGA_ADC_SPIMOSIFPGA_ADC_SPICLKFPGA_ADC_SPICSn
nPERSTL0
FPGA_I2C1_SDAFPGA_I2C1_SCL
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
04-CV SoC Bank 3A/3B/4A
B
4 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
04-CV SoC Bank 3A/3B/4A
B
4 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
04-CV SoC Bank 3A/3B/4A
B
4 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
04-CV SoC Bank 3A/3B/4A
SPI0_LCD INTERFACE
CAM INTERFACE
USB Blaster INTERFACE
CONTROL SIGNAL
FPGA DDR3 INTERFACE
3.3V
1.5V
1.5V
T41T41
Bank 3A
Bank 3B
CYCLONE V GX SoC BANK 3
5CSXFC6D_F896
U1A
Bank 3A
Bank 3B
CYCLONE V GX SoC BANK 3
5CSXFC6D_F896
U1A
DIFFIO_TX_B12pAF6
DIFFIO_RX_B14n,DQ2B AJ2
DIFFIO_TX_B29n,DQ4B,B_A_11 AK9
DIFFIO_TX_B33n,GND AJ10DIFFIO_RX_B34p,DQ5B,B_BA_1 AJ11
DIFFIO_TX_B33p,DQ5B,B_BA_0 AH10
DIFFIO_TX_B36n,DQ5B,B_A_7 AK13
DIFFIO_RX_B35n,DQSn5B,B_CK# AA15DIFFIO_TX_B36p,B_A_6 AK12
DIFFIO_RX_B35p,DQS5B,B_CK AA14
DIFFIO_RX_B38p,DQ5B,B_A_4 AG15DIFFIO_RX_B38n,DQ5B,B_A_5 AH15DIFFIO_TX_B40p,DQ5B,B_A_0 AJ14DIFFIO_TX_B40n,DQ5B,B_A_1 AK14
DIFFIO_TX_B13n,DQ2B AH5DIFFIO_RX_B14p,DQ2B AJ1DIFFIO_TX_B13p,DQ2B AG5
DIFFIO_TX_B16n,DQ2B AH3DIFFIO_RX_B15n AD12
DIFFIO_TX_B16p,DQ2B AG2DIFFIO_RX_B15p AC12
DIFFIO_TX_B28n,DQ4B,B_A_13 AK8
DIFFIO_RX_B27n,DQSn4B,B_CS#_1 AC14DIFFIO_TX_B28p,B_A_12 AK7
DIFFIO_RX_B27p,DQS4B,B_CS#_0 AB15
DIFFIO_RX_B30n,DQ4B,B_A_9 AH14
DIFFIO_RX_B19n,DQSn3BAB13
DIFFIO_RX_B11n,DQSn2BAB12
DIFFIO_RX_B18n,DQ3BAG11
DIFFIO_RX_B10n,DQ2BAH2
DIFFIO_TX_B12n,DQ2BAG6
DIFFIO_RX_B26n,DQ4B,B_A_15AG13
DIFFIO_TX_B21n,DQ3BAK4
DIFFIO_TX_B24n,DQ3BAK6
DIFFIO_RX_B19p,DQS3BAA13
DIFFIO_RX_B26p,DQ4B,B_A_14AG12
DIFFIO_RX_B22p,DQ3BAE13
DIFFIO_TX_B9nAG7
DIFFIO_RX_B22n,DQ3BAF13
DIFFIO_RX_B11p,DQS2BAA12
DIFFIO_TX_B17nAH9
DIFFIO_TX_B24p,DQ3BAJ5
DIFFIO_TX_B20n,DQ3BAK3 DIFFIO_TX_B20pAK2
DIFFIO_TX_B25p,DQ4B,B_WE#AJ6
DIFFIO_TX_B21p,DQ3BAJ4
DIFFIO_TX_B17p,DQ3BAG10
DIFFIO_TX_B25n,GNDAJ7
DIFFIO_RX_B18p,DQ3BAF11
DIFFIO_TX_B8p,DQ1BAF9
DIFFIO_RX_B10p,DQ2BAG1
DIFFIO_RX_B23nAE14
DIFFIO_TX_B9p,DQ2BAF8
DIFFIO_RX_B23pAD14
DIFFIO_RX_B30p,DQ4B,B_A_8 AH13
DIFFIO_TX_B29p,DQ4B,B_A_10 AJ9
DIFFIO_TX_B32n,DQ4B,B_RAS# AH8DIFFIO_TX_B32p,DQ4B,B_CAS# AH7
DIFFIO_RX_B34n,DQ5B,B_BA_2 AK11
Bank 4A
CYCLONE V GX SoC BANK 4
5CSXFC6D_F896
U1B
Bank 4A
CYCLONE V GX SoC BANK 4
5CSXFC6D_F896
U1B
DIFFIO_TX_B61n,DQ8B,GNDAJ22
DIFFIO_RX_B42n,DQ6B,B_DQ_0AF18 DIFFIO_RX_B62n,DQ8B,B_DQ_20 AF21
RZQ_0,DIFFIO_TX_B41n AG17
DIFFIO_RX_B42p,DQ6B,B_DQ_1AE17 DIFFIO_RX_B62p,DQ8B,B_DQ_21 AF20DIFFIO_TX_B41p,DQ6B,B_DQ_2AG16
DIFFIO_TX_B61p,DQ8B,B_DQ_22AH23
DIFFIO_TX_B64n,DQ8B,B_DQ_23 AK24DIFFIO_TX_B44n,DQ6B,B_DQ_3AF16DIFFIO_RX_B63n,GND AA19DIFFIO_RX_B43n,DQSn6B,B_DQS#_0W16
DIFFIO_TX_B64p,DQ8B,B_DM_2 AK23
DIFFIO_RX_B63p,GND Y18
DIFFIO_RX_B66n,DQ9B,B_DQ_24 AF24
DIFFIO_TX_B44p,B_ODT_0AE16
DIFFIO_TX_B65n,GND AJ25
DIFFIO_RX_B43p,DQS6B,B_DQS_0V16
DIFFIO_RX_B46n,DQ6B,B_DQ_4AH20 DIFFIO_RX_B66p,DQ9B,B_DQ_25 AF23DIFFIO_TX_B45n,DQ6B,B_ODT_1AK16 DIFFIO_TX_B65p,DQ9B,B_DQ_26 AJ24
DIFFIO_TX_B68n,DQ9B,B_DQ_27 AK26
DIFFIO_RX_B46p,DQ6B,B_DQ_5AG21
DIFFIO_RX_B67n,DQSn9B,B_DQS#_3 AD19
DIFFIO_TX_B45p,DQ6B,B_DQ_6AJ16
DIFFIO_TX_B68p,GND AJ26
DIFFIO_RX_B67p,DQS9B,B_DQS_3 AC20
DIFFIO_RX_B70n,DQ9B,B_DQ_28 AE23
DIFFIO_TX_B48p,DQ6B,B_DM_0AH17
DIFFIO_TX_B69n,DQ9B,GND AH25
DIFFIO_TX_B48n,DQ6B,B_DQ_7AH18
DIFFIO_RX_B50n,DQ7B,B_DQ_8AK18DIFFIO_RX_B70p,DQ9B,B_DQ_29 AE22DIFFIO_TX_B69p,DQ9B,B_DQ_30 AG25
DIFFIO_TX_B72n,DQ9B,B_DQ_31 AK27DIFFIO_RX_B71n,GND W19
DIFFIO_TX_B72p,DQ9B,B_DM_3 AJ27DIFFIO_RX_B71p,GND V18
DIFFIO_RX_B74n,DQ10B,B_DQ_32 AD21DIFFIO_TX_B73n,GND AK29
DIFFIO_RX_B74p,DQ10B,B_DQ_33 AD20
DIFFIO_TX_B73p,DQ10B,B_DQ_34 AK28
DIFFIO_TX_B76n,DQ10B,B_DQ_35 AH27
DIFFIO_RX_B75n,DQSn10B,B_DQS#_4 AA20DIFFIO_TX_B76p,GND AG26
DIFFIO_RX_B75p,DQS10B,B_DQS_4 Y19
DIFFIO_RX_B78n,DQ10B,B_DQ_36 AC23
DIFFIO_TX_B77n,DQ10B,GND AF26DIFFIO_RX_B78p,DQ10B,B_DQ_37 AC22
DIFFIO_TX_B77p,DQ10B,B_DQ_38 AF25
DIFFIO_TX_B80n,DQ10B,B_DQ_39 AE24
DIFFIO_RX_B79n,GND AB21DIFFIO_TX_B80p,DQ10B,B_DM_4 AD24
DIFFIO_RX_B79p,GND AA21
DIFFIO_TX_B60p,B_RESET#AK21 DIFFIO_RX_B59n,DQSn8B,B_DQS#_2AA18DIFFIO_RX_B58n,DQ8B,B_DQ_16AE19
DIFFIO_TX_B57n,GNDAH22
DIFFIO_TX_B52p,B_CKE_1AJ19
DIFFIO_TX_B56p,DQ7B,B_DM_1AG23
DIFFIO_RX_B54p,DQ7B,B_DQ_13AF19
DIFFIO_RX_B58p,DQ8B,B_DQ_17AE18
DIFFIO_TX_B53n,DQ7B,B_CKE_0AJ21DIFFIO_TX_B52n,DQ7B,B_DQ_11AK19
DIFFIO_RX_B51p,DQS7B,B_DQS_1V17
DIFFIO_TX_B57p,DQ8B,B_DQ_18AG22
DIFFIO_TX_B53p,DQ7B,B_DQ_14AJ20
DIFFIO_TX_B56n,DQ7B,B_DQ_15AH24
DIFFIO_RX_B59p,DQS8B,B_DQS_2Y17
DIFFIO_RX_B50p,DQ7B,B_DQ_9AJ17
DIFFIO_TX_B60n,DQ8B,B_DQ_19AK22
DIFFIO_TX_B49p,DQ7B,B_DQ_10AG18
DIFFIO_RX_B51n,DQSn7B,B_DQS#_1W17
DIFFIO_TX_B49n,GNDAH19
DIFFIO_RX_B54n,DQ7B,B_DQ_12AG20
R6 100R6 100
T42T42
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3_HPS_DM0DDR3_HPS_DQS_P0DDR3_HPS_DQS_N0DDR3_HPS_DQ0DDR3_HPS_DQ1DDR3_HPS_DQ2DDR3_HPS_DQ3DDR3_HPS_DQ4DDR3_HPS_DQ5DDR3_HPS_DQ6DDR3_HPS_DQ7
DDR3_HPS_DM1DDR3_HPS_DQS_P1DDR3_HPS_DQS_N1DDR3_HPS_DQ8DDR3_HPS_DQ9DDR3_HPS_DQ10DDR3_HPS_DQ11DDR3_HPS_DQ12DDR3_HPS_DQ13DDR3_HPS_DQ14DDR3_HPS_DQ15
DDR3_HPS_RESETn
ADC_ORpADC_ORn
DDR3_HPS_A0
DDR3_HPS_DM2DDR3_HPS_DQS_P2DDR3_HPS_DQS_N2DDR3_HPS_DQ16
DDR3_HPS_A1
DDR3_HPS_DQ17
FAN_CTRL
DDR3_HPS_A2DDR3_HPS_A3DDR3_HPS_A4DDR3_HPS_A5DDR3_HPS_A6DDR3_HPS_A7
DDR3_HPS_DQ18
DDR3_HPS_CKE
DDR3_HPS_CLK_PDDR3_HPS_CLK_N
DDR3_HPS_A[14:0]
DDR3_HPS_ODT
DDR3_HPS_DQ[31:0]
DDR3_HPS_CSn
USER_HPS_PB[3:0]
DDR3_HPS_WEnDDR3_HPS_RASn
DDR3_HPS_DM[3:0]
DDR3_HPS_CASn
DDR3_HPS_BA[2:0]
DDR3_HPS_RESETn
DDR3_HPS_A8DDR3_HPS_A9DDR3_HPS_A10DDR3_HPS_A11DDR3_HPS_A12DDR3_HPS_A13DDR3_HPS_A14
DDR3_HPS_DQ19DDR3_HPS_DQ20DDR3_HPS_DQ21DDR3_HPS_DQ22DDR3_HPS_DQ23
DDR3_HPS_DQS_N[3:0]
DDR3_HPS_DM3DDR3_HPS_DQS_P3DDR3_HPS_DQS_N3DDR3_HPS_DQ24DDR3_HPS_DQ25DDR3_HPS_DQ26DDR3_HPS_DQ27DDR3_HPS_DQ28
DDR3_HPS_DQS_P[3:0]DDR3_HPS_DQ29DDR3_HPS_DQ30DDR3_HPS_DQ31
DDR3_HPS_CLK_PDDR3_HPS_CLK_NDDR3_HPS_CKE
USER_HPS_PB0USER_HPS_PB1USER_HPS_PB2USER_HPS_PB3
DDR3_HPS_BA0DDR3_HPS_BA1DDR3_HPS_BA2DDR3_HPS_RASnDDR3_HPS_CASnDDR3_HPS_WEnDDR3_HPS_CSn
DDR3_HPS_ODT
HPS_RZQ
ADC_Dp11ADC_Dn11ADC_Dp4ADC_Dn4
ADC_Dp8ADC_Dn8
ADC_Dp0ADC_Dn0
ADC_DCOnADC_DCOp
ADC_Dn2ADC_Dp2
ADC_Dn6ADC_Dp6
RTC_INTn
ADC_DCOpADC_DCOn
ADC_ORpADC_ORn
FAN_CTRL
FPGA_ADC_OEB
RTC_INTn
FPGA_ADC_OEB
ADC_Dp11ADC_Dn11
ADC_Dp4ADC_Dn4
ADC_Dp8ADC_Dn8
ADC_Dp6ADC_Dn6
ADC_Dp0ADC_Dn0
ADC_Dp2ADC_Dn2
RTC_INTn
DDR3_HPS_DQS_P[3:0]
USER_HPS_PB[3:0]
FPGA_ADC_OEB
FAN_CTRL
DDR3_HPS_DQS_N[3:0]
DDR3_HPS_DQ[31:0]
DDR3_HPS_A[14:0]
DDR3_HPS_DM[3:0]
DDR3_HPS_BA[2:0]
DDR3_HPS_CKEDDR3_HPS_ODTDDR3_HPS_CSn
DDR3_HPS_WEnDDR3_HPS_RASnDDR3_HPS_CASn
DDR3_HPS_RESETn
DDR3_HPS_CLK_PDDR3_HPS_CLK_N
ADC_ORpADC_ORn
ADC_DCOpADC_DCOn
ADC_Dp11ADC_Dn11
ADC_Dp4ADC_Dn4
ADC_Dp8ADC_Dn8
ADC_Dp6ADC_Dn6
ADC_Dp0ADC_Dn0
ADC_Dp2ADC_Dn2
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
05-CV SoC Bank 5A/5B/6A/6B
B
5 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
05-CV SoC Bank 5A/5B/6A/6B
B
5 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
05-CV SoC Bank 5A/5B/6A/6B
B
5 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
05-CV SoC Bank 5A/5B/6A/6B
HPS DDR3 INTERFACE
ADC INTERFACE
CONTROL INTERFACE
SPI1_AD9628 INTERFACE
1.8V
1.8V
1.5V
1.5V
R15 100R15 100
CYCLONE V GX SoC BANK 5Bank 5A
Bank 5B
5CSXFC6D_F896
U1C
CYCLONE V GX SoC BANK 5Bank 5A
Bank 5B
5CSXFC6D_F896
U1C
DIFFIO_TX_R12p,DQ2R AG28RZQ_1,DIFFIO_TX_R1p,DQ1R AG27
DIFFIO_RX_R4p,DQ1RW20
DIFFIO_RX_R17nV25
DIFFIO_TX_R18n,DQ3RAC29DIFFIO_RX_R19p,DQ3RAB30
DIFFIO_TX_R20p,DQ3RAB28 DIFFIO_RX_R19n,DQ3RAA30
DIFFIO_TX_R20n,DQ3RAA28DIFFIO_TX_R24p,DQ3RAD30
RZQ_2,DIFFIO_TX_R24nAC30
DIFFIO_RX_R11n,DQ2RY24
DIFFIO_RX_R4n,DQ1RY21DIFFIO_TX_R12n,DQ2R AF28DIFFIO_TX_R7p,DQ1RAA25
DIFFIO_RX_R8p,DQ1RAB22 DIFFIO_RX_R13p,DQS2R V23DIFFIO_TX_R7nAB26
DIFFIO_TX_R14p AF29DIFFIO_RX_R8n,DQ1RAB23 DIFFIO_RX_R13n,DQSn2R W24
DIFFIO_RX_R9pAA24 DIFFIO_TX_R14n,DQ2R AF30
DIFFIO_TX_R10p,DQ2RAE27 DIFFIO_RX_R15p,DQ2R AD26DIFFIO_RX_R9nAB25
DIFFIO_TX_R16p,DQ2R AH30DIFFIO_TX_R10n,DQ2RAE28 DIFFIO_RX_R15n,DQ2R AC27
DIFFIO_RX_R11p,DQ2RY23 DIFFIO_TX_R16n AG30
DIFFIO_RX_R17pW25
DIFFIO_TX_R18p,DQ3RAC28
CYCLONE V GX SoC BANK 6
Bank 6A
Bank 6B
5CSXFC6D_F896
U1D
CYCLONE V GX SoC BANK 6
Bank 6A
Bank 6B
5CSXFC6D_F896
U1D
HPS_DDR,HPS_A_13C29
HPS_GI14 M25
HPS_DDR,HPS_A_14H25
HPS_DDR,HPS_DM_0 K28
HPS_DDR,HPS_WE#C28
HPS_DDR,HPS_DQ_7 J29
HPS_DDR,HPS_A_15G25
HPS_DDR,HPS_DQ_5 L24
HPS_RZQ_0D27
HPS_DDR,HPS_DQ_6 J30HPS_DDR,HPS_DQ_4 L25
HPS_DDR,HPS_ODT_1H29
HPS_DDR,HPS_DQS_0 N18
HPS_DDR,HPS_ODT_0H28
HPS_DDR,HPS_DQS#_0 M19
HPS_DDR,HPS_DQ_3 G28
HPS_DDR,HPS_DQ_1 K22HPS_DDR,HPS_DQ_2 H30HPS_DDR,HPS_DQ_0 K23
HPS_DDR,HPS_A_0F26HPS_DDR,HPS_A_1G30
HPS_DDR,HPS_A_4J25HPS_DDR,HPS_A_2F28
HPS_DDR,HPS_A_5J27HPS_DDR,HPS_A_3F30
HPS_DDR,HPS_CKM23
HPS_GI11 M22
HPS_DDR,HPS_DM_1 M28
HPS_GI12 N23
HPS_DDR,HPS_A_6F29
HPS_DDR,HPS_DQ_15 M30
HPS_DDR,HPS_CK#L23
HPS_DDR,HPS_DQ_13 M27
HPS_DDR,HPS_A_7E28
HPS_DDR,HPS_DQ_14 L28HPS_DDR,HPS_BA_1J24 HPS_DDR,HPS_BA_0E29
HPS_DDR,HPS_BA_2J23
HPS_DDR,HPS_DQ_12 M26
HPS_DDR,HPS_CAS#E27
HPS_DDR,HPS_CKE_0L29
HPS_DDR,HPS_RAS#D30
HPS_DDR,HPS_DQS_1 N25
HPS_DDR,HPS_A_8H27
HPS_DDR,HPS_CKE_1L30
HPS_DDR,HPS_A_10D29
HPS_DDR,HPS_DQS#_1 N24
HPS_DDR,HPS_A_9G26
HPS_DDR,HPS_DQ_11 K27
HPS_DDR,HPS_A_11C30
HPS_DDR,HPS_DQ_9 L26
HPS_DDR,HPS_CS#_0H24
HPS_DDR,HPS_DQ_10 K29
HPS_DDR,HPS_A_12B30
HPS_DDR,HPS_DQ_8 K26
HPS_DDR,HPS_CS#_1K21
HPS_GI13 J26
HPS_DDR,HPS_DQS_4 T24
HPS_GI3 U20
HPS_DDR,HPS_DQ_36 T25HPS_DDR,HPS_DQ_37 U25
HPS_DDR,HPS_DQS#_4 T23HPS_DDR,HPS_DM_2R28
HPS_DDR,HPS_DQ_32 W26
HPS_DDR,HPS_DQ_29R26
HPS_DDR,HPS_DQ_26T29
HPS_DDR,HPS_DM_4 W27
HPS_DDR,HPS_DQ_27T28
HPS_GI7 V20
HPS_DDR,HPS_DQ_23R29
HPS_GI6 T30
HPS_DDR,HPS_DQ_39 Y29HPS_DDR,HPS_DQ_38 V27
HPS_GI8 P22HPS_DDR,HPS_DQ_24P24
HPS_DDR,HPS_DQ_34 U27
HPS_GI1 Y28
HPS_DDR,HPS_DQ_35 V28
HPS_GI2 V29
HPS_DDR,HPS_DQ_33 R24
HPS_GI4 T21HPS_DDR,HPS_DQ_25P25
HPS_DDR,HPS_DM_3W30
HPS_DDR,HPS_DQ_31W29
HPS_DDR,HPS_DQS#_2R18
HPS_DDR,HPS_DQ_20P26
HPS_GI9 P29
HPS_DDR,HPS_DQ_22N27
HPS_DDR,HPS_RESET# P30
HPS_DDR,HPS_DQ_21P27
HPS_DDR,HPS_DQS_2R19
HPS_DDR,HPS_DQ_19N28
HPS_DDR,HPS_DQS#_3R21
HPS_DDR,HPS_DQ_17T26 HPS_DDR,HPS_DQ_16U26
HPS_GI10 N30
HPS_DDR,HPS_DQ_18N29
HPS_DDR,HPS_DQ_28R27
HPS_GI5 U28
HPS_DDR,HPS_DQ_30V30
HPS_DDR,HPS_DQS_3R22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB1HS_STPUSB1HS_DIRUSB1HS_NXTUSB1HS_CLKUSB1HS_D7USB1HS_D5USB1HS_D6
MMC_DAT3MMC_DAT2
MMC_DAT7MMC_DAT6
MMC_CLKeMMC_RSTn
MII1_RXD1MII1_RX_CLKMII1_TX_ENMII1_RX_DVMII_MDCMII_MDIOMII1_RXD0MII1_TXD3MII1_TXD2MII1_TXD1MII1_TXD0
HPS_DVI_IRQHPS_GPIO49HPS_GPIO50HPS_I2C1_SDA
CLK_OSC2CLK_OSC1
USB1HS_D4USB1HS_D3USB1HS_D2USB1HS_D1USB1HS_D0HPS_GPIO0HPS_GPIO9
MMC_DAT5MMC_DAT4MMC_DAT1MMC_DAT0MMC_CDMMC_CMD
MII1_TX_CLKMII1_RXD2MII1_RXD3HPS_GPIO28QSPI_IO0QSPI_IO1QSPI_IO2QSPI_IO3QSPI_SS0QSPI_CLK
HPS_I2C1_SCLHPS_GPIO53HPS_GPIO54HPS_I2C0_SDAHPS_I2C0_SCLHPS_SPIM0_CLK
HPS_SPIM0_MOSIHPS_SPIM0_MISOHPS_SPIM0_CS0nHPS_GPIO61HPS_GPIO62HPS_UART1_RXHPS_UART1_TXHPS_UART0_RXHPS_UART0_TX
HPS_WARM_RSTn
CLK_OSC1CLK_OSC2
USB1HS_CLKUSB1HS_NXTUSB1HS_DIRUSB1HS_STP
USB1HS_D[7:0]
MMC_CLKMMC_CMD
MMC_CD
eMMC_RSTn
MMC_DAT[7:0]
MII1_RXD[3:0]
MII1_TXD[3:0]
MII1_RX_CLKMII1_RX_DV
MII1_TX_ENMII1_TX_CLK
HPS_TRST
MII_INT
MII_MDCMII_MDIO
HPS_RESETnHPS_WARM_RSTn
HPS_SPIM0_MISOHPS_SPIM0_MOSIHPS_SPIM0_CLKHPS_SPIM0_CS0n
QSPI_SS0QSPI_CLK
HPS_GPIO44
HPS_DVI_IRQ
HPS_GPIO49HPS_GPIO50HPS_GPIO53HPS_GPIO54HPS_GPIO61HPS_GPIO62
HPS_GPIO62
QSPI_SS0HPS_SPIM0_CS0n
HPS_GPIO28
HPS_UART0_TX
HPS_TDOHPS_RESETn
HPS_TDI
HPS_TCKHPS_TMS
QSPI_IO[3:0]
HPS_GPIO0HPS_GPIO9
HPS_I2C0_SDAHPS_I2C0_SCL
HPS_I2C1_SDAHPS_I2C1_SCL
HPS_UART0_TX
HPS_UART1_TXHPS_UART1_RX
HPS_UART0_RX
LCD_I2C1_SCLLCD_I2C1_SDA
DDC_SCLDDC_SDA
HPS_I2C0_SCLHPS_I2C0_SDA
CAM_SCLCAM_SDA
HPS_I2C0_SCLI2C_SDA_VGAI2C_SCL_VGA
HPS_I2C0_SDA
HPS_RSTn
HPS_TDO
HPS_TCKHPS_TMSHPS_TDI
HPS_GPIO44
MII_INT
3.3V_VDD
2.5V_VDD
3.3V_VDD
3.3V_VDD
3.3V_VDD5V_VDD
CLK_OSC1CLK_OSC2
HPS_RESETnHPS_WARM_RSTn
USB1HS_CLKUSB1HS_NXTUSB1HS_DIR
USB1HS_D[7:0]
USB1HS_STP
MII1_RXD[3:0]
MII1_TXD[3:0]
MII1_RX_CLKMII1_RX_DV
MII1_TX_CLKMII1_TX_EN
MII_INT
MII_MDCMII_MDIO
MMC_DAT[7:0]
MMC_CLKMMC_CMD
eMMC_RSTn
MMC_CD
HPS_SPIM0_MISOHPS_SPIM0_MOSIHPS_SPIM0_CLKHPS_SPIM0_CS0n
QSPI_IO[3:0]
QSPI_SS0QSPI_CLK
HPS_GPIO44HPS_GPIO49HPS_GPIO50HPS_GPIO53HPS_GPIO54HPS_GPIO61HPS_GPIO62
HPS_GPIO0HPS_GPIO9
HPS_I2C0_SDAHPS_I2C0_SCL
HPS_I2C1_SDAHPS_I2C1_SCL
DDC_SCLDDC_SDA
CAM_SDA
LCD_I2C1_SDA
CAM_SCL
LCD_I2C1_SCL
HPS_DVI_IRQ
I2C_SDA_VGAI2C_SCL_VGA
HPS_TCKHPS_TMSHPS_TDIHPS_TDO
HPS_UART0_RXHPS_UART0_TX
HPS_UART1_RXHPS_UART1_TX
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
06-CV SoC Bank 7A/7B/7C/7D
B
6 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
06-CV SoC Bank 7A/7B/7C/7D
B
6 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
06-CV SoC Bank 7A/7B/7C/7D
B
6 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
CLKSEL0CLKSEL1BOOTSEL0BOOTSEL1BOOTSEL2
CLK IN & RESET
USB INTERFACE
ETHERNET INTERFACE
MMC INTERFACE
HPS SPI INTERFACE
QSPI INTERFACE
GPIO INTERFACE
GPIO for BOOT06-CV SoC Bank 7A/7B/7C/7D
HPS_GPIO66
HPS_GPIO66HPS_GPIO62HPS_GPIO60
HPS_GPIO60
HPS_GPIO33
HPS_GPIO33
HPS_GPIO28
HPS_GPIO28
HPS_GPIO62
HPS I2C INTERFACE
HPS UART INTERFACE
HPS_GPIO65
Default: CLKSEL[1:0]=10
Default: BOOTSEL[2:0]=101
R29 10KR29 10K
R30 10KR30 10K
C49100nFC49100nF
T1T1
C54100nFC54100nF
R32 10KR32 10KR24 4.7KR24 4.7K
R12 NC0402R12 NC0402
R44 NC0402R44 NC0402
T2T2
R13 0RR13 0R
R31 10KR31 10K
R33 10KR33 10K
R14 0RR14 0R
R398 0RR398 0R
R28 10KR28 10K
S11
DIP Switch 4Pairs
S11
DIP Switch 4Pairs
1234 5
678
T4T4
R11 NC0402R11 NC0402
R9 0RR9 0R
R27 10KR27 10K
R25 NC0402R25 NC0402
U11
TXS0102DCTR
U11
TXS0102DCTR
B2 1GND 2
VCCA3
A24 A15
OE6
VCCB 7B1 8
R10 0RR10 0R
T3T3
R84.7K
R84.7K
R74.7KR74.7K
R21 4.7KR21 4.7KR20 4.7KR20 4.7K
R23 NC0402R23 NC0402
CYCLONE V GX SoC BANK 7
Bank 7A
Bank 7B
Bank 7C
Bank 7D
5CSXFC6D_F896
U1E
CYCLONE V GX SoC BANK 7
Bank 7A
Bank 7B
Bank 7C
Bank 7D
5CSXFC6D_F896
U1E
TRACE_D5,SPIS1_MOSI,CAN1_TX,HPS_GPIO54 G21
QSPI_IO2,USB1_DIR,HPS_GPIO31 A19
TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55 C24
QSPI_IO3,USB1_NXT,HPS_GPIO32 E19
TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56 E23
QSPI_SS0,BOOTSEL1,HPS_GPIO33 A18
SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57 A23
QSPI_CLK,HPS_GPIO34 D19
SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58 C22
QSPI_SS1,HPS_GPIO35 C19
SPIM0_MISO,CAN1_RX,UART1_CTS,HPS_GPIO59 B23
RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6C14
SPIM0_SS0,CAN1_TX,UART1_RTS,BOOTSEL0,HPS_GPIO60 H20
SDMMC_CMD,USB0_D0,HPS_GPIO36 F18SDMMC_PWREN,USB0_D1,HPS_GPIO37 B17
SDMMC_D0,USB0_D2,HPS_GPIO38 G18
UART0_RX,CAN0_RX,SPIM0_SS1,HPS_GPIO61 B22
SDMMC_D1,USB0_D3,HPS_GPIO39 C17
UART0_TX,CAN0_TX,SPIM1_SS1,HPS_GPIO62 G22
SDMMC_D4,USB0_D4,HPS_GPIO40 H17
I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63 C23
SDMMC_D5,USB0_D5,HPS_GPIO41 C18
I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64 D22
SDMMC_D6,USB0_D6,HPS_GPIO42G17
CAN0_RX,UART0_RX,SPIM1_MISO,HPS_GPIO65 E24
SDMMC_D7,USB0_D7,HPS_GPIO43E18
CAN0_TX,UART0_TX,SPIM1_SS0,HPS_GPIO66 D24
SDMMC_CLK_IN,USB0_CLK,HPS_GPIO44E17 SDMMC_CLK,USB0_STP,HPS_GPIO45A16 SDMMC_D2,USB0_DIR,HPS_GPIO46D17
RGMII0_TX_CLK,HPS_GPIO0 F16
SDMMC_D3,USB0_NXT,HPS_GPIO47B16
RGMII0_TXD0,USB1_D0,HPS_GPIO1 E16RGMII0_TXD1,USB1_D1,HPS_GPIO2 G16RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10N16 RGMII0_TXD2,USB1_D2,HPS_GPIO3 D16
RGMII0_TX_CTL,HPS_GPIO9 B15
RGMII0_TXD3,USB1_D3,HPS_GPIO4 D14RGMII0_RX_CTL,USB1_D7,HPS_GPIO8M17
RGMII0_RXD0,USB1_D4,HPS_GPIO5 A15
RGMII0_RXD3,USB1_NXT,HPS_GPIO13A14
HPS_nRSTC27
NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14 H19
HPS_nPORF23
NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15F20
HPS_TDOB28
NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16J19
VCC_HPSG23
NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17F21
HPS_TMSA29
NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18F19
HPS_TCKH22
NAND_DQ0,RGMII1_RXD0,HPS_GPIO19A21
HPS_TRSTA28
NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20E21
HPS_TDIB27
NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21B21
HPS_PORSELF24
NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22K17
HPS_CLK1D25
NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23A20
HPS_CLK2F25
NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24G20
TRACE_CLK,HPS_GPIO48B26TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49B25
NAND_DQ7,RGMII1_RXD2,HPS_GPIO26 B18
TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50C25
NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27 D21
TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51A25
NAND_WE,QSPI_SS1,BOOTSEL2,HPS_GPIO28 D20
TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52 H23
QSPI_IO0,USB1_CLK,HPS_GPIO29 C20
TRACE_D4,SPIS1_CLK,CAN1_RX,HPS_GPIO53 A24
QSPI_IO1,USB1_STP,HPS_GPIO30 H18
RGMII0_RXD2,USB1_DIR,HPS_GPIO12E14RGMII0_RXD1,USB1_STP,HPS_GPIO11C15
NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25B20
RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7D15
R26 10KR26 10K
T5T5
R34 10KR34 10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA_TX_D_P3FPGA_TX_D_N3
FPGA_TX_D_P2FPGA_TX_D_N2
FPGA_TX_D_P1FPGA_TX_D_N1FPGA_TX_D_P0FPGA_TX_D_N0
USER_FPGA_DIPSW0USER_FPGA_DIPSW1
USER_FPGA_DIPSW2USER_FPGA_DIPSW3
PCIE_LED_X1PCIE_LED_X4
USER_FPGA_LED0USER_FPGA_LED1
USER_FPGA_LED2USER_FPGA_LED3
SDI_TX_SD_HDnFPGA_I2C0_SCLFPGA_I2C0_SDASDI_TX_EN
HDMI_I2S_WSRHDMI_I2S_DR
DSS_D2DSS_D1
DSS_D23DSS_ACBIAS
SDI_FAULTnSDI_RSTIn
DSS_D19DSS_D20
SDI_RX_BYPASSSDI_RX_EN
DSS_HSYNC
DSS_D5DSS_D6
PCIE_SMBDAT
DSS_D0DSS_D9
DSS_D21DSS_D8
DSS_D22
DSS_D7DSS_D3DSS_D4
DSS_CLKDSS_VSYNC
DSS_D11DSS_D12DSS_D16DSS_D17
DSS_D13DSS_D10
DSS_D14
DSS_D18DSS_D15
FPGA_RX_D_P2FPGA_RX_D_N2
FPGA_RX_D_P1FPGA_RX_D_N1
FPGA_RX_D_P3FPGA_RX_D_N3
FPGA_RX_D_P0FPGA_RX_D_N0
HDMI_I2S_CKR
PCIE_WAKEn
PCIE_PERSTnSDI_CLK148_EN
SDI_CLK148_DNSDI_CLK148_UP
PCIE_PRSNT2_X4PCIE_PRSNT2_X1
PCIE_SMBCLK
FPGA_TX_D_P[3:0]FPGA_TX_D_N[3:0]
FPGA_RX_D_P[3:0]FPGA_RX_D_N[3:0]
HDMI_I2S_DR HDMI_I2S_DHDMI_I2S_CKRHDMI_I2S_WSR
HDMI_I2S_CKHDMI_I2S_WS
DSS_D[23:0]
DSS_ACBIASDSS_HSYNCDSS_VSYNCDSS_CLK
SDI_FAULTn
SDI_TX_SD_HDnSDI_TX_EN
SDI_RX_BYPASSSDI_RX_EN
SDI_CLK148_EN
SDI_CLK148_UPSDI_CLK148_DN
PCIE_PRSNT2_X1PCIE_PRSNT2_X4
PCIE_SMBDATPCIE_SMBCLK
FPGA_H_SMBCLKFPGA_H_SMBDAT
SDI_I2C_SCLSDI_I2C_SDA
PCIE_WAKEn
SDI_RSTIn
FPGA_I2C0_SCLFPGA_I2C0_SDA
USER_FPGA_DIPSW0USER_FPGA_DIPSW1USER_FPGA_DIPSW2USER_FPGA_DIPSW3
PCIE_LED_X1PCIE_LED_X4
USER_FPGA_LED0USER_FPGA_LED1USER_FPGA_LED2USER_FPGA_LED3
PCIE_PERSTn
PCIE_PRSNT2_X1PCIE_PRSNT2_X4
3.3V_VDD
3.3V_VDD
PCIE_SMBCLKPCIE_SMBDAT
PCIE_WAKEn
FPGA_TX_D_P[3:0]FPGA_TX_D_N[3:0]
FPGA_RX_D_P[3:0]FPGA_RX_D_N[3:0]
DSS_D[23:0]
DSS_ACBIASDSS_HSYNCDSS_VSYNCDSS_CLK
SDI_TX_SD_HDnSDI_TX_EN
SDI_RX_BYPASSSDI_RX_EN
SDI_RSTInSDI_FAULTn
SDI_CLK148_EN
SDI_CLK148_UPSDI_CLK148_DN
HDMI_I2S_DHDMI_I2S_CKHDMI_I2S_WS
SDI_I2C_SCLSDI_I2C_SDA
PCIE_PRSNT2_X1PCIE_PRSNT2_X4
FPGA_H_SMBCLKFPGA_H_SMBDAT
PCIE_LED_X1PCIE_LED_X4
USER_FPGA_LED0USER_FPGA_LED1USER_FPGA_LED2USER_FPGA_LED3
USER_FPGA_DIPSW0USER_FPGA_DIPSW1USER_FPGA_DIPSW2USER_FPGA_DIPSW3
PCIE_PERSTn
PCIE_PRSNT2_X1PCIE_PRSNT2_X4
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
07-CV SoC Bank 8A
B
8 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
07-CV SoC Bank 8A
B
8 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
07-CV SoC Bank 8A
B
8 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
07-CV SoC Bank 8A
LCD DSS INTERFACE
SDI INTERFACE
PCIE CTL INTERFACE
SDI TX I2C INTERFACE
SDI OSC 148.5MHz CONTROL
CH7033 I2S
3.3V
R19 0RR19 0R
R91 0RR91 0R
CYCLONE V GX SoC BANK 8
Bank 8A
5CSXFC6D_F896
U1F
CYCLONE V GX SoC BANK 8
Bank 8A
5CSXFC6D_F896
U1F
DIFFIO_RX_T13p,DQS2TH14 DIFFIO_RX_T31n,DQ4T G11
DIFFIO_TX_T14pC10 DIFFIO_TX_T32n D4DIFFIO_RX_T13n,DQSn2TG13
DIFFIO_RX_T33p K7DIFFIO_TX_T14n,DQ2TC9
DIFFIO_TX_T34p,DQ5T E3DIFFIO_RX_T15p,DQ2TF13 DIFFIO_RX_T33n K8
DIFFIO_TX_T16p,DQ2TA6 DIFFIO_TX_T34n,DQ5T E2DIFFIO_RX_T15n,DQ2TE13
DIFFIO_RX_T35p,DQ5T G10DIFFIO_TX_T16nA5
DIFFIO_TX_T36p,DQ5T E1DIFFIO_RX_T17pH8 DIFFIO_RX_T35n,DQ5T F10
DIFFIO_TX_T18p,DQ3TA4 DIFFIO_TX_T36n,DQ5T D1DIFFIO_RX_T17nG8
DIFFIO_RX_T37p,DQS5T J10DIFFIO_TX_T18n,DQ3TA3
DIFFIO_TX_T38p E7DIFFIO_RX_T19p,DQ3TE12 DIFFIO_RX_T37n,DQSn5T J9
DIFFIO_TX_T20p,DQ3TD6 DIFFIO_TX_T38n,DQ5T E6DIFFIO_RX_T19n,DQ3TD12
DIFFIO_RX_T39p,DQ5T F9DIFFIO_TX_T20n,DQ3TC5
DIFFIO_TX_T40p,DQ5T G7DIFFIO_RX_T21p,DQS3TH13 DIFFIO_RX_T39n,DQ5T F8
DIFFIO_TX_T22pD5 DIFFIO_TX_T40n F6DIFFIO_RX_T21n,DQSn3TH12
DIFFIO_TX_T22n,DQ3TC4
DIFFIO_TX_T2p,DQ1TB13DIFFIO_TX_T2n,DQ1TA13DIFFIO_RX_T3p,DQ1TC13 DIFFIO_RX_T23p,DQ3T F11
DIFFIO_RX_T3n,DQ1TB12 DIFFIO_TX_T24p,DQ3T E8DIFFIO_RX_T5p,DQS1TF15
DIFFIO_RX_T23n,DQ3T E11
DIFFIO_TX_T6pC12
DIFFIO_TX_T24n D7DIFFIO_RX_T25p J7
DIFFIO_TX_T26p,DQ4T B2
DIFFIO_RX_T5n,DQSn1TF14DIFFIO_RX_T25n H7
DIFFIO_TX_T6n,DQ1TB11DIFFIO_TX_T26n,DQ4T B1DIFFIO_RX_T7p,DQ1TD11DIFFIO_RX_T27p,DQ4T B6
DIFFIO_TX_T8p,DQ1TA9DIFFIO_TX_T28p,DQ4T C3
DIFFIO_RX_T7n,DQ1TD10DIFFIO_RX_T27n,DQ4T B5
DIFFIO_TX_T8nA8DIFFIO_TX_T28n,DQ4T B3DIFFIO_TX_T10p,DQ2TC7
DIFFIO_RX_T29p,DQS4T K12DIFFIO_TX_T10n,DQ2TB7
DIFFIO_TX_T30p D2DIFFIO_RX_T11p,DQ2TE9 DIFFIO_RX_T29n,DQSn4T J12
DIFFIO_TX_T12p,DQ2TC8 DIFFIO_TX_T30n,DQ4T C2DIFFIO_RX_T11n,DQ2TD9
DIFFIO_RX_T31p,DQ4T G12DIFFIO_TX_T12n,DQ2TB8
DIFFIO_TX_T32p,DQ4T E4
R17 4.7KR17 4.7K
R414 33R414 33R413 33R413 33
R16 4.7KR16 4.7K
R82 4.7KR82 4.7K
R43 4.7KR43 4.7K
R83 4.7KR83 4.7K
R42 4.7KR42 4.7K
R92 0RR92 0R
R412 33R412 33
R18 0RR18 0R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_RX_P0PCIE_RX_N0PCIE_RX_P1PCIE_RX_N1PCIE_RX_P2PCIE_RX_N2
PCIE_RX_P3PCIE_RX_N3
PCIE_REFCLK_QL0_PPCIE_REFCLK_QL0_N
GXB_RX_L4_PGXB_RX_L4_N
SDI_RX_PSDI_RX_N
CLK_148_PCLK_148_N
FPGA_RX_H_P0FPGA_RX_H_N0
FPGA_RX_H_P1FPGA_RX_H_N1FPGA_RX_H_P2FPGA_RX_H_N2FPGA_RX_H_P3FPGA_RX_H_N3
REFCLK_QL2_PREFCLK_QL2_N
PCIE_TX_P0PCIE_TX_N0PCIE_TX_P1PCIE_TX_N1PCIE_TX_P2PCIE_TX_N2
PCIE_TX_P3PCIE_TX_N3GXB_TX_L4_PGXB_TX_L4_N
SDI_TX_PSDI_TX_N
FPGA_TX_H_P0FPGA_TX_H_N0
FPGA_TX_H_P1FPGA_TX_H_N1FPGA_TX_H_P2FPGA_TX_H_N2FPGA_TX_H_P3FPGA_TX_H_N3
XCVR_RREF_TLREFCLK_QL2_PREFCLK_QL2_N
PCIE_REFCLK_QL0_PPCIE_REFCLK_QL0_N
PCIE_RX_P[3:0]PCIE_RX_N[3:0]
PCIE_TX_N[3:0]PCIE_TX_P[3:0]
FPGA_RX_H_N[3:0]
FPGA_TX_H_N[3:0]FPGA_TX_H_P[3:0]
FPGA_RX_H_P[3:0]
SDI_RX_PSDI_RX_N
SDI_TX_PSDI_TX_N
CLK_148_PCLK_148_N
PCIE_TX_N[3:0]
PCIE_RX_P[3:0]PCIE_RX_N[3:0]
PCIE_TX_P[3:0]
PCIE_REFCLK_QL0_PPCIE_REFCLK_QL0_N
SDI_RX_PSDI_RX_N
SDI_TX_NSDI_TX_P
CLK_148_PCLK_148_N
FPGA_TX_H_N[3:0]
FPGA_RX_H_P[3:0]FPGA_RX_H_N[3:0]
FPGA_TX_H_P[3:0]
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
08-CV SoC Bank GXB L0/L1/L2
B
9 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
08-CV SoC Bank GXB L0/L1/L2
B
9 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
08-CV SoC Bank GXB L0/L1/L2
B
9 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
08-CV SoC Bank GXB L0/L1/L2
XCVR FPGA INTERFACE
XCVR PCIE INTERFACE
XCVR SDI INTERFACE
R37 0RR37 0R
R392KR392K
R36 0RR36 0RR38 0RR38 0R
R410 0RR410 0R
R35 0RR35 0R
Cyclone V GX SoC Transceiver
GXB_LO
GXB_L1
GXB_L2
5CSXFC6D_F896
U1M
Cyclone V GX SoC Transceiver
GXB_LO
GXB_L1
GXB_L2
5CSXFC6D_F896
U1M
REFCLK0LnW7 REFCLK0LpW8
GXB_RX_L0n,GXB_REFCLK_L0nAE1 GXB_RX_L0p,GXB_REFCLK_L0pAE2 GXB_TX_L0p AD4GXB_TX_L0n AD3
GXB_RX_L1n,GXB_REFCLK_L1nAC1 GXB_RX_L1p,GXB_REFCLK_L1pAC2 GXB_TX_L1p AB4GXB_TX_L1n AB3
GXB_RX_L2n,GXB_REFCLK_L2nAA1 GXB_RX_L2p,GXB_REFCLK_L2pAA2 GXB_TX_L2p Y4GXB_TX_L2n Y3
GXB_RX_L3n,GXB_REFCLK_L3nW1 GXB_RX_L3p,GXB_REFCLK_L3pW2 GXB_TX_L3p V4GXB_TX_L3n V3
GXB_TX_L4n T3GXB_TX_L4p T4
GXB_RX_L5p,GXB_REFCLK_L5pR2GXB_RX_L5n,GXB_REFCLK_L5nR1 GXB_TX_L5n P3GXB_TX_L5p P4
REFCLK2LpP9REFCLK2LnP8
GXB_RX_L6p,GXB_REFCLK_L6pN2GXB_RX_L6n,GXB_REFCLK_L6nN1
GXB_TX_L6n M3GXB_TX_L6p M4
GXB_TX_L7n K3GXB_TX_L7p K4GXB_RX_L8p,GXB_REFCLK_L8pJ2GXB_RX_L8n,GXB_REFCLK_L8nJ1
GXB_TX_L8n H3GXB_TX_L8p H4
GXB_RX_L4n,GXB_REFCLK_L4nU1 GXB_RX_L4p,GXB_REFCLK_L4pU2
REFCLK1LpT9REFCLK1LnT8
GXB_RX_L7p,GXB_REFCLK_L7pL2GXB_RX_L7n,GXB_REFCLK_L7nL1
RREF_TL G1R411 0RR411 0R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_BOTRCLK_BOT1
CLK_50M_FPGA
ADC_Dp3ADC_Dn3
CLK_TOP1CLK_TOP1_EN
CLK_ENET_FPGA_PCLK_ENET_FPGA_N
DDR3_FPGA_A2DDR3_FPGA_A3
ADC_CLK105_CP
ADC_CLK105_CN
PCIE_REFCLK_SYNR_P
PCIE_REFCLK_SYNR_N
CLK_ENET_FPGA_PHY
ADC_Dp1ADC_Dn1
CLK_0n
CLK_TOP1
ADC_CLK105_PADC_CLK105_N
DDR3_FPGA_A3DDR3_FPGA_A2
CLK_BOT1
CLK_ENET_FPGA_PHY
CLK_50M_FPGA
CLK_ENET_FPGA_PCLK_ENET_FPGA_N
PCIE_REFCLK_SYNR_NPCIE_REFCLK_SYNR_P
ADC_Dp3ADC_Dn3
ADC_Dp1ADC_Dn1
ADC_CLK105_P
ADC_CLK105_N
CLK_BOT1
CLK_ENET_FPGA_PHY
CLK_50M_FPGA
CLK_TOP1
CLK_ENET_FPGA_PCLK_ENET_FPGA_N
PCIE_REFCLK_SYNR_NPCIE_REFCLK_SYNR_P
ADC_CLK105_PADC_CLK105_N
ADC_Dp3ADC_Dn3
ADC_Dp1ADC_Dn1
DDR3_FPGA_A2DDR3_FPGA_A3
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
09-CV SoC CLK 3B/4A/5B/8A
B
10 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
09-CV SoC CLK 3B/4A/5B/8A
B
10 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
09-CV SoC CLK 3B/4A/5B/8A
B
10 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
09-CV SoC CLK 3B/4A/5B/8A
1.5V
1.5V
1.8V
3.3V
C52 100nFC52 100nF
C53 100nFC53 100nF
R41 NC0402R41 NC0402
T95T95
Cyclone V GX SoC Clocks
Bank 3B
Bank 4A
Bank 5B
Bank 8A
5CSXFC6D_F896
U1N
Cyclone V GX SoC Clocks
Bank 3B
Bank 4A
Bank 5B
Bank 8A
5CSXFC6D_F896
U1N
CLK1n,DIFFIO_RX_B39nY16CLK1p,DIFFIO_RX_B39pW15
CLK2n,DIFFIO_RX_B47nAB17CLK2p,DIFFIO_RX_B47pAA16
CLK5p,DIFFIO_RX_R21p,DQS3RAA26FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB,DIFFIO_TX_R22p AE29
CLK3n,DIFFIO_RX_B55nAD17CLK3p,DIFFIO_RX_B55pAC18
CLK4p,FPLL_BR_FBp,DIFFIO_RX_R23p,DQ3RY26CLK4n,FPLL_BR_FBn,DIFFIO_RX_R23n,DQ3RY27
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn,DIFFIO_TX_T4n,DQ1T A10CLK7p,DIFFIO_RX_T1pH15CLK7n,DIFFIO_RX_T1nG15
CLK0p,FPLL_BL_FBp,DIFFIO_RX_B31pAF14 CLK0n,FPLL_BL_FBn,DIFFIO_RX_B31nAF15
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB,DIFFIO_TX_B37p,DQ5B,B_A_2 AH12FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn,DIFFIO_TX_B37n,DQ5B,B_A_3 AJ12
CLK5n,DIFFIO_RX_R21n,DQSn3RAB27
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn,DIFFIO_TX_R22n,DQ3R AD29
CLK6p,FPLL_TL_FBp,DIFFIO_RX_T9pK14CLK6n,FPLL_TL_FBn,DIFFIO_RX_T9nJ14 FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB,DIFFIO_TX_T4p,DQ1T A11
R40 0RR40 0RR47 0RR47 0R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_ENET_FPGA_P
CLK_ENET_FPGA_N
CLK_148_P
SDI_CLK148_EN CLK_148_NCLK_148_CN
CLK_148_CP
SDI_CLK148_UP
SDI_CLK148_DN
CLK_50M_FPGA
CLK_OSC1
REFCLK_100M_N PCIE_REFCLK_QL0_NPCIE_REFCLK_QL0_P
PCIE_REFCLK_SYN_NPCIE_REFCLK_SYN_P
CLK_OSC2
CLK_ENET_FPGA_PHY
CLK_BOT1
CLK_OSC1
CLK_OSC2
SDI_CLK148_EN
SDI_CLK148_UPSDI_CLK148_DN
CLK_BOT1
CLK_ENET_FPGA_PHY
CLK_50M_FPGA
CLK_ENET_FPGA_PCLK_ENET_FPGA_N
REFCLK_100M_P
PCIE_REFCLK_QL0_NPCIE_REFCLK_QL0_P
PCIE_REFCLK_SYN_NPCIE_REFCLK_SYN_P
CLK_148_PCLK_148_N
3.3V_VDD_X1
1.8V_VDD_X5
3.3V_VDD_X7
PCIE_REFCLK_QL0_PPCIE_REFCLK_QL0_N
PCIE_REFCLK_SYN_PPCIE_REFCLK_SYN_N
3.3V_VDD_X4
3.3V_VDD
3.3V_VDD
2.5V_VDD
2.5V_VDD
1.8V_VDD
3.3V_VDD
3.3V_VDD
CLK_OSC1
CLK_OSC2
SDI_CLK148_EN
SDI_CLK148_UPSDI_CLK148_DN
CLK_BOT1
CLK_ENET_FPGA_PHY
CLK_50M_FPGA
CLK_ENET_FPGA_NCLK_ENET_FPGA_P
PCIE_REFCLK_QL0_PPCIE_REFCLK_QL0_N
PCIE_REFCLK_SYN_NPCIE_REFCLK_SYN_P
CLK_148_NCLK_148_P
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
10-PLLs
B
10 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
10-PLLs
B
10 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
10-PLLs
B
10 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
10-PLLs
R69 4.99KR69 4.99K
R66 10KR66 10K
X7
25MHz
X7
25MHz
EN1
GND2
VCC 4
OUT 3 R68 33R68 33
R52 0RR52 0R
R58 0RR58 0R
R61 0RR61 0R
R49 1KR49 1K
C46 1nFC46 1nF
X6
148.5MHz
X6
148.5MHz
EN1
NC2
GND3 OUT 4OUTn 5
VCC 6
C34 100nFC34 100nFR51 0RR51 0R
FB6600R,FBFB6600R,FB
R60 1KR60 1K
C44
2.2uF
C44
2.2uF
C42 100nFC42 100nF
R65 33R65 33
R71 180KR71 180K C47 100nFC47 100nF
C45100nFC45100nF
FB5
600R,FB
FB5
600R,FB
R64 10KR64 10K
C43 100nFC43 100nF
X1
125MHz
X1
125MHz
EN1
NC2
GND3 OUT 4OUTn 5
VCC 6
R420 0RR420 0R
C35 100nFC35 100nF
FB4
600R,FB
FB4
600R,FB
C31100nFC31100nF
R70 4.99KR70 4.99K
C40100nFC40100nF
U58
SI52112
U58
SI52112
VDD1
XOUT2XIN/CLKIN3
VSS4VSS25
DIFF1 6DIFF1# 7
DIFF2 8DIFF2# 9
VDD210
PAD11
C34212pFC34212pF
FB7
600R,FB
FB7
600R,FB
X5
50MHz
X5
50MHz
EN1
GND2
VCC 4
OUT 3
C38
2.2uF
C38
2.2uF
C32
10uF
C32
10uF
C41
10uF
C41
10uF
FB8
600R,FB
FB8
600R,FB
C20100nFC20100nF
C603
2.2uF
C603
2.2uF
C39100nFC39100nF
R54 NC0402R54 NC0402
C37100nFC37100nF
X4
100MHz
X4
100MHz
EN1
NC2
GND3 OUT 4OUTn 5
VCC 6
R63 0RR63 0R
R56 NC0402R56 NC0402
R53 NC0402R53 NC0402
X325MHzX325MHz1
2
3
4
C21
10uF
C21
10uF
R67 10KR67 10K
R62 0RR62 0R
C30812pFC30812pF
FB69
600R,FB
FB69
600R,FB
R57 0RR57 0R
R55 NC0402R55 NC0402
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JTAG_TMSJTAG_TCKFPGA_TDIFPGA_TDO
CAM_D1
FPGA_DCLK
FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3FPGA_AS_nCSO
CAM_D11CAM_CLKCAM_D8CAM_D2CAM_WENCAM_VSCAM_FLDCAM_D0CAM_D5CAM_PCLKCAM_D6
ADC_Dp9
FPGA_nSTATUS
CAM_D10CAM_D3CAM_D4
PR_REQUESTCvP_CONFDONE
ADC_Dn9
FPGA_nCONFIG
FPGA_CONF_DONE
FPGA_nCE
JTAG_BLASTER_TCKJTAG_BLASTER_TMSJTAG_BLASTER_TDIJTAG_BLASTER_TDO
ADC_Dn5ADC_Dp5
CAM_SCL
CAM_WENCAM_CLK
CAM_VS
CAM_PCLK
CAM_D[11:0]
CAM_HS
CAM_FLD
CAM_STROBE
CAM_SDA
nPERSTL0
JTAG_BLASTER_TDO
JTAG_BLASTER_TCKJTAG_BLASTER_TMSJTAG_BLASTER_TDI
JTAG_TCKJTAG_TMSJTAG_TDIFPGA_TDI
JTAG_TDI
HPS_TCK
HPS_TMS
HPS_TDOFPGA_TDO
JTAG_TCK
JTAG_TMS
JTAG_HPS_EN
HPS_TDO
HPS_TCKHPS_TMSHPS_TDI
FPGA_TDO HPS_TDI
JTAG_TMS
FPGA_TDI
HPS_WARM_RSTn
USB_DISABLEn
JTAG_TDI
JTAG_TCK
MSEL0
MSEL2MSEL3
MSEL1
MSEL4
nCEO
DEV_CLRnDEV_OE
ADC_Dp9ADC_Dn9
ADC_Dp5ADC_Dn5
HPS_WARM_RSTnUSB_DISABLEn
PCIE_PERSTn
PCIE_PERSTn ADC_Dn5
PCIE_WAKEn ADC_Dp5
PCIE_WAKEn
3.3V_VDD
3.3V_VDD
3.3V_VDD
3.3V_VDD
3.3V_VDD
3.3V_VDD
3.3V_VDD
3.3V_VDD
CAM_SDA
CAM_D[11:0]
CAM_CLKCAM_WENCAM_VSCAM_HSCAM_STROBE
CAM_PCLKCAM_FLD
CAM_SCL
nPERSTL0
JTAG_BLASTER_TCKJTAG_BLASTER_TMS
JTAG_BLASTER_TDOJTAG_BLASTER_TDI
HPS_TCKHPS_TMS
HPS_TDOHPS_TDI
ADC_Dp9ADC_Dn9
ADC_Dp5ADC_Dn5
HPS_WARM_RSTnUSB_DISABLEn
PCIE_PERSTnPCIE_WAKEn
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
11-CV SoC Bank 3A/5A/9A Config
B
11 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
11-CV SoC Bank 3A/5A/9A Config
B
11 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
11-CV SoC Bank 3A/5A/9A Config
B
11 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
11-CV SoC Bank 3A/5A/9A ConfigCamera INTERFACE
R104 1KR104 1K
J3
PIN 5x2 DIP
J3
PIN 5x2 DIP
1 2
3 4
5 6
7 8
9 10
JP7JP7
T70T70
R562 0RR562 0RR87 0RR87 0R
R88 10KR88 10K
T79T79
R103 1KR103 1K
JP10JP10
T77T77
S12
DIP Switch 4Pairs
S12
DIP Switch 4Pairs
12345
678R561 0RR561 0R
L: COM=NCH: COM=NO
U56
TS3A5018
L: COM=NCH: COM=NO
U56
TS3A5018
IN1
NC1 2NO1 3COM14
NC2 5NO2 6COM27
GND8
COM39 NO3 10NC3 11
COM412 NO4 13NC4 14
EN#15
V+16
D37TVSD37TVS
R97 1KR97 1K
R589 0RR589 0R
R132 1KR132 1K
D38TVSD38TVS
R590 0RR590 0R
R5650RR5650R
R95 0RR95 0R
R85 10KR85 10K
R560 0RR560 0R
D39TVSD39TVS
JP11JP11
R86 10KR86 10K
D40TVSD40TVS
JP8JP8
R102 1KR102 1K
R8910KR8910K
T76T76
R143 1KR143 1K
R563 0RR563 0R
R564 0RR564 0R
R98 1KR98 1K
C341100nFC341100nF
R100 1KR100 1K
R105 1KR105 1K
R566 0RR566 0R
T78T78
Cyclone V GX SoC Configuration
Bank 3A
Bank 5A
Bank 9A
5CSXFC6D_F896
U1G
Cyclone V GX SoC Configuration
Bank 3A
Bank 5A
Bank 9A
5CSXFC6D_F896
U1G
nCEO,DIFFIO_TX_R3p,DQ1R AJ29
DATA12,DIFFIO_RX_B3p,DQS1BAC9
DEV_OE,DIFFIO_TX_R5pAE26 nPERSTL0,DIFFIO_RX_R6p,DQS1R W21
CvP_CONFDONE,DIFFIO_TX_R3n,DQ1R AH29
TDOAB9
AS_DATA2,DATA2AE8
nCSO,DATA4AB8
TMSV9
AS_DATA3,DATA3AC7
TCKAC5
nCEG5
nSTATUSF4
PR_DONE,DIFFIO_RX_B7n AF5
MSEL1 K6
DATA15,DIFFIO_TX_B6p,DQ1BAG3
DATA11,DIFFIO_TX_B4pAE11
DATA13,DIFFIO_TX_B6n,DQ1BAH4DATA14,DIFFIO_RX_B5n,DQ1BAE7
CLKUSR,DIFFIO_RX_B5p,DQ1BAD7
PR_READY,DIFFIO_TX_B8n,DQ1B AG8
MSEL2 G6
PR_ERROR,DIFFIO_RX_B7p AF4
MSEL3 L7nCONFIGJ5INIT_DONE,DIFFIO_RX_R2pAD25
PR_REQUEST,DIFFIO_TX_R1n,DQ1R AH28
MSEL4 L9
CRC_ERROR,DIFFIO_RX_R2n AC25
AS_DATA1,DATA1AE5
TDIU8
AS_DATA0,ASDO,DATA0AE6
DCLKU7
DATA5,DIFFIO_TX_B2nAE9DATA6,DIFFIO_RX_B1n,DQ1BAE12DATA7,DIFFIO_TX_B2p,DQ1BAD9DATA8,DIFFIO_RX_B1p,DQ1BAD11DATA9,DIFFIO_TX_B4n,DQ1BAF10DATA10,DIFFIO_RX_B3n,DQSn1BAD10
DEV_CLRn,DIFFIO_TX_R5n,DQ1RAD27nPERSTR0,DIFFIO_RX_R6n,DQSn1R W22
MSEL0 L8CONF_DONEF3
R567 NC0402R567 NC0402
R96 33R96 33
JP9JP9
R84 10KR84 10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3_FPGA_CKEDDR3_FPGA_CLK_PDDR3_FPGA_CLK_N
DDR3_FPGA_DM2DDR3_FPGA_DM3
DDR3_FPGA_CSnDDR3_FPGA_WEnDDR3_FPGA_RASnDDR3_FPGA_CASn
DDR3_FPGA_BA0DDR3_FPGA_BA1DDR3_FPGA_BA2DDR3_FPGA_RESETnDDR3_FPGA_ODTDDR3_FPGA_ZQ1
DDR3_FPGA_CKEDDR3_FPGA_CLK_PDDR3_FPGA_CLK_N
DDR3_FPGA_DM0DDR3_FPGA_DM1
DDR3_FPGA_CSnDDR3_FPGA_WEnDDR3_FPGA_RASnDDR3_FPGA_CASn
DDR3_FPGA_BA0DDR3_FPGA_BA1DDR3_FPGA_BA2DDR3_FPGA_RESETnDDR3_FPGA_ODTDDR3_FPGA_ZQ
DDR3_FPGA_A0DDR3_FPGA_A1DDR3_FPGA_A2DDR3_FPGA_A3DDR3_FPGA_A4DDR3_FPGA_A5DDR3_FPGA_A6DDR3_FPGA_A7DDR3_FPGA_A8DDR3_FPGA_A9DDR3_FPGA_A10DDR3_FPGA_A11DDR3_FPGA_A12DDR3_FPGA_A13DDR3_FPGA_A14
DDR3_FPGA_A0DDR3_FPGA_A1DDR3_FPGA_A2DDR3_FPGA_A3DDR3_FPGA_A4DDR3_FPGA_A5DDR3_FPGA_A6DDR3_FPGA_A7DDR3_FPGA_A8DDR3_FPGA_A9DDR3_FPGA_A10DDR3_FPGA_A11DDR3_FPGA_A12DDR3_FPGA_A13DDR3_FPGA_A14
DDR3_FPGA_DQ16DDR3_FPGA_DQ21DDR3_FPGA_DQ17DDR3_FPGA_DQ19DDR3_FPGA_DQ20DDR3_FPGA_DQ18DDR3_FPGA_DQ22DDR3_FPGA_DQ23DDR3_FPGA_DQ24DDR3_FPGA_DQ26DDR3_FPGA_DQ25DDR3_FPGA_DQ27DDR3_FPGA_DQ29DDR3_FPGA_DQ30DDR3_FPGA_DQ28DDR3_FPGA_DQ31
DDR3_FPGA_DQS_P2DDR3_FPGA_DQS_N2DDR3_FPGA_DQS_P3DDR3_FPGA_DQS_N3
DDR3_FPGA_DQ6DDR3_FPGA_DQ7DDR3_FPGA_DQ3DDR3_FPGA_DQ1DDR3_FPGA_DQ0DDR3_FPGA_DQ4DDR3_FPGA_DQ2DDR3_FPGA_DQ5DDR3_FPGA_DQ14DDR3_FPGA_DQ11DDR3_FPGA_DQ15DDR3_FPGA_DQ9DDR3_FPGA_DQ10DDR3_FPGA_DQ13DDR3_FPGA_DQ12DDR3_FPGA_DQ8
DDR3_FPGA_DQS_P0DDR3_FPGA_DQS_N0DDR3_FPGA_DQS_P1DDR3_FPGA_DQS_N1
DDR3_FPGA_DQ[31:0]
DDR3_FPGA_A[14:0]
DDR3_FPGA_DQS_P[3:0]DDR3_FPGA_DQS_N[3:0]
DDR3_FPGA_BA[2:0]
DDR3_FPGA_DM[3:0]
DDR3_FPGA_CLK_P
DDR3_FPGA_CLK_N
DDR3_FPGA_CKEDDR3_FPGA_CLK_PDDR3_FPGA_CLK_N
DDR3_FPGA_CSnDDR3_FPGA_WEnDDR3_FPGA_RASnDDR3_FPGA_CASn
DDR3_FPGA_RESETnDDR3_FPGA_ODT
DDR3_FPGA_RESETn
DDR3_FPGA_CKE
DDR3_FPGA_A11DDR3_FPGA_A10DDR3_FPGA_CASnDDR3_FPGA_A12DDR3_FPGA_RASnDDR3_FPGA_WEn
DDR3_FPGA_A13DDR3_FPGA_A14DDR3_FPGA_A6DDR3_FPGA_A3DDR3_FPGA_BA2DDR3_FPGA_BA1DDR3_FPGA_BA0
DDR3_FPGA_A7
DDR3_FPGA_A2 DDR3_FPGA_A8
DDR3_FPGA_A0DDR3_FPGA_A5DDR3_FPGA_A1DDR3_FPGA_A4DDR3_FPGA_CSnDDR3_FPGA_A9
DDR3_FPGA_ODT
VREF_FPGA_DDR3 VREF_FPGA_DDR3
1.5V_VDD 1.5V_VDD
1.5V_VDD
0.75_VTT 0.75_VTT 0.75_VTT0.75_VTT
0.75_VTT
1.5V_VDD
1.5V_VDD
1.5V_VDD
1.5V_VDD
DDR3_FPGA_BA[2:0]
DDR3_FPGA_DM[3:0]
DDR3_FPGA_A[14:0]
DDR3_FPGA_DQS_P[3:0]DDR3_FPGA_DQS_N[3:0]
DDR3_FPGA_DQ[31:0]
DDR3_FPGA_CKEDDR3_FPGA_CLK_PDDR3_FPGA_CLK_N
DDR3_FPGA_CSnDDR3_FPGA_WEnDDR3_FPGA_RASnDDR3_FPGA_CASn
DDR3_FPGA_RESETnDDR3_FPGA_ODT
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
12-DDR3 FPGA
B
11 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
12-DDR3 FPGA
B
11 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
12-DDR3 FPGA
B
11 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
12-DDR3 FPGA
C90470nFC90470nF
RN3 51RRN3 51R
13579
111315 16
1412108642
C63100nFC63100nF
C55100nFC55100nF
C58100nFC58100nF
C60100nFC60100nF
R109 4.7KR109 4.7K
C692.2nFC692.2nF
C64100nFC64100nF
C752.2nFC752.2nF
C61100nFC61100nF
RN2 51RRN2 51R
13579
111315 16
1412108642
C732.2nFC732.2nF
RN1 51RRN1 51R
13579
111315 16
1412108642
C8510nFC8510nF
C783.3nFC783.3nF
C804.7nFC804.7nF
C824.7nFC824.7nF
C65100nFC65100nF
C762.2nFC762.2nF
C62100nFC62100nF
C8410nFC8410nF
C712.2nFC712.2nF
C742.2nFC742.2nF
C86100nFC86100nF
C8310nFC8310nF
C56100nFC56100nF
C67100nFC67100nF
C66100nFC66100nF
C772.2nFC772.2nF
R111240R111240
C793.3nFC793.3nF
R110240R110240
C814.7nFC814.7nF
C722.2nFC722.2nF
C87100nFC87100nF
C91470nFC91470nF
C92470nFC92470nF
R107
100
R107
100
C702.2nFC702.2nF
C88100nFC88100nF
DDR3 DeviceU4
MT41K256M16HA-125
DDR3 DeviceU4
MT41K256M16HA-125
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4 L9
A10/APL7A11R7A12/BCnN7
RESETnT2
VSSQ B1VSSQ B9VSSQ D1
A9R3 A8T8 A7R2 A6R8
NC5 M7
NC1 J1
NC3 L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2 J9RASJ3
CK_PJ7
CSL2
BA0M2BA1N8BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2VDDD9VDDG7VDDK2
VSS A9
VSS B3
VSS E1
VSS G8
DQ0 E3
LDQS_P F3
DQ1 F7DQ2 F2DQ3 F8DQ4 H3DQ5 H8DQ6 G2DQ7 H7DQ8 D7DQ9 C3
DQ10 C8DQ11 C2DQ12 A7DQ13 A2DQ14 B8DQ15 A3
UDQS_P C7LDQS_N G3
UDQS_N B7
VSSQ D8VSSQ E2VSSQ E8VSSQ F9
VDDQH9
VDDK8VDDN1VDDN9VDDR1VDDR9
VREFDQH1VREFCAM8
VSSQ G1VSSQ G9
VDDQA1VDDQA8VDDQC1VDDQC9VDDQD2VDDQE9VDDQF1VDDQH2
VSS J2VSS J8
VSS M1VSS M9
VSS P1VSS P9
VSS T1VSS T9
C93470nFC93470nF
C68100nFC68100nF
R108 4.7KR108 4.7K
DDR3 DeviceU5
MT41K256M16HA-125
DDR3 DeviceU5
MT41K256M16HA-125
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4 L9
A10/APL7A11R7A12/BCnN7
RESETnT2
VSSQ B1VSSQ B9VSSQ D1
A9R3 A8T8 A7R2 A6R8
NC5 M7
NC1 J1
NC3 L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2 J9RASJ3
CK_PJ7
CSL2
BA0M2BA1N8BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2VDDD9VDDG7VDDK2
VSS A9
VSS B3
VSS E1
VSS G8
DQ0 E3
LDQS_P F3
DQ1 F7DQ2 F2DQ3 F8DQ4 H3DQ5 H8DQ6 G2DQ7 H7DQ8 D7DQ9 C3
DQ10 C8DQ11 C2DQ12 A7DQ13 A2DQ14 B8DQ15 A3
UDQS_P C7LDQS_N G3
UDQS_N B7
VSSQ D8VSSQ E2VSSQ E8VSSQ F9
VDDQH9
VDDK8VDDN1VDDN9VDDR1VDDR9
VREFDQH1VREFCAM8
VSSQ G1VSSQ G9
VDDQA1VDDQA8VDDQC1VDDQC9VDDQD2VDDQE9VDDQF1VDDQH2
VSS J2VSS J8
VSS M1VSS M9
VSS P1VSS P9
VSS T1VSS T9
C57100nFC57100nF
C89100nFC89100nF
C59100nFC59100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3_HPS_DM[3:0]
DDR3_HPS_CSnDDR3_HPS_WEnDDR3_HPS_RASn
DDR3_HPS_DQS_P[3:0]
DDR3_HPS_A0DDR3_HPS_A1DDR3_HPS_A2DDR3_HPS_A3DDR3_HPS_A4DDR3_HPS_A5DDR3_HPS_A6DDR3_HPS_A7DDR3_HPS_A8DDR3_HPS_A9DDR3_HPS_A10DDR3_HPS_A11DDR3_HPS_A12DDR3_HPS_A13DDR3_HPS_A14
DDR3_HPS_CKE
DDR3_HPS_RESETn
DDR3_HPS_CASn
DDR3_HPS_RESETnDDR3_HPS_ODT
DDR3_HPS_CKE
DDR3_HPS_DQ[31:0]
DDR3_HPS_A[14:0]
DDR3_HPS_A6
DDR3_HPS_A0
DDR3_HPS_CLK_P
DDR3_HPS_DQ21
DDR3_HPS_CKE
DDR3_HPS_DQS_N[3:0]
DDR3_HPS_CLK_N
DDR3_HPS_DQ23
DDR3_HPS_DM2DDR3_HPS_DM3
DDR3_HPS_CSnDDR3_HPS_WEnDDR3_HPS_RASnDDR3_HPS_CASn
DDR3_HPS_DQ20DDR3_HPS_DQ22
DDR3_HPS_A1
DDR3_HPS_BA0DDR3_HPS_BA1DDR3_HPS_BA2DDR3_HPS_RESETn
DDR3_HPS_DQ16DDR3_HPS_DQ18DDR3_HPS_DQ17DDR3_HPS_DQ19
DDR3_HPS_CLK_P
DDR3_HPS_ODTDDR3_HPS_ZQ2
DDR3_HPS_A2DDR3_HPS_A3
DDR3_HPS_DQ29DDR3_HPS_DQ27DDR3_HPS_DQ24DDR3_HPS_DQ31
DDR3_HPS_A4DDR3_HPS_A5DDR3_HPS_A6DDR3_HPS_A7
DDR3_HPS_DQ28
DDR3_HPS_CLK_PDDR3_HPS_DQ30DDR3_HPS_DQ25DDR3_HPS_DQ26
DDR3_HPS_A8DDR3_HPS_A9DDR3_HPS_A10DDR3_HPS_A11
DDR3_HPS_DQS_P2DDR3_HPS_DQS_N2DDR3_HPS_DQS_P3DDR3_HPS_DQS_N3
DDR3_HPS_A10DDR3_HPS_A9DDR3_HPS_RASnDDR3_HPS_CSnDDR3_HPS_BA0DDR3_HPS_A8
DDR3_HPS_A11
DDR3_HPS_A12DDR3_HPS_A13DDR3_HPS_A14
DDR3_HPS_CLK_N
DDR3_HPS_BA[2:0]
DDR3_HPS_CASnDDR3_HPS_A7DDR3_HPS_A12DDR3_HPS_A0
DDR3_HPS_WEn
DDR3_HPS_DQ2DDR3_HPS_DQ4DDR3_HPS_DQ7DDR3_HPS_DQ5DDR3_HPS_DQ3DDR3_HPS_DQ0DDR3_HPS_DQ6DDR3_HPS_DQ1DDR3_HPS_DQ10DDR3_HPS_DQ13DDR3_HPS_DQ8DDR3_HPS_DQ12DDR3_HPS_DQ11
DDR3_HPS_CKE
DDR3_HPS_DQ15DDR3_HPS_DQ9
DDR3_HPS_CLK_PDDR3_HPS_CLK_N
DDR3_HPS_DQ14
DDR3_HPS_DQS_P0DDR3_HPS_DQS_N0
DDR3_HPS_DM0DDR3_HPS_DM1
DDR3_HPS_CSn
DDR3_HPS_DQS_P1DDR3_HPS_DQS_N1
DDR3_HPS_WEnDDR3_HPS_RASnDDR3_HPS_CASn
DDR3_HPS_BA0DDR3_HPS_BA1DDR3_HPS_BA2DDR3_HPS_RESETnDDR3_HPS_ODTDDR3_HPS_ZQ
DDR3_HPS_CLK_N
DDR3_HPS_A13DDR3_HPS_A14
DDR3_HPS_A2
DDR3_HPS_BA2
DDR3_HPS_ODT
DDR3_HPS_BA1
DDR3_HPS_A3
DDR3_HPS_A4DDR3_HPS_A5DDR3_HPS_A1
1.5V_VDD
1.5V_VDD
0.75_VTT
1.5V_VDD
1.5V_VDD
1.5V_VDD
0.75_VTT
1.5V_VDD
0.75_VTT
1.5V_VDD
VREF_HPS_DDR3
0.75_VTT
VREF_HPS_DDR3
0.75_VTT
1.5V_VDD
1.5V_VDD
DDR3_HPS_DQS_P[3:0]DDR3_HPS_DQS_N[3:0]
DDR3_HPS_DQ[31:0]
DDR3_HPS_CKEDDR3_HPS_CLK_PDDR3_HPS_CLK_N
DDR3_HPS_WEnDDR3_HPS_RASn
DDR3_HPS_CSn
DDR3_HPS_RESETnDDR3_HPS_ODT
DDR3_HPS_CASn
DDR3_HPS_BA[2:0]
DDR3_HPS_DM[3:0]
DDR3_HPS_A[14:0]
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
13-DDR3 HPS
B
13 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
13-DDR3 HPS
B
13 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
13-DDR3 HPS
B
13 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
13-DDR3 HPS
C1253.3nFC1253.3nF
C94100nFC94100nF
C104100nFC104100nF
C139100nFC139100nF
C13410nFC13410nF
C96100nFC96100nF
C1242.2nFC1242.2nF
R116240R116240
DDR3 DeviceU6
MT41K256M16HA-125
DDR3 DeviceU6
MT41K256M16HA-125
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4 L9
A10/APL7A11R7A12/BCnN7
RESETnT2
VSSQ B1VSSQ B9VSSQ D1
A9R3 A8T8 A7R2 A6R8
NC5 M7
NC1 J1
NC3 L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2 J9RASJ3
CK_PJ7
CSL2
BA0M2BA1N8BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2VDDD9VDDG7VDDK2
VSS A9
VSS B3
VSS E1
VSS G8
DQ0 E3
LDQS_P F3
DQ1 F7DQ2 F2DQ3 F8DQ4 H3DQ5 H8DQ6 G2DQ7 H7DQ8 D7DQ9 C3
DQ10 C8DQ11 C2DQ12 A7DQ13 A2DQ14 B8DQ15 A3
UDQS_P C7LDQS_N G3
UDQS_N B7
VSSQ D8VSSQ E2VSSQ E8VSSQ F9
VDDQH9
VDDK8VDDN1VDDN9VDDR1VDDR9
VREFDQH1VREFCAM8
VSSQ G1VSSQ G9
VDDQA1VDDQA8VDDQC1VDDQC9VDDQD2VDDQE9VDDQF1VDDQH2
VSS J2VSS J8
VSS M1VSS M9
VSS P1VSS P9
VSS T1VSS T9
C1182.2nFC1182.2nF
C1284.7nFC1284.7nF
C137100nFC137100nF
C1122.2nFC1122.2nF
C98100nFC98100nF
C12910nFC12910nF
C1082.2nFC1082.2nF
C105100nFC105100nF
C13210nFC13210nF
C140100nFC140100nF
C143470nFC143470nF
C1172.2nFC1172.2nF
C99100nFC99100nF
C1263.3nFC1263.3nF
C95100nFC95100nF
C145470nFC145470nF
C1192.2nFC1192.2nF
C1102.2nFC1102.2nF
C138100nFC138100nF
C1132.2nFC1132.2nF
C101100nFC101100nF
C13310nFC13310nF
C141470nFC141470nF
C103100nFC103100nF
C146470nFC146470nF
C107100nFC107100nF C144
470nFC144470nF
R112
100
R112
100
C1202.2nFC1202.2nF
C1112.2nFC1112.2nF
R115240R115240
C97100nFC97100nF
C102100nFC102100nF
C106100nFC106100nF
DDR3 DeviceU7
MT41K256M16HA-125
DDR3 DeviceU7
MT41K256M16HA-125
A5P2 A4P8 A3N2 A2P3 A1P7 A0N3
NC4 L9
A10/APL7A11R7A12/BCnN7
RESETnT2
VSSQ B1VSSQ B9VSSQ D1
A9R3 A8T8 A7R2 A6R8
NC5 M7
NC1 J1
NC3 L1
ZQL8
CK_NK7
WEL3
CKEK9
A13T3
ODTK1
NC2 J9RASJ3
CK_PJ7
CSL2
BA0M2BA1N8BA2M3
CASK3
UDMD3
A14T7
LDME7
VDDB2VDDD9VDDG7VDDK2
VSS A9
VSS B3
VSS E1
VSS G8
DQ0 E3
LDQS_P F3
DQ1 F7DQ2 F2DQ3 F8DQ4 H3DQ5 H8DQ6 G2DQ7 H7DQ8 D7DQ9 C3
DQ10 C8DQ11 C2DQ12 A7DQ13 A2DQ14 B8DQ15 A3
UDQS_P C7LDQS_N G3
UDQS_N B7
VSSQ D8VSSQ E2VSSQ E8VSSQ F9
VDDQH9
VDDK8VDDN1VDDN9VDDR1VDDR9
VREFDQH1VREFCAM8
VSSQ G1VSSQ G9
VDDQA1VDDQA8VDDQC1VDDQC9VDDQD2VDDQE9VDDQF1VDDQH2
VSS J2VSS J8
VSS M1VSS M9
VSS P1VSS P9
VSS T1VSS T9
C1212.2nFC1212.2nF
C1142.2nFC1142.2nF
C13110nFC13110nF
C1092.2nFC1092.2nF
RN6 51RRN6 51R
13579
111315 16
1412108642
C1222.2nFC1222.2nF
R114 4.7KR114 4.7K
C1152.2nFC1152.2nF
C1274.7nFC1274.7nF
C142470nFC142470nF
C100100nFC100100nF
R113 4.7KR113 4.7K
RN5 51RRN5 51R
13579
111315 16
1412108642
C1232.2nFC1232.2nF
C13010nFC13010nF
C135100nFC135100nF
C1162.2nFC1162.2nF
C136100nFC136100nF
RN4 51RRN4 51R
13579
111315 16
1412108642
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DSS_D0DSS_D1DSS_D2DSS_D3DSS_D4DSS_D5DSS_D6DSS_D7
DSS_D8DSS_D9DSS_D10DSS_D11DSS_D12DSS_D13DSS_D14DSS_D15
DSS_D16DSS_D17DSS_D18DSS_D19DSS_D20DSS_D21DSS_D22DSS_D23
DSS_ACBIASDSS_HSYNCDSS_VSYNC
DSS_CLK
TOUCH_X1TOUCH_X2TOUCH_Y1TOUCH_Y2
SPI0_FPGA_CLKSPI0_FPGA_MOSISPI0_FPGA_MISOSPI0_FPGA_CSn1LCD_I2C1_SCLLCD_I2C1_SDA
DSS_D[23:0]
DSS_D0DSS_D1DSS_D2DSS_D3DSS_D4DSS_D5DSS_D6DSS_D7
DSS_D8DSS_D9DSS_D10DSS_D11DSS_D12DSS_D13DSS_D14DSS_D15
DSS_D16DSS_D17DSS_D18DSS_D19DSS_D20DSS_D21DSS_D22DSS_D23
DSS_ACBIASDSS_HSYNCDSS_VSYNCDSS_CLK
TOUCH_X1TOUCH_X2TOUCH_Y1TOUCH_Y2
RESET_HPS_GLOBELnLCD_PWM
SPI0_FPGA_CLKSPI0_FPGA_CSn0SPI0_FPGA_MOSI
SPI0_FPGA_MISOTSP_FPGA_INTn
TOUCH_X1TOUCH_Y1TOUCH_X2TOUCH_Y2
LCD_I2C1_SDALCD_I2C1_SCL
LCD_PWM
SPI0_FPGA_CLKSPI0_FPGA_MOSI
SPI0_FPGA_CSn0SPI0_FPGA_MISO
TSP_FPGA_INTn
DSS_D[23:0]
DSS_ACBIASDSS_HSYNCDSS_VSYNCDSS_CLK
RESET_HPS_GLOBELn
SPI0_FPGA_CSn1
3.3V_LCD_VDD
5V_LCD_VDD3.3V_VDD
3.3V_AVDD_TOUCH
5V_LCD_VDD5V_VDD 3.3V_LCD_VDD3.3V_VDD 3.3V_AVDD_TOUCH3.3V_VDD
LCD_I2C1_SDALCD_I2C1_SCL
LCD_PWM
SPI0_FPGA_CLKSPI0_FPGA_MOSI
SPI0_FPGA_CSn0
TSP_FPGA_INTn
SPI0_FPGA_MISO
DSS_D[23:0]
DSS_ACBIASDSS_HSYNCDSS_VSYNCDSS_CLK
RESET_HPS_GLOBELn
SPI0_FPGA_CSn1
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
14-FPGA LCD
B
14 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
14-FPGA LCD
B
14 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
14-FPGA LCD
B
14 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
BLUE
GREEN
RED
14-FPGA LCD
LCD DSS INTERFACE
J4
LCD_50P_R5_2H
J4
LCD_50P_R5_2H
B01B12B23B34B45B56B67B78GND19G010G111G212G313G414G515G616G717GND218R019R120R221R322R423R524R625R726GND327DEN28HSYNC29VSYNC30GND431CLK32GND533
X+34X-35Y+36Y-37
SPI_CLK38SPI_MOSI39SPI_MISO40SPI_CS41IIC_CLK42IIC_DAT43GND644
VDD145VDD246VDD347VDD448
RESET49PWREN50
GND751GND852
T28T28
C14922nFC14922nF
T22T22
U8
TSC2046IPWR
U8
TSC2046IPWR
VCC 1X+ 2Y+ 3X- 4Y- 5
GND 6VBAT 7AUX 8VREF09 IOVDD10 PENIRE#11 DOUT12 BUSY13 DIN14 CS#15 DCLK16
T29T29
C16710uFC16710uF
FB17
600R,FB
FB17
600R,FB
C14822nFC14822nF
T23T23
T18T18
C14722nFC14722nF
C152100nFC152100nF
FB9
180R,FB
FB9
180R,FB
T31T31
R118 0RR118 0R
T14T14
T43T43
C155100nFC155100nF
T30T30
FB10
600R,FB
FB10
600R,FB
T16T16
R119 0RR119 0R
C15310uFC15310uF
T36T36
T17T17
T15T15
R121 10KR121 10K
T32T32
T37T37
T44T44
C154100nFC154100nF
C15110uFC15110uF
T33T33
C156100nFC156100nF
T38T38
T24T24
T9T9
T11T11
T34T34
T20T20
T39T39
T8T8
T25T25
R117 0RR117 0R
T21T21
R120
10K
R120
10K
T26T26
T45T45
T12T12
T35T35
T27T27
C15022nFC15022nF
T10T10
T19T19
T13T13
C157100nFC157100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DSS_D0DSS_D1DSS_D2DSS_D3DSS_D4DSS_D5DSS_D6DSS_D7DSS_D8DSS_D9DSS_D10DSS_D11DSS_D12DSS_D13DSS_D14DSS_D15DSS_D16DSS_D17DSS_D18DSS_D19DSS_D20DSS_D21DSS_D22DSS_D23
DSS_D[23:0]
DSS_ACBIAS
DSS_HSYNCDSS_VSYNCVSYNC_OUTHSYNC_OUT
RESET_HPS_GLOBELn
DDC_SCLDDC_SDA
I2C_SDA_HDMIDDCI2C_SCL_HDMIDDC
DDC_SDADDC_SCL
HDMI_I2S_DHDMI_I2S_CK
VGA_RED
VGA_BLU
5V_HSYNC5V_VSYNC
HDMI_TX2+HDMI_TX2-
HDMI_TX1+HDMI_TX1-
HDMI_TX0+HDMI_TX0-
HDMI_CLK+HDMI_CLK-
VGA_XI
HSYNC_OUT
VSYNC_OUT
5V_HSYNC
5V_VSYNC
HDMI_I2S_WS
VGA_XO
HDMI_TX2-
HDMI_CLK+HDMI_CLK-
HDMICONN_I2CSDAHDMICONN_I2CSCL
HDMI_TX2+
I2C_SCL_HDMIDDCI2C_SDA_HDMIDDC HDMICONN_I2CSDA
HDMICONN_I2CSCL
DDC_SDA
HDMI_I2S_D
HDMI_I2S_WSHDMI_I2S_CK
DDC_SCL
DSS_D[23:0]
DSS_ACBIASDSS_HSYNCDSS_VSYNC
RESET_HPS_GLOBELn
HPS_DVI_IRQ
DSS_CLK
VGA_GRNI2C_SDA_VGAI2C_SCL_VGA
I2C_SDA_VGAI2C_SCL_VGA
DSS_CLK
HDMI_TX0+HDMI_TX0-
HDMI_TX1+HDMI_TX1-
HDMICONN_HPLGHPS_DVI_IRQ
3.3V_VDD
VGA_VDDGND_SHIELDS
3.3V_AVDD_VGA
3.3V_VDD
1.8V_AVDD_VGA
1.8V_VDD
3.3V_VDD
3.3V_VDD
5V_VDD
5V_VDD
3.3V_VDD
GND_SHIELDS
5V_VDD
5V_VDD
3.3V_VDD5V_VDD
VGA_VDD5V_VDD
AGND_VGA
3.3V_VDD
3.3V_AVDD_VGA
1.8V_AVDD_VGA1.8V_VDD
AGND_VGA
VGA_VDD
3.3V_AVDD_VGA
VGA_VDD
VGA_VDD
VGA_VDD
DDC_SCLDDC_SDA
HDMI_I2S_DHDMI_I2S_CKHDMI_I2S_WS
DSS_D[23:0]
DSS_ACBIASDSS_HSYNCDSS_VSYNC
RESET_HPS_GLOBELn
HPS_DVI_IRQ
I2C_SCL_VGAI2C_SDA_VGA
DSS_CLK
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
15-FPGA VGA/HDMI
B
15 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
15-FPGA VGA/HDMI
B
15 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
15-FPGA VGA/HDMI
B
15 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
15-FPGA VGA/HDMI
Near Pin53,61
Near Pin42,10
Near Pin41,30
Near Pin9,60
C190100nFC190100nF
R126 4.7KR126 4.7K
R127
75
R127
75
C173100nFC173100nF
R133 1.2KR133 1.2K
C187100nFC187100nF
FB22
600R,FB
FB22
600R,FB
C193100nFC193100nF
J5
CN_HDMI_SMD19_F
J5
CN_HDMI_SMD19_F
DAT2-3DAT2+1DAT2_S2
SCL15SDA16
DAT-6DAT+4DAT1_S5
+5V 18DDC/CEC 17
HPLG19
DAT0-9DAT0+7DAT0_S8
CLK+10CLK-12CLK_S11
MTG1 20
MTG2 21
MTG3 22
MTG4 23
CEC 13NC 14
C168100nFC168100nF C853
10uF
C853
10uF
D46TVSD46TVS
FB13180R,FB
FB13180R,FB
C579100nFC579100nF
R138 10KR138 10K
C18610uFC18610uF
C184100nFC184100nF
C16010pFC16010pF
FB15180R,FB
FB15180R,FB
C18910uFC18910uF
R152 10KR152 10K
C51100nFC51100nF
C16110pFC16110pF
C181100nFC181100nF
R123
75
R123
75
R140 10KR140 10K
FB12
47R,FB
FB12
47R,FB
C16410pFC16410pF
C17510uFC17510uF
C171 22pFC171 22pF
FB21
600R,FB
FB21
600R,FB
R135 10KR135 10K
D1BAT54SD1BAT54S
123
D47BTR6V8UD
D47BTR6V8UD
1 2 3 4 5678910
C15922pFC15922pF
C192100nFC192100nF
R128 NC0402R128 NC0402
C48100nFC48100nF
C18010uFC18010uF
R125 4.7KR125 4.7K
R153 10KR153 10K
C183100nFC183100nF
U10
SN74LVC2G07DCK
U10
SN74LVC2G07DCK
1A1GND22A3 2Y 4VCC 51Y 6
D2BAT54SD2BAT54S
123
C179100nFC179100nF
C854
10uF
C854
10uF
C15810pFC15810pF
D3BAT54SD3BAT54S
123
C185100nFC185100nF
D48BTR6V8UD
D48BTR6V8UD
1 2 3 4 5678910
R1361KR1361K
D5BAT54SD5BAT54S
123
R1341KR1341K
X925MHzX925MHz
1
2
3
4
C174100nFC174100nF
C19110uFC19110uF
C16222pFC16222pF
C18210uFC18210uF
D4BAT54SD4BAT54S
123
C16522pFC16522pF
R151 10KR151 10K
C177100nFC177100nF
CN1
VGA FEMALE
CN1
VGA FEMALE
R1
G2
B3
HSYNC13VSYNC14
GND0 5GND_R 6GND_G 7GND_B 8
KEY/+5V 9
GND1 10
SHIELD1 16SHIELD2 17
ID0/REV 11ID2/REV 4ID1/SDA 12ID3/SCL 15
R141
20K
R141
20K
R130 0RR130 0R
C17810uFC17810uF
FB14
47R,FB
FB14
47R,FB
FB19
47R,FB
FB19
47R,FB
D49TVSD49TVS
FB16
47R,FB
FB16
47R,FB
FB24
600R,FB
FB24
600R,FB
U9
CH7033B
U9
CH7033B
D029D128D227D326D425D521D620D719D818D917D1016D1115D1214D1313D1412D158D166D175D184D193D202D211D2288D2387
CE/CSB84
GCLK82H/WEB86V85
HSO/CSYNC48 VSO49
RESETB7
ISET80
SPC54SPD55
XI/FIN68
XO67
IRQ81
SPCM72SPDM69
DDC_SC63DDC_SD64
RESERVE50
I2S_D/SPDIF56I2S_CK58I2S_WS57
DAC0 78
DAC1 76
DAC2 74
AVDD1 23AVDD2 46
AVDD_DAC1 77AVDD_DAC2 73
VDDMQ1 53VDDMQ2 61
VDDMS1 60VDDMS2 9
AVDD_PLL 71
DVDD1 42DVDD2 10
VDDIO 83
AGND_PLL 70AGND_DAC1 79AGND_DAC2 75
AGND1 47AGND2 22
DGND 45GNDMQ1 52GNDMQ2 62GNDMS1 11GNDMS2 59
PGND 89
TDC2P 40TDC2N 39
TDC1P 37TDC1N 36
TDC0P 35TDC0N 34
HPD 51TLCN 31TLCP 32
VDDH1 30VDDH2 41
VSSH1 33VSSH2 38
NC124NC243NC344NC465NC566
C194100nFC194100nF
FB18
47R,FB
FB18
47R,FB
U3
TXS0102DCTR
U3
TXS0102DCTR
B2 1GND 2
VCCA3
A24 A15
OE6
VCCB 7B1 8 R154 10KR154 10K
C172 22pFC172 22pF
FB25
600R,FB
FB25
600R,FB
C16310pFC16310pF
C16610pFC16610pF
C176100nFC176100nF
C188100nFC188100nF
R587 10KR587 10K
FB11
47R,FB
FB11
47R,FB
R124
75
R124
75
R144
52.3K
R144
52.3K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ADC1_MODE
ADC1_INP
ADC1_INN
AMP1_OUTP
AMP1_OUTN
AMP2_OUTPADC2_INP
ADC2_INN
ADC2_MODE
AMP1_OUTPAMP1_OUTN
AMP2_OUTPAMP2_OUTN
AMP2_OUTNAMP2_OUTN
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
VCM_AMP
3.3V_AMP
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
ADC_GND
3.3V_AMP
ADC_GND
VCM_AMP
ADC_GND ADC_GND
3.3V_VDD 3.3V_AMP
ADC_GND ADC_GND
AMP1_OUTPAMP1_OUTN
AMP2_OUTPAMP2_OUTN
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
16-FPGA ADC Pre-AMP
B
16 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
16-FPGA ADC Pre-AMP
B
16 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
16-FPGA ADC Pre-AMP
B
16 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
16-FPGA ADC Pre-AMP
Keep 75ohm Trace Impedance for Single Ended ADC_IN
Addd Jumper JP1/JP3 When Using Differential Signal Input
C217100nFC217100nF
L8 15nHL8 15nH1 2
C226100nFC226100nF
C208
NC0402
C208
NC0402
C225100nFC225100nF
R584330R584330C829
22pFC82922pF
C227100nFC227100nF
U14
ADL5562
U14
ADL5562
VIP21VIP12
VIN13VIN24
ENBL12
VCC05VCC16VCC27
VOP 11VON 10
VCOM 9
EP 17
GND0 13GND1 14GND2 15GND3 16VCC38
R179 22R179 22
C224100nFC224100nF
R163 40.2R163 40.2
R582 150R582 150
R168 0RR168 0R
L5 15nHL5 15nH1 2
R585 33R585 33
L1 15nHL1 15nH1 2
R178 40.2R178 40.2
C212100nFC212100nF
R172 0RR172 0R
C205100nFC205100nF
J7 SMAJ7 SMA
1
52 3 4
C211100nFC211100nF
U13
ADL5562
U13
ADL5562
VIP21VIP12
VIN13VIN24
ENBL12
VCC05VCC16VCC27
VOP 11VON 10
VCOM 9
EP 17
GND0 13GND1 14GND2 15GND3 16VCC38
R166 0RR166 0R
C201100nFC201100nF
C204100nFC204100nF
C247100nFC247100nF
FB30
600R,FB
FB30
600R,FB
C830 68pFC830 68pF
R173 0RR173 0R
MABA
T47
MABA
T475
4
1
32
R180 40.2R180 40.2
C199100nFC199100nF
C202100nFC202100nF
J8 SMAJ8 SMA
1
52 3 4 R175 22R175 22
R158 0RR158 0R
R165 40.2R165 40.2
L11 15nHL11 15nH1 2
C831 68pFC831 68pF
JP3JP3
C220100nFC220100nF
R578330R578330
J6 SMAJ6 SMA
1
52 3 4 R160 22R160 22
C21310uFC21310uF
R580 33R580 33
R579 33R579 33
R577 150R577 150
R156
1K
R156
1K
R182 0RR182 0R
C219100nFC219100nF
C215100nFC215100nF
C223
NC0402
C223
NC0402
C209100nFC209100nF
C203100nFC203100nF
C206100nFC206100nF
R576 150R576 150R164 22R164 22
C210100nFC210100nF
FB35
600R,FB
FB35
600R,FB
R159 0RR159 0R
C19810uFC19810uF
J9 SMAJ9 SMA
1
52 3 4
JP1JP1
C200100nFC200100nF
C827 68pFC827 68pF
R181 0RR181 0R
C216100nFC216100nF
MABA
T46
MABA
T465
4
1
32 C826
22pFC82622pF
C207100nFC207100nF
C248100nFC248100nF
R171
1K
R171
1K
R167 0RR167 0R
C218100nFC218100nF
R581 150R581 150
R397 0RR397 0R
R583 33R583 33
C828 68pFC828 68pF
C214100nFC214100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AMP1_OUTNAMP1_OUTP
AMP2_OUTNAMP2_OUTP
ADC_CLK105_N
ADC_CLK105_P
FPGA_ADC_SPICLKFPGA_ADC_SPICSn
FPGA_ADC_SPIMOSI
ADC_ORpADC_ORn
FPGA_ADC_OEB
ADC_D0BADC_D1BADC_D2BADC_D3B
ADC_Dp11ADC_Dn11ADC_Dp10ADC_Dn10ADC_Dp9ADC_Dn9ADC_Dp8ADC_Dn8
ADC_Dn7ADC_Dp7
ADC_Dp6
ADC_Dn6ADC_Dp5ADC_Dn5
ADC_Dp4ADC_Dn4
ADC_Dn3ADC_Dp3
ADC_Dp2ADC_Dn2ADC_Dp1ADC_Dn1ADC_Dp0ADC_Dn0
ADC_DCOpADC_DCOn
AMP1_OUTNAMP1_OUTP
AMP2_OUTNAMP2_OUTP
ADC_ORpADC_ORn
ADC_DCOpADC_DCOn
ADC_Dp[11:0]ADC_Dn[11:0]
FPGA_ADC_OEB
FPGA_ADC_SPIMOSIFPGA_ADC_SPICLKFPGA_ADC_SPICSn
ADC_CLK105_NADC_CLK105_P
ADC_D0BADC_D1BADC_D2BADC_D3B
1.8V_AVDD
1.8V_VDD
VREF_ADC
VCM_ADC
1.8V_AVDD1.8V_VDD
ADC_GND
1.8V_AVDD
1.8V_VDD
VREF_ADC VCM_ADC
ADC_GND
ADC_GND
ADC_GND
ADC_GND ADC_GND
ADC_Dp[11:0]ADC_Dn[11:0]
ADC_ORpADC_ORn
ADC_DCOpADC_DCOn
FPGA_ADC_OEB
FPGA_ADC_SPIMOSIFPGA_ADC_SPICLKFPGA_ADC_SPICSn
ADC_CLK105_NADC_CLK105_P
AMP1_OUTNAMP1_OUTP
AMP2_OUTNAMP2_OUTP
ADC_D3BADC_D2BADC_D1BADC_D0B
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
17-FPGA ADC Sampling
B
17 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
17-FPGA ADC Sampling
B
17 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
17-FPGA ADC Sampling
B
17 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
17-FPGA ADC Sampling
C246100nFC246100nF
FB31
600R,FB
FB31
600R,FB
C238100nFC238100nF
FB59
600R,FB
FB59
600R,FB
C230100nFC230100nF
R186
100
R186
100
C234100nFC234100nF
C239100nFC239100nF
C231100nFC231100nF
C236100nFC236100nF
C235100nFC235100nF
C240100nFC240100nF
C232100nFC232100nF
C237100nFC237100nF
C241100nFC241100nF
C233100nFC233100nF
R188 10KR188 10K
C228
10uF
C228
10uF
C245100nFC245100nF
C229
10uF
C229
10uF
C242
10uF
C242
10uF
R185 0RR185 0R
FB76
600R,FB
FB76
600R,FB
T48T48
C244
1uF
C244
1uF
FB56
600R,FB
FB56
600R,FB
C243
10uF
C243
10uF
U15
AD9628
U15
AD9628
AVDD49AVDD_150AVDD_253AVDD_354AVDD_459AVDD_560AVDD_663AVDD_764
DRVDD10DRVDD_119DRVDD_228DRVDD_337
VIN-A52VIN+A51
VIN-B61VIN+B62
VREF55VCM57
CLK+1 CLK-2
SCLK/DFS45CSB46
SDIO/DCS44
SYNC3SENSE56RBIAS58
ORA/OR+ 43D11A/OR- 42
OEB47
NC3 4NC2 5NC1 6
NC4 7
D0B/NC 8D1B/NC 9D2B/NC 11D3B/NC 12
D10A/D11+ 41D9A/D11- 40D8A/D10+ 39D7A/D10- 38D6A/D9+ 36D5A/D9- 35D4A/D8+ 34D3A/D8- 33D2A/D7+ 32D1A/D7- 31D0A/D6+ 30
NC/D6- 29NC/D5+ 27NC/D5- 26
DCOB/D4+ 23ORB/D4- 22
D11B/D3+ 21D10B/D3- 20D9B/D2+ 18D8B/D2- 17D7B/D1+ 16D6B/D1- 15D5B/D0+ 14D4B/D0- 13
NC/DCO+ 25DCOA/DCO- 24
PWDN48
EP65
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDI_TXCAP_NSDI_TXCAP_P
SDI_TX_P
SDI_TX_N
SDI_TX_SD_HDn
SDI_RSTInSDI_TX_ENSDI_I2C_SDASDI_I2C_SCL
SDI_FAULTn
SDI_EQIN_P1
SDI_IN_P1
SDI_EQIN_N1
SDO_NSDO_P
SDI_RX_P
SDI_RX_N
SDI_RX_CDn
SDI_RX_BYPASS
SDI_RX_EN
SDI_TX_SD_HDn
SDI_RX_EN
SDI_TX_EN
SDI_RX_BYPASS
SDI_RSTInSDI_FAULTn
SDI_I2C_SDASDI_I2C_SCL
SDI_TX_PSDI_TX_N
SDI_RX_PSDI_RX_N
3.3V_SDI
3.3V_SDI
3.3V_SDI
3.3V_SDI
3.3V_SDI
3.3V_SDI
3.3V_SDI
3.3V_VDD 3.3V_SDI
SDI_TX_SD_HDn
SDI_RX_EN
SDI_TX_EN
SDI_RX_BYPASS
SDI_RSTInSDI_FAULTn
SDI_I2C_SCLSDI_I2C_SDA
SDI_TX_NSDI_TX_P
SDI_RX_PSDI_RX_N
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
18-FPGA SDI Xcvr
B
18 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
18-FPGA SDI Xcvr
B
18 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
18-FPGA SDI Xcvr
B
18 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
18-FPGA SDI Xcvr
SPI_EN=GND: non-SPI mode, LMH0344 Compatible
C253
4.7uF
C253
4.7uF
R192 750R192 750
FB32
600R,FB
FB32
600R,FB
U18
LMH0384
U18
LMH0384
VEE1 1
SPI_EN4
SDI2SDI3
AEC+5
AEC-6
BYPASS/CD#7
MUTEref8 VEE/SS 9
SDO 11SDO 10AUTO_SLEEP/MISO12
MUTE/SCK14
CD/MOSI15
VCC1 13VCC2 16
DAP 17
R193 75R193 75
R195 0RR195 0R
R207
0R
R207
0R
C266
1uF
C266
1uF
J11 SMBJ11 SMB
1
52 3 4
C257100nF
C257100nF
C260
4.7uF
C260
4.7uF
C261
4.7uF
C261
4.7uF
R204 37.4R204 37.4
R194 75R194 75
C2514.7uFC2514.7uF
R208 75R208 75
C2621uFC2621uF
R202 75R202 75
C2524.7uFC2524.7uF
J10 SMBJ10 SMB
1
5 234
R196 49.9R196 49.9
C259100nF
C259100nF
R198
10K
R198
10K
C256100nF
C256100nF
C255
22uF
C255
22uFL16 5.6nHL16 5.6nH1 2
C250
4.7uF
C250
4.7uF
C2644.7uFC2644.7uF
R197 49.9R197 49.9
R203 75R203 75
R206NC0402R206NC0402
CableDriver
U17
LMH0303
CableDriver
U17
LMH0303
SDI1SDI2
VEE 3
RREF4
VCC 9
SD/HD10SDO 12SDO 11
CENTERPAD 17
RSTI5ENABLE6SDA7SCL8
FAULT 13
NC514NC615
RSTO 16
R205 NC0402R205 NC0402
L14 5.6nHL14 5.6nH1 2
C2631uFC2631uF
C25410nFC25410nF
L15 5.6nHL15 5.6nH1 2
D6
Green
D6
Green
C2654.7uFC2654.7uF
R199 75R199 75
R20175R20175
C258100nF
C258100nF
T94T94R200 75R200 75
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAM_D0CAM_D1CAM_D2CAM_D3CAM_D4CAM_D5CAM_D6CAM_D7CAM_D8CAM_D9CAM_D10CAM_D11
CAM_HSCAM_VS
CAM_FLDCAM_WENCAM_STROBECAM_SDACAM_SCL
CAM_CLK
CAM_PCLK
CAM_D8CAM_D9CAM_D10CAM_D11
CAM_D0CAM_D1CAM_D2CAM_D3CAM_D4CAM_D5CAM_D6CAM_D7
CAM_HSCAM_VS
CAM_FLDCAM_WEN
CAM_STROBECAM_SDACAM_SCL
CAM_CLK
CAM_PCLK
CAM_HSCAM_STROBE
CAM_WENCAM_CLK
CAM_VS
CAM_PCLK
CAM_D[11:0]
CAM_FLD
CAM_SCLCAM_SDA
FPGA_I2C1_SCLFPGA_I2C1_SDA
CAM_SCLCAM_SDA
FPGA_I2C1_SCLFPGA_I2C1_SDA
3.3V_Camer
3.3V_Camer_IO3.3V_VDD
3.3V_Camer3.3V_VDD
3.3V_VDD
1.8V_VDD
3.3V_Camer_IO
CAM_HSCAM_STROBE
CAM_PCLK
CAM_D[11:0]
CAM_VS
CAM_CLKCAM_WEN
CAM_FLD
CAM_SCLCAM_SDA
FPGA_I2C1_SDAFPGA_I2C1_SCL
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
19-FPGA Camera
B
19 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
19-FPGA Camera
B
19 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
19-FPGA Camera
B
19 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
19-FPGA Camera
J12
FPC_30P
J12
FPC_30P
GND 1
D02D13D24D35D46D57D68D79D810D911D1012D1113
GND1 14
PCLK15
GND2 16
HSYNC17VSYNC19
VDD5018 VDD3320
XCLKA21XCLKB22
GND3 23
FLD24WEN25STROBE26SDA27SCL28
GND4 29
VDD1830
MT 31MT2 32
C272
10uF
C272
10uF
T68T68
T65T65
T62T62
T59T59
T56T56
T53T53
T50T50
C273
10uF
C273
10uF
U35
TXS0102DCTR
U35
TXS0102DCTR
B21GND2
VCCA 3
A2 4A1 5
OE 6
VCCB7B18
C270100nFC270100nF
C268100nFC268100nF
C26722pFC26722pF T67T67
R210
0R
R210
0R
T64T64
C271100nFC271100nF
T61T61
T58T58
T55T55
T52T52
T49T49
C274
10uF
C274
10uF
C275
10uF
C275
10uF
C269100nFC269100nF
FB33
600R,FB
FB33
600R,FB
C50100nFC50100nF
T69T69
T66T66
T63T63
T60T60
T57T57
T54T54
T51T51
C249100nFC249100nF
FB34
600R,FB
FB34
600R,FB
R209 0RR209 0R
R212
0R
R212
0R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA_TX_D_P0FPGA_TX_D_N0FPGA_TX_D_P1FPGA_TX_D_N1FPGA_TX_D_P2FPGA_TX_D_N2FPGA_TX_D_P3FPGA_TX_D_N3
FPGA_H_SMBCLKFPGA_H_SMBDAT
FPGA_TX_H_P0FPGA_TX_H_N0FPGA_TX_H_P1FPGA_TX_H_N1FPGA_TX_H_P2FPGA_TX_H_N2FPGA_TX_H_P3FPGA_TX_H_N3
FPGA_RX_D_P0FPGA_RX_D_N0FPGA_RX_D_P1FPGA_RX_D_N1FPGA_RX_D_P2FPGA_RX_D_N2FPGA_RX_D_P3FPGA_RX_D_N3
FPGA_RX_H_P0FPGA_RX_H_N0FPGA_RX_H_P1FPGA_RX_H_N1FPGA_RX_H_P2FPGA_RX_H_N2FPGA_RX_H_P3FPGA_RX_H_N3
nPERSTL0
nPERSTL0
FPGA_TX_H_P[3:0]FPGA_TX_H_N[3:0]
FPGA_RX_H_P[3:0]FPGA_RX_H_N[3:0]
FPGA_H_SMBCLKFPGA_H_SMBDAT
FPGA_TX_D_P[3:0]FPGA_TX_D_N[3:0]
FPGA_RX_D_P[3:0]FPGA_RX_D_N[3:0]
5V_EXP25V_VDD 5V_EXP2
FPGA_H_SMBDATFPGA_H_SMBCLK
FPGA_TX_H_P[3:0]FPGA_TX_H_N[3:0]
FPGA_RX_H_P[3:0]FPGA_RX_H_N[3:0]
FPGA_TX_D_P[3:0]FPGA_TX_D_N[3:0]
FPGA_RX_D_P[3:0]FPGA_RX_D_N[3:0]
nPERSTL0
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
20-FPGA Extend IF
B
20 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
20-FPGA Extend IF
B
20 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
20-FPGA Extend IF
B
20 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
20-FPGA Extend IF
FB90
60R,FB
FB90
60R,FB
J18
HEADER_40P
J18
HEADER_40P
1 13 35 57 79 9
11 1113 1315 1517 1719 1921 2123 2325 2527 2729 2931 3133 3335 3537 3739 39
224466881010121214141616181820202222242426262828303032323434363638384040
C276100nFC276100nF
C277100nFC277100nF
C278
47uF
C278
47uF
R215 0RR215 0R
C279
22uF
C279
22uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MIIA_LXRESET_HPS_GLOBELn
MIIA_RXD0MIIA_RXD1MIIA_RXD2MIIA_RXD3
MIIA_RX_DVMIIA_RX_CLKMIIA_TX_CLK
MII1_TX_EN
MIIA_TXD0MIIA_TXD1MIIA_TXD2MIIA_TXD3
MIIA_MDIOMIIA_MDC
MII1_RXD0MII1_RXD1MII1_RXD2MII1_RXD3
MII1_RX_DVMII1_RX_CLKMII1_TX_CLK
MII1_TXD0MII1_TXD1MII1_TXD2MII1_TXD3
MII_MDIOMII_MDC
MIIA_TRP3MIIA_TRN3
MIIA_LED_LINK
MIIA_LED_ACT
MIIA_XOMIIA_XI
MIIA_LED_10_100MIIA_LED_1000MIIA_LED_ACT
MIIA_LED_LINK
MIIA_LED_ACTMIIA_RXD1MIIA_RXD0
MIIA_RXD3MIIA_LED_1000
MIIA_RX_DV
MIIA_RXD2
MIIA_RX_CLK
MII1_RXD[3:0]
MII1_TXD[3:0]
MII1_RX_CLKMII1_RX_DV
MII1_TX_CLKMII1_TX_EN
MII_INTMII_MDIOMII_MDC
RESET_HPS_GLOBELn
MII_INT
MIIA_TRN2MIIA_TRP2
MIIA_TRN1MIIA_TRP1
MIIA_TRN0MIIA_TRP0
3.3V_VDD
3.3V_AVDD_MII
MIID_1.1V
MIIA_1.1V
3.3V_VDD
MIID_2.5V
MIID_2.5V
MIID_2.5V
MIID_2.5V
3.3V_VDD
3.3V_VDD
3.3V_VDD 3.3V_AVDD_MII MIID_1.1V MIIA_1.1V
MIID_2.5V
GND_SHIELDS
MIID_2.5V
MII1_RXD[3:0]
MII1_TXD[3:0]
MII1_RX_CLKMII1_RX_DV
MII1_TX_CLKMII1_TX_EN
MII_INTMII_MDIOMII_MDC
RESET_HPS_GLOBELn
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
21-HPS Gig Ethernet
B
21 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
21-HPS Gig Ethernet
B
21 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
21-HPS Gig Ethernet
B
21 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
21-HPS Gig Ethernet
Place TX Term Resistor Near MAC
Place RX Term Resistor Near PHY
R241 10KR241 10K
J14
RJ45
J14
RJ45
TD1+1TD1-2TD2+3TD2-4
RD1+7RD1-8RD2+9RD2-10
GRLA11GRLC12
YELC13YELA14
TCT 5RCT 6
GND1 15GND2 16
H1 17H2 18
R226 33R226 33
C286100nFC286100nF
R220 33R220 33
R2344.7K R2344.7K
C296100nFC296100nF
R236 33R236 33
C289
10uF
C289
10uF
R229 33R229 33
R248 NC0402R248 NC0402
R222 NC0402R222 NC0402
Q2SI2301Q2SI2301
C287100nFC287100nF
R245 10KR245 10K
R223 33R223 33
R237 33R237 33
C290100nFC290100nF
R24910KR24910K
R219 33R219 33
R230 33R230 33
R228 NC0402R228 NC0402
C282
10uF
C282
10uFR246 10KR246 10K
R239 0RR239 0R
C291
NC0603
C291
NC0603
R2384.7K R2384.7K
C288100nFC288100nF
R232 33R232 33
C283100nFC283100nF
FB39
600R,FB
FB39
600R,FB
U19
AR8035
U19
AR8035
RESTn1
VDD333AVDD3314
LX2
DVDDL38
AVDDL211 AVDDL16
RXD226
AVDDL317
RXD325
RX_DV30RX_CLK31GTX_CLK33
RXD128 RXD029
TX_EN32
TXD034TXD135TXD236TXD337
TRXP0 9TRXN0 10
TRXP1 12TRXN1 13
TRXP2 15TRXN2 16
TRXP3 18TRXN3 19
XTLO 4XTLI 5
RBIAS 7CLK_25M 23
LED_10_100 24LED_1000 22LED_ACT 21
VDDH_REG 8VDDIO_REG 27
INT20 MDC40 MDIO39
GND_PAD 41
R227 33R227 33
FB40
180R,FB
FB40
180R,FB
R225 2.37KR225 2.37K
R221 33R221 33
C295
1uF
C295
1uF
R243 10KR243 10K
C292100nFC292100nF
C284
1uF
C284
1uF
C29422pFC29422pF
X1025MHzX1025MHz1
2
3
4
R216 0RR216 0RR217 1KR217 1K
C29322pFC29322pF
R224 33R224 33
Q1SI2301Q1SI2301
R247 10KR247 10K
R242 10KR242 10K
R244 10KR244 10K
R2334.7K R2334.7K
R218 1KR218 1K
R231 33R231 33
C285100nFC285100nF
R240 10KR240 10K
L17 4.7uHL17 4.7uH1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MMC_DAT0MMC_DAT1MMC_DAT2MMC_DAT3
MMC_CMDMMC_CLK
MMC_DAT4MMC_DAT3eMMC_VCCI
eMMC_RSTn
MMC_DAT7MMC_DAT6MMC_DAT5MMC_DAT4
MMC_CD
MMC_DAT2MMC_DAT3MMC_CMD
MMC_CLK
MMC_DAT0MMC_DAT1MMC_CD
MMC_CLKMMC_CMD
MMC_CD
eMMC_RSTn
MMC_DAT[7:0]
3.3V_VDD
3.3V_eMMC
3.3V_eMMC3.3V_VDD
3.3V_VDD3.3V_VDD
3.3V_eMMC
MMC_CMD
MMC_DAT[7:0]
MMC_CLK
eMMC_RSTn
MMC_CD
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
HPS eMMC/TF_Card
B
22 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
HPS eMMC/TF_Card
B
22 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
HPS eMMC/TF_Card
B
22 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
22-HPS eMMC/TF_Card
R293 10KR293 10K
D26 TVSD26 TVS
R297 10KR297 10K
R307 33R307 33
R254 10KR254 10K
Q8BSS138Q8BSS138
U20NCEMBM11-04GU20NCEMBM11-04G
DAT0H3DAT1H4DAT2H5DAT3J2DAT4J3DAT5J4DAT6J5DAT7J6
RSTnU5CMDW5CLKW6
NC16H2NC18J1NC27K1NC72AA2
VDDIK2
VDDF1M6VDDF2N5VDDF3T10VDDF4U9
VDD1AA3VDD2Y4VDD3K6VDD4AA5VDD5W4
VSS1P5VSS2K4VSS3M7VSS4R10VSS5Y2VSS6Y5VSS7AA4VSS8AA6VSS9U8
NC1 D14NC2 D1NC3 B13NC4 B2NC5 A11NC6 A9NC7 A6NC8 A4NC9 H14
NC10 H13NC11 H12NC12 H11NC13 H10NC14 H9NC15 H8
NC17 H1
NC19 J7NC20 J8NC21 J9NC22 J10NC23 J11NC24 J12NC25 J13NC26 J14
NC28 K3NC29 K7NC30 K8NC31 K9NC32 K10NC33 K11NC34 K12NC35 K13NC36 K14NC37 L4NC38 L3NC39 L2NC40 L1NC41 L12NC42 L13NC43 L14NC44 M1NC45 M2NC46 M3NC47 M12NC48 M13NC49 M14NC50 N3NC51 N2NC52 N1NC53 P2NC54 P1NC55 P12NC56 P13NC57 P14
NC
58R
3N
C59
R2
NC
60R
1N
C61
R14
NC
62R
13N
C63
R12
NC
64T3
NC
65T2
NC
66T1
NC
67A
A14
NC
68A
A13
NC
69A
A12
NC
70A
A11
NC
71A
A8
NC
73A
A1
NC
74Y
14N
C75
Y13
NC
76Y
12N
C77
Y11
NC
78Y
10N
C79
Y9
NC
80Y
8N
C81
Y7
NC
82Y
6N
C83
Y3
NC
84Y
1N
C85
W14
NC
86W
13N
C87
W12
NC
88W
11N
C89
W10
NC
90W
9N
C91
W8
NC
92W
7N
C93
W3
NC
94W
2N
C95
W1
NC
96V
14N
C97
V13
NC
98V
12N
C99
V3
NC
100
V2
NC
101
V1
NC
102
U12
NC
103
U13
NC
104
U14
NC
105
U1
NC
106
U2
NC
107
U3
NC
108
T12
NC
109
T13
NC
110
T14
RFU1U6RFU2U7RFU3U10RFU4AA7RFU5AA10RFU7R5RFU8P3RFU9P10RFU10N10RFU11M8RFU12M9RFU13M10RFU14M5RFU15H6RFU16H7RFU17K5
NC
111
N12
NC
112
N13
NC
113
N14
NC
114
AH
11N
C11
5T5
NC
116
AE
1N
C11
7A
E14
NC
118
AA
9N
C11
9A
G2
NC
120
AG
13N
C12
1A
H4
NC
122
AH
6N
C12
3A
H9
D19 TVSD19 TVS
R291 10KR291 10K
D23 TVSD23 TVS
R256 10KR256 10K
R294 10KR294 10K
C301100nFC301100nF
C298100nFC298100nF
C299100nFC299100nF
C300100nFC300100nF
C297
2.2uF
C297
2.2uF
Q15SI2301
Q15SI2301
R306 33R306 33
R295 10KR295 10K
R399
10K
R399
10K
R586 NC0805R586 NC0805
D21 TVSD21 TVS
R260 10KR260 10K
D24 TVSD24 TVS
R255 10KR255 10K
Q7SI2301
Q7SI2301
R299 33R299 33R300 33R300 33
TF1
MicroSD Card Connector
TF1
MicroSD Card Connector
DAT21CD/DAT32CMD3VDD4CLOCK5VSS6DAT07DAT18CD9
GND 10GND1 11GND2 12GND3 13
TBD1 14TBD2 15
R308 0RR308 0R
R302 33R302 33
D22 TVSD22 TVS
R304 33R304 33
R292 10KR292 10KC337
10uF
C337
10uF
D25 TVSD25 TVS
C302
2.2uF
C302
2.2uF
R257 10KR257 10K
R296 10KR296 10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB1HS_D0USB1HS_D1USB1HS_D2USB1HS_D3USB1HS_D4USB1HS_D5USB1HS_D6USB1HS_D7
USB1HS_NXTUSB1HS_DIRUSB1HS_STPUSB_PHY_XI
USB1HS_CLK
USB_PHY_XO
USB1HS_D[7:0]
RESET_HPS_GLOBELn
RESET_HPS_GLOBELnDN3DP3
DN4DP4
VBUS1_CN
VBUS2_CN
VBUS3_CN
VBUS4_CN
VBUS1
VBUS2 VBUS2_CN
VBUS3_CN
VBUS1_CN
VBUS4
VBUS3
VBUS4_CN
DN1DP1
DP2DN2
USB1HS_D[7:0]
USB1HS_NXTUSB1HS_DIRUSB1HS_STP
USB1HS_CLK
RESET_HPS_GLOBELnHUB_USB_DPHUB_USB_DM
HUB_USB_DMHUB_USB_DP
3.3V_VDD
3.3V_VDD
3.3V_VDD
1.8V_VDD
3.3V_VDD
3.3V_VDD 1.8V_VDD
3.3V_VDD
3.3V_VDD
GND_SHIELDS
GND_SHIELDS
5V_VDD
5V_VDD
USB1HS_D[7:0]
USB1HS_STP
USB1HS_NXTUSB1HS_DIR
USB1HS_CLK
RESET_HPS_GLOBELn
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
23-HPS USB PHY/HUB
B
23 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
23-HPS USB PHY/HUB
B
23 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
23-HPS USB PHY/HUB
B
23 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
23-HPS USB PHY/HUBNear U21
Near U21
Near U22
FB48180R,FB FB48180R,FB
C318100nFC318100nF
R574 NC0402R574 NC0402
C330
47uF
C330
47uF
R570 NC0402R570 NC0402
D9TVSD9TVS
C324
1uF
C324
1uF
U57
TPS2080
U57
TPS2080
GND1
IN12IN23
EN14 EN2 5OUT2 6OUT1 7
OC# 8 T140T140
R277 10KR277 10K
R573 NC0402R573 NC0402
D12TVSD12TVS
CON1
USB-Ax2
CON1
USB-Ax2
VBUSA1DA-2DA+3GNDA4
VBUSB5DB-6DB+7GNDB8
SHELD1 9SHELD2 10SHELD3 11SHELD4 12
C3075pFC3075pF
C314
10uF
C314
10uF
C321
1uF
C321
1uF
C332
47uF
C332
47uF
R572 NC0402R572 NC0402
C309100nFC309100nF
R283 1MR283 1M
C310100nFC310100nF
R575 NC0402R575 NC0402
C322100nFC322100nF
F4FUSE 0.5A F4FUSE 0.5A
C312100nFC312100nF
C3045pFC3045pF
T142T142
R262 1MR262 1M
R275 10KR275 10K
C319100nFC319100nF
R571 NC0402R571 NC0402
D13TVSD13TVS
D7TVSD7TVS
FB46180R,FB FB46180R,FB
CON2
USB-Ax2
CON2
USB-Ax2
VBUSA1DA-2DA+3GNDA4
VBUSB5DB-6DB+7GNDB8
SHELD1 9SHELD2 10SHELD3 11SHELD4 12
T139T139
F1FUSE 0.5A F1FUSE 0.5A
C305100nFC305100nF
FB45180R,FB FB45180R,FB
R569 1KR569 1K
R269 10KR269 10K
C32722pFC32722pF
C329
47uF
C329
47uF
D14TVSD14TVS
C32822pFC32822pF
D8TVSD8TVS
C311
10uF
C311
10uF
C316100nFC316100nF
R279
12K
R279
12K
R265
8.06K
R265
8.06K
X1124MHz
X1124MHz1
2
3
4
T141T141
C320100nFC320100nF
F3FUSE 0.5A F3FUSE 0.5A
C313100nFC313100nF
C331
47uF
C331
47uF
C323100nFC323100nF
C325100nFC325100nF
R263 10KR263 10KR264 0RR264 0R
FB49180R,FB FB49180R,FB
U21
USB3320C
U21
USB3320C
DAT03DAT14DAT25DAT36DAT47DAT59DAT610DAT713
NXT2DIR31STP29REFCLK26
CLKOUT1
XO25
RESET27
RBIAS24
GND 33
VBAT 21
REFSEL1 11
NC 12
REFSEL0 8
REFSEL2 14
SPK_L15SPK_R16
VDD18_1 28
DP 18DM 19
VDD33 20
VDD18_2 30
VBUS 22
ID 23
VDDIO 32
CPEN 17
C303
4.7uF
C303
4.7uF
R568 0RR568 0R
R274 10KR274 10K
C315100nFC315100nF
C317100nFC317100nF
R273 0RR273 0R
D10TVSD10TVS
C306
10uF
C306
10uF
X1224MHz
X1224MHz
1
2
3
4
U22
USB2514i
U22
USB2514i
DN1 1DP1 2
DN2 3DP2 4
VDD33_15
NC/DN3 6NC/DP3 7
NC/DN4 8NC/DP4 9
VDD33_210 TEST 11
PRTPWR1/BC_EN1 12
OCS1n 13
CRFILT14
VDD33_315
PRTPWR2/BC_EN2 16
OCS2n 17
NC/PRTPWR3/BC_EN3 18
OCS3n 19
NC/PRTPWR4/BC_EN4 20
OCS4n 21
SDA/SMBDTA/NON_REM122
VDD33_423
SCL/SMBCLK/CFG_SEL024HS_IND/CFG_SEL125
RESETn26
VBUS_DET27
SUSP_IND/L_PWR/NON_REM028
VDD33_529
DM_UP30DP_UP31
XTALOUT32
XTALIN/CLKIN33
PLLFILT34
RBIAS 35
VDD33_636
VSS_PAD 37
F2FUSE 0.5A F2FUSE 0.5A
C326100nFC326100nF
R276 10KR276 10K
D11TVSD11TVS
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HPS_UART0_RXHPS_GPIO9HPS_I2C0_SDAHPS_UART1_RX
HPS_GPIO49HPS_GPIO50HPS_GPIO53HPS_GPIO54HPS_GPIO44HPS_GPIO62
HPS_UART0_TX
HPS_UART1_TX
HPS_GPIO0HPS_I2C0_SCL
QSPI_IO0QSPI_IO1QSPI_IO2QSPI_IO3QSPI_SS0QSPI_CLK
HPS_I2C1_SCLHPS_SPIM0_MOSIHPS_SPIM0_CLKHPS_SPIM0_CS0n
HPS_I2C1_SDAHPS_SPIM0_MISOHPS_GPIO61
HPS_GPIO9
HPS_GPIO49HPS_GPIO50
HPS_GPIO61
HPS_SPIM0_CS0n
HPS_SPIM0_MOSI
HPS_SPIM0_CLK
HPS_SPIM0_MISO
QSPI_IO[3:0]
QSPI_SS0QSPI_CLK
HPS_I2C0_SCLHPS_I2C0_SDAHPS_I2C1_SCLHPS_I2C1_SDA
HPS_UART0_RX
HPS_UART1_RXHPS_UART1_TX
HPS_UART0_TX
HPS_GPIO0
HPS_GPIO53HPS_GPIO54
HPS_GPIO44
HPS_GPIO62
5V_EXP3
5V_VDD 5V_EXP33.3V_EXP3
3.3V_VDD 3.3V_EXP3
HPS_SPIM0_MOSIHPS_SPIM0_MISO
QSPI_IO[3:0]
QSPI_SS0QSPI_CLK
HPS_SPIM0_CS0nHPS_SPIM0_CLK
HPS_I2C0_SCLHPS_I2C0_SDAHPS_I2C1_SCLHPS_I2C1_SDA
HPS_UART0_RXHPS_UART0_TXHPS_UART1_RXHPS_UART1_TX
HPS_GPIO9HPS_GPIO0
HPS_GPIO44
HPS_GPIO49HPS_GPIO50HPS_GPIO53HPS_GPIO54HPS_GPIO61HPS_GPIO62
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
24-HPS Extend IF
B
24 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
24-HPS Extend IF
B
24 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
24-HPS Extend IF
B
24 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
24-HPS Extend IF
C335100nFC335100nF
C334
22uF
C334
22uF
FB51
180R,FB
FB51
180R,FB
FB50
180R,FB
FB50
180R,FB
J21
HEADER_40P
J21
HEADER_40P
1 13 35 57 79 9
11 1113 1315 1517 1719 1921 2123 2325 2527 2729 2931 3133 3335 3537 3739 39
224466881010121214141616181820202222242426262828303032323434363638384040
C336
22uF
C336
22uF
C333100nFC333100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FX2_D_NFX2_D_P
VBUS_5V
FX2_WAKEUP
24M_XTALOUT24M_XTALINUSB_CLK
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PD0FX2_PD1FX2_PD2FX2_PD3
FX2_PD4FX2_PD5FX2_PD6FX2_PD7
FX2_RESETn
FX2_WAKEUP
FX2_FLAGAFX2_FLAGBFX2_FLAGC
FX2_SLRDnFX2_SLWRn
FX2_SDAFX2_SCL
FX2_PA2FX2_FLAGCFX2_PA7FX2_FLAGAFX2_PA3FX2_PA4EXTRA_SIG0FX2_PB4FX2_PA6FX2_PB2FX2_FLAGBFX2_PB0FX2_PA1FX2_PB5USB_DISABLEnFX2_PB6
JTAG_TXJTAG_RXFACTORY_REQUESTUSB_CFG5USB_RESETnUSB_OEnUSB_RDnUSB_WRnFACTORY_STATUSSC_RXSC_TXUSB_CFG4EXTRA_SIG1USB_CFG6USB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4
FX2_PB1FX2_PB3FX2_SCLFX2_PD6FX2_PD4
FX2_SLWRnFX2_SLRDnFX2_PD7FX2_PD5FX2_PA5
USB_CFG3M570_PCIE_JTAG_EN
USB_DATA7USB_DATA5USB_DATA6RSTUSB_CFG8TRSTUSB_FULLUSB_EMPTYUSB_CFG11USB_SCLUSB_SDAEXTRA_SIG2USB_CFG10USB_CFG0USB_CFG1USB_CFG2USB_CFG9
FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_RESETn
USB_CLKFX2_PB7
USB_CFG7M570_CLOCK
MAX_SDA
C_USB_MAX_TDIC_USB_MAX_TCKC_USB_MAX_TMSC_USB_MAX_TDO
FX2_SDA
C_USB_MAX_TCKC_USB_MAX_TDIC_USB_MAX_TDOC_USB_MAX_TMS
JTAG_BLASTER_TDOJTAG_BLASTER_TMSJTAG_BLASTER_TDIJTAG_BLASTER_TCK
SC_TX
SC_RX
JTAG_TX
JTAG_RX
C_USB_MAX_TDO
C_USB_MAX_TDI
C_USB_MAX_TCK
C_USB_MAX_TMS
USB_SCLUSB_SDAUSB_FULLUSB_EMPTY
FACTORY_REQUEST
USB_DATA[7:0]
USB_FULLUSB_EMPTYUSB_SCLUSB_SDA
USB_RESETnUSB_OEnUSB_RDnUSB_WRn JTAG_BLASTER_TDO
JTAG_BLASTER_TMSJTAG_BLASTER_TDIJTAG_BLASTER_TCKUSB_DISABLEn
3.3V_Blaster
3.3V_Blaster
3.3V_Blaster
1.8V_Blaster
1.8V_Blaster
3.3V_Blaster
1.5V_Blaster3.3V_Blaster
1.5V_Blaster3.3V_Blaster3.3V_Blaster
1.5V_Blaster
3.3V_VDD
1.8V_VDD 1.8V_Blaster
1.5V_VDD3.3V_Blaster
GND_SHIELDS
USB_RESETnUSB_OEnUSB_RDnUSB_WRn
USB_DATA[7:0]
USB_FULLUSB_EMPTYUSB_SCLUSB_SDA
JTAG_BLASTER_TDOJTAG_BLASTER_TMS
JTAG_BLASTER_TCKJTAG_BLASTER_TDI
USB_DISABLEn
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
25-On-Board USB Blaster II
B
25 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
25-On-Board USB Blaster II
B
25 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
25-On-Board USB Blaster II
B
25 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
CycloneV USB Interface
JTAG Interface (From MAX II)
JTAG Interface (For MAX II)
25-On-Board USB Blaster II
R474 56R474 56
C739100nFC739100nF
C743100nFC743100nF
R454 0RR454 0R
R471 1KR471 1K
T104T104
MAX IIBANK 1
U55B
EPM570GF100
MAX IIBANK 1
U55B
EPM570GF100
IO_B1_B1B1IO_B1_C1C1IO_B1_C2C2IO_B1_D1D1IO_B1_D2D2IO_B1_D3D3IO_B1_E3E3IO_B1_F1F1IO_B1_F2F2IO_B1_F3F3IO_B1_G1G1IO_B1_G2G2IO_B1_G3G3IO_B1_H1H1IO_B1_H4H4IO_B1_H7H7
IO_B1_H8 H8IO_B1_J3 J3IO_B1_J4 J4IO_B1_J5 J5IO_B1_J6 J6IO_B1_J8 J8IO_B1_J9 J9IO_B1_K1 K1
IO_B1_K10 K10
IO_B1_K2 K2IO_B1_K3 K3IO_B1_K4 K4IO_B1_K5 K5IO_B1_K6 K6IO_B1_K7 K7IO_B1_K8 K8
FB79
600R,FB
FB79
600R,FB
R455 NC0402R455 NC0402 U38
CY7C68013A
U38
CY7C68013A
RDY0 A1RDY1 B1XTALINC1
AVCC1D1
DMINUSE1
AGND1F1
VCC1G1
GND1H1
PD7 A2
CLKOUT B2XTALOUTC2
AVCC2D2
DPLUSE2
AGND2F2
IFCLKG2
RESERVEDH2
PD5 A3PD4 B3
PD6 C3
SCL F3SDA G3
PB0 H3
GND2A4GND3B4GND4C4
PB1 F4
PB3 G4PB2 H4
VCC2A5VCC3B5
PB6 F5PB5 G5PB4 H5
PD3 A6PD2 B6
PA7C6
PA4F6
PA1G6
PB7 H6
PD1 A7
WAKEUP B7
PA6C7
GND5D7
VCC5E7
PA3F7
CTL1 G7CTL0 H7
PD0 A8
RESET B8
PA5C8
GND6D8
VCC6E8
PA2F8
PA0G8
CTL2 H8
VCC4C5
C740100nFC740100nF
T146T146
R458 4.7KR458 4.7K
R459 0RR459 0R
FB78
600R,FB
FB78
600R,FB
T101T101
C746100nFC746100nF
T147T147
C741100nFC741100nF
MAX IIBANK2
U55C
EPM570GF100
MAX IIBANK2
U55C
EPM570GF100
IO_B2_A1A1
IO_B2_A10A10
IO_B2_A2A2IO_B2_A3A3IO_B2_A4A4
IO_B2_A5 A5
IO_B2_A6 A6
IO_B2_A7A7
IO_B2_A8 A8
IO_B2_A9A9
IO_B2_B10 B10
IO_B2_B2B2IO_B2_B3B3IO_B2_B4B4IO_B2_B5B5
IO_B2_B6 B6
IO_B2_B7B7
IO_B2_B8B8
IO_B2_B9B9
IO_B2_C10 C10
IO_B2_C3 C3IO_B2_C4 C4
IO_B2_C7C7
IO_B2_C8C8 IO_B2_C9C9
IO_B2_D10D10
IO_B2_D8 D8IO_B2_D9D9 IO_B2_E8 E8
IO_B2_E9 E9
IO_B2_F10 F10IO_B2_F9 F9
IO_B2_G10 G10
IO_B2_G8 G8IO_B2_G9 G9
IO_B2_H10 H10IO_B2_H9 H9
IO_B2_J10 J10R460 0RR460 0R
T119T119
T143T143
T116T116
T148T148
MAX IICONFIGURATION
U55D
EPM570GF100
MAX IICONFIGURATION
U55D
EPM570GF100
IO2/GCLK2p F8IO2/GCLK3p E10
IO1/DEV_CLRn K9IO1/DEV_OEJ7
IO1/GCLK0p E2IO1/GCLK1p E1TCKH3 TDIH2
TMSJ1TDOJ2
R469 1KR469 1K
FB77
180R,FB
FB77
180R,FB
D51TVSD51TVS
T149T149
T105T105
C73112pFC73112pF
T145T145
T103T103
R461 0RR461 0R
X1324MHzX1324MHz
1
2
3
4
R478 1KR478 1K
C73212pFC73212pF
D50TVSD50TVS
C747100nFC747100nF
C733100nFC733100nF
C735100nFC735100nF
C744100nFC744100nF
R464
20K
R464
20K
D52
Green
D52
GreenD53
Green
D53
Green
R467 1KR467 1K
R456 100KR456 100K
R475 1KR475 1K
J22
HEADER 5x2 SMD
J22
HEADER 5x2 SMD
1 23 45 67 89 10
R462 0RR462 0R
T121T121
T118T118
T134T134
C736100nFC736100nF
MAX IIPOWER
U55A
EPM570GF100
MAX IIPOWER
U55A
EPM570GF100
GNDINTC5
GNDINTF5 GNDINTE6
GNDIOD5
GNDIOG7
GNDIOD7
GNDIOG5 GNDIOF6 GNDIOE5
GNDINTH5
VCCINT C6VCCINT E7
VCCINT H6VCCINT F4
VCCIO2 F7VCCIO2 D6VCCIO2 D4
VCCIO1 E4VCCIO1 G4VCCIO1 G6
D54
Green
D54
Green
R466 56R466 56
R477 1KR477 1K
U36
MAX811
U36
MAX811
GND1
RESET#2VCC 4
MR# 3
T150T150
R476 56R476 56
CON3USB MINI-BCON3USB MINI-B
VB 1D- 2D+ 3ID 4
G1 5
G3
6G
27
G5
8G
49
G810
G611 G712
R457 4.7KR457 4.7K
D55
Green
D55
Green
C737100nFC737100nF
R463 10KR463 10K
R473 1KR473 1K
C742100nFC742100nF
C734100nFC734100nF
C745100nFC745100nF
R479 56R479 56
C738100nFC738100nF
T102T102
C730100nFC730100nF
T120T120
T117T117
T106T106
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HPS_UART0_RX
HPS_UART0_TX
RESET_HPS_GLOBELn
HPS_RESETn
RTC_RESETn
PB_COLD_RESETn
PB_WARM_RESETn
HPS_WARM_RSTn
USER_HPS_LED2
USER_HPS_LED3
USER_FPGA_LED2
USER_FPGA_LED3
USER_FPGA_LED0
USER_FPGA_LED1
PCIE_LED_X1
PCIE_LED_X4
USER_HPS_LED0
USER_HPS_LED1
USER_FPGA_PB0
USER_HPS_PB0
USER_HPS_PB3
USER_HPS_PB2
USER_HPS_PB1
USER_FPGA_DIPSW0USER_FPGA_DIPSW1USER_FPGA_DIPSW2USER_FPGA_DIPSW3
RTC_RESETn
HPS_I2C0_SCLHPS_I2C0_SDA
RTC_INTn
USER_FPGA_PB0
USER_HPS_PB[3:0]
RTC_INTn
HPS_RESETn
HPS_WARM_RSTn
USER_FPGA_DIPSW0USER_FPGA_DIPSW1USER_FPGA_DIPSW2USER_FPGA_DIPSW3
PCIE_LED_X1PCIE_LED_X4
USER_FPGA_LED0USER_FPGA_LED1USER_FPGA_LED2USER_FPGA_LED3
RESET_HPS_GLOBELnRTC_RESETn
HPS_UART0_RXHPS_UART0_TX
USER_HPS_LED2USER_HPS_LED3
USER_HPS_LED0USER_HPS_LED1
HPS_GPIO53HPS_GPIO54HPS_GPIO49HPS_GPIO62
HPS_I2C0_SCLHPS_I2C0_SDA
VBAT
HPS_UART0_TX
HPS_UART0_RX
3.3V_VDD
3.3V_VDD
3.3V_VDD3.3V_VDD
3.3V_VDD
3.3V_VDD
1.5V_VDD
3.3V_VDD
3.3V_VDD1.5V_VDD
VBAT
3.3V_VDD 3.3V_VDD
USER_FPGA_PB0
USER_HPS_PB[3:0]
RTC_INTn
HPS_RESETn
HPS_WARM_RSTn
USER_FPGA_DIPSW0USER_FPGA_DIPSW1USER_FPGA_DIPSW2USER_FPGA_DIPSW3
PCIE_LED_X1PCIE_LED_X4
USER_FPGA_LED0USER_FPGA_LED1USER_FPGA_LED2USER_FPGA_LED3
RESET_HPS_GLOBELnRTC_RESETn
HPS_UART0_RXHPS_UART0_TX
HPS_GPIO53HPS_GPIO54HPS_GPIO49HPS_GPIO62
HPS_I2C0_SCLHPS_I2C0_SDA
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
26-MISC Led/Button/RTC/Reset
B
26 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
26-MISC Led/Button/RTC/Reset
B
26 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
26-MISC Led/Button/RTC/Reset
B
26 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
26-MISC Led/Button/RTC/Reset
J25: Left to Right 3.3V, TX, RX, GND, GND J24: Left to Right 3.3V, TX, RX, GND
R321 4.7KR321 4.7K
T75T75
S4
Switch
S4
Switch
1 23 4
R322 4.7KR322 4.7K
S8
DIP Switch 4Pairs
S8
DIP Switch 4Pairs
1234 5
678
R290 4.7KR290 4.7K
D15Green
D15Green
D16Green
D16Green
D30Green
D30Green
Q3BSS138Q3BSS138
S2
Switch
S2
Switch
1 23 4
R315 4.7KR315 4.7K
R31110KR31110K
C340100nFC340100nF
D20TVSD20TVS
R324 4.7KR324 4.7K
R323 4.7KR323 4.7K
R318 4.7KR318 4.7K
S1
Switch
S1
Switch
1 23 4
D35Green
D35Green
R309
10K
R309
10K
BT1BatteryBT1Battery
VC
C1
GN
D2
R326 4.7KR326 4.7K
R316 4.7KR316 4.7K
R319 4.7KR319 4.7K
R329 4.7KR329 4.7K
J25
CN 5x1 2.00MM
J25
CN 5x1 2.00MM
1
2
3
4
5
D36Green
D36Green
R28449.9 R28449.9
D33Green
D33Green
D18TVSD18TVS
R313 0RR313 0R
R28549.9 R28549.9
U23
DS3231SN
U23
DS3231SN
32K1VCC2SQW/INT#3RST#4NC65NC76NC87NC98 NC10 9NC4 10NC3 11NC2 12GND 13VBAT 14SDA 15SCL 16
R305 100R305 100
JP5JP5
S3
Switch
S3
Switch
1 23 4
R330 4.7KR330 4.7K
C339
10uF
C339
10uF
R298
1K
R298
1K
R28649.9 R28649.9
R328 4.7KR328 4.7K
R314 0RR314 0R
D34Green
D34Green
R301 100R301 100
R28749.9 R28749.9
R310 4.7KR310 4.7K
D31Green
D31Green
J24
PIN 4x1 DIP
J24
PIN 4x1 DIP
1
2
3
4
R317 4.7KR317 4.7K
R331 4.7KR331 4.7K
S5
Switch
S5
Switch
1 23 4
R332 4.7KR332 4.7K
R325 4.7KR325 4.7K
D17TVSD17TVS
R288 4.7KR288 4.7K
D27Green
D27Green
D32Green
D32Green
R333 4.7KR333 4.7K
R320 4.7KR320 4.7K
R312
10K
R312
10K
D29Green
D29Green
R327 4.7KR327 4.7K
R303 100R303 100
S6
Switch
S6
Switch
1 23 4
D28Green
D28Green
C338
10uF
C338
10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5V_SHDNn
12V_SHDNn
INTVCC_1
INTVCC_1
FAN_CTRL
3.3V_POWER_EN
5V_SHDNn
2.5V_POWER_EN
12V_SHDNn1.8V_POWER_EN1.1V_POWER_EN1.5V_POWER_ENVTT_POWER_EN
3.3V_POWER_EN2.5V_POWER_EN
VTT_POWER_EN
1.8V_POWER_EN1.1V_POWER_EN1.5V_POWER_EN
INTVCC_1
DC_IN
5V_VCC 5V_VDD
12V_VDD
DC_IN
DC_IN
DC_IN
12V_VCC
12V_ATX
12V_VCC
5V_VCC
GND_SHIELDS
INTVCC_1
INTVCC_1
12V_VCC
FAN_CTRL
3.3V_POWER_EN2.5V_POWER_EN1.8V_POWER_EN1.1V_POWER_EN1.5V_POWER_ENVTT_POWER_EN
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
27-Power In/5V/12V
B
27 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
27-Power In/5V/12V
B
27 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
27-Power In/5V/12V
B
27 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
27-Power In/5V/12V
T109T109
C751
22uF
C751
22uF
C852220nFC852220nF
L31 3.3uHL31 3.3uH12
D58 B360AD58 B360A
R559 0RR559 0R
D64
Red
D64
Red
C7591nFC7591nF
C76922pFC76922pF
R498 11.3KR498 11.3K
L32
0.68uH
L32
0.68uH
12
S10
DIP Switch 4Pairs
S10
DIP Switch 4Pairs
1234 5
678
C765
22uF
C765
22uF
T111T111
C749
22uF
C749
22uF
C748
220uF
C748
220uF
C762100pFC762100pF
R502
4.7K
R502
4.7K
D63GreenD63Green
C774
4.7uF
C774
4.7uF
D62BAT165D62BAT165
R482 1KR482 1K
C750
22uF
C750
22uF
C770
10nF
C770
10nF
D59 B360AD59 B360A
R496
52.3K
R496
52.3K
Q10
SI7114ADN
Q10
SI7114ADN
123
4 56789
D60BAT165D60BAT165
C753
4.7uF
C753
4.7uF
C772
4.7uF
C772
4.7uF
Q11
SI7114ADN
Q11
SI7114ADN
123
4 56789
D56 B360AD56 B360A
R487 20KR487 20K
gnd-pad
U39
LTC3855EUH-1
gnd-pad
U39
LTC3855EUH-1
TK/SS11 ITH12 VFB1 3
SGND14
VFB2 5
ITH26TK/SS27
SENSE2+ 8SENSE2- 9
PGOOD2 17
NC18
PGOOD1 16
TG2 20
BOOST2 21PGND222
BG2 23
EXTVCC24 INTVCC25
PGND128
SW2 19
DIFFP10DIFFN11DIFFOUT12
RUN213
ILIM114
ILIM215
VIN26
BG1 27
BOOST1 29TG1 30
SW1 31
CLKOUT32 PHSASMD33 MODE/PLLIN34 FREQ35
ITEMP236
ITEMP137 RUN138
SENSE1+ 39SENSE1- 40
SGND241
R507 0RR507 0R
C756
47uF
C756
47uF
C757100nFC757100nF
R488 8.2KR488 8.2K
J23
ATX-POWER
J23
ATX-POWER
COM1
COM2
+12V 3
+12V 4D61 B360AD61 B360A
Q13
SI7114ADN
Q13
SI7114ADN
123
4 56789
C754 100nFC754 100nF
R484 NC0402R484 NC0402
T108T108
R485 NC0402R485 NC0402
T107T107
R505 4.7KR505 4.7K
C768
22uF
C768
22uF
C760
22uF
C760
22uFQ12
SI7114ADN
Q12
SI7114ADN
123
4 56789
C767
22uF
C767
22uFR494 215KR494 215K
C76382pFC76382pF
R483
10K
R483
10K
R491 20KR491 20K
C7581nFC7581nF
T110T110
Q9BSS138Q9BSS138
D65
Red
D65
Red
R550 0RR550 0R
C76422pFC76422pF
R490 147KR490 147K
T144T144
R489
24K
R489
24K
C761 100nFC761 100nFR495
57.6K
R495
57.6K
S9
DIP Switch 4Pairs
S9
DIP Switch 4Pairs
1234 5
678
Q14
SI7114ADN
Q14
SI7114ADN
123
4 56789
R492 20KR492 20K
C752
22uF
C752
22uF
R497 3.9KR497 3.9KC766
22uF
C766
22uF
R499
0R
R499
0R
D571N4148WD571N4148W
R493169K
R493169K
C755
47uF
C755
47uF
R501 4.7KR501 4.7K
R500
24K
R500
24K
C850
10uF
C850
10uF
F5
FUSE 6A
F5
FUSE 6A
CON4
PWR_JACK 2.54MM
CON4
PWR_JACK 2.54MM
23
1
JP15JP15
C851
2.2uF
C851
2.2uF
C771100nFC771100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.1V_POWER_EN
1.8V_POWER_EN1.8V_POWER_GOOD
EAOUT
1.1V_POWER_GOOD1.8V_POWER_EN1.1V_POWER_EN
5V_VDD 1.1V_VCCP1.1V_VCC
5V_VDD
1.8V_VCCP1.8V_VCC
5V_VDD
5V_VDD
5V_VDD
5V_VDD
1.8V_POWER_EN1.1V_POWER_EN
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
28-Power1.1V/1.8V
B
28 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
28-Power1.1V/1.8V
B
28 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
28-Power1.1V/1.8V
B
28 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
28-Power 1.1V/1.8V
R515232KR515232K
T136T136
C788
22uF
C788
22uF
T138T138
C787
22uF
C787
22uF
R556
180K
R556
180K
R518 10KR518 10K
C786
22uF
C786
22uF
T137T137
U47EN5394QIU47EN5394QI
PVIN134PVIN235PVIN336PVIN437PVIN538PVIN639PVIN740PVIN841PVIN942PVIN1043
PGND11PGND22PGND33PGND44PGND527PGND628PGND729PGND830PGND931PGND1032PGND1133PGND1264PGND1365PGND1466PGND1567PGND1668PGND1769PGND1870
VOUT1 5VOUT2 6VOUT3 7VOUT4 8VOUT5 9VOUT6 10VOUT7 11VOUT8 12VOUT9 13
S-OUT 48S-IN 49M/S 50
EN-PB 51ENABLE 52
AVIN 53POK 54
AGND 55VFB 56
EAOUT 57
OCP_ADJ 58SS 59
S_DELAY 60MARK1 61MARK2 62
VSENSE 63N
C14
14N
C15
15N
C16
16N
C17
17N
C18
18N
C19
19N
C20
20N
C21
21N
C22
22N
C23
23N
C24
24
NC
25(S
W)
25N
C26
(SW
)26
NC
4444
NC
4545
NC
4646
NC
4747
R553 NC0402R553 NC0402
R516232KR516232K
C783
47uF
C783
47uF
R503 10KR503 10K
T127T127
U41
EP53F8QI
U41
EP53F8QI
NC_SW11
PGND12PGND23
AVIN2 4
VFB 5
NC6
VOUT2 7VOUT1 8
AGND 9
AVIN1 10
POK 11ENABLE 12
PVIN113PVIN214
NC_SW215NC_SW316
R517 10KR517 10K
R558
169K
R558
169K
R552 NC0402R552 NC0402
T135T135
C7895pFC7895pF
T125T125
D67
Red
D67
Red
R551 NC0402R551 NC0402
C782
47uF
C782
47uFC832
10uF
C832
10uF
C835
10uF
C835
10uF
R508 0RR508 0R
R506 0RR506 0R
R557 NC0402R557 NC0402
T124T124
C836
2.2uF
C836
2.2uFC790
1uF
C790
1uF
C833
2.2uF
C833
2.2uF
T123T123
T126T126
C837220nFC837220nF
R514232KR514232K
C780
10uF
C780
10uF C834220nFC834220nF
C785 47nFC785 47nF
C82539pFC82539pF
C779
47uF
C779
47uF
T122T122
D66
Red
D66
Red
R504 10KR504 10K
C781
47uF
C781
47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.5V_POWER_GOOD
VTT_POWER_ENVTT_POWER_GOOD
1.5V_POWER_EN
1.5V_POWER_ENVTT_POWER_EN
5V_VDD
5V_VDD
1.5V_VCC 1.5V_VCCP
5V_VDD
1.5V_VDD
3.3V_VDD
3.3V_VDD
0.75_VTT0.75_VTTP
1.5V_POWER_ENVTT_POWER_EN
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
29-Power 1.5V/VTT
B
29 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
29-Power 1.5V/VTT
B
29 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
29-Power 1.5V/VTT
B
29 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
29-Power 1.5V/VTT
C8031nFC8031nF
R519 0RR519 0R
C792
22uF
C792
22uF
C797
22uF
C797
22uF
R521 200KR521 200K
R591
1K
R591
1K
C799
10uF
C799
10uF
C798
22uF
C798
22uF
C796
10uF
C796
10uF
D69
Red
D69
Red
C804
10uF
C804
10uF
U43
EV1320QI
U43
EV1320QI
NC1
AVIN 2
ENABLE 3POK 4
SS5
AGND6
PGND17PGND28
C1N 9C2N 10
VOUT1 11VOUT2 12
C1P 13C2P 14
VDDQ115VDDQ216
C801
22uF
C801
22uF
C800
10uF
C800
10uF
R531 10KR531 10K
C793
22uF
C793
22uFC838
10uF
C838
10uF
D68
Red
D68
Red
U42
EN5339QI
U42
EN5339QI
NC
_SW
11
PGND12PGND23
VOUT0 4VOUT1 5VOUT2 6VOUT3 7
PGND38PGND49
TST210TST111TST012
NC
113
VFB 14AGND15
AVIN16
POK 17ENABLE 18
PVIN119PVIN220
NC
_SW
221
NC
_SW
322
NC
_SW
423
NC
_SW
524
PADGND25
R535 0RR535 0R
C839
2.2uF
C839
2.2uF
C802
10uF
C802
10uF
R523 10KR523 10K
R522 33KR522 33K
C840220nFC840220nF
C795
1uF
C795
1uF
R530 1KR530 1K
R524 10KR524 10K
C79410pFC79410pF
R527 0RR527 0R
C841
10uF
C841
10uF
C842
2.2uF
C842
2.2uF
R520
348K
R520
348K
C843220nFC843220nF
C791
22uF
C791
22uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3.3V_POWER_GOOD3.3V_POWER_EN
2.5V_POWER_EN3.3V_POWER_EN
2.5V_POWER_EN2.5V_POWER_GOOD
2.5V_VCCP5V_VDD
5V_VDD
2.5V_VCC
5V_VDD 3.3V_VCC 3.3V_VCCP
5V_VDD
5V_VDD
2.5V_POWER_EN3.3V_POWER_EN
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
30-Power 2.5V/3.3V
B
30 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
30-Power 2.5V/3.3V
B
30 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
30-Power 2.5V/3.3V
B
30 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
30-Power 3.3V/2.5
T129T129
C817
22uF
C817
22uF
C808
47uF
C808
47uF
C809
22uF
C809
22uF
C8208.2pFC8208.2pF
R541
2K
R541
2K
C844
10uF
C844
10uF
C847
10uF
C847
10uF
R537
5.6K
R537
5.6K
R532 10KR532 10KT132T132
C821
1uF
C821
1uF
C845
2.2uF
C845
2.2uF
R538 10KR538 10K
C848
2.2uF
C848
2.2uF
C811
47uF
C811
47uF
R536
6.8K
R536
6.8K
C80610nFC80610nF
C846220nFC846220nF
C849220nFC849220nF
R547 0RR547 0R
D71
Red
D71
Red
R543
348K
R543
348K
R545 100KR545 100K
C816
22uF
C816
22uF
T128T128
R544 10KR544 10K
C80510nFC80510nF
R540
2K
R540
2K
C807
15nF
C807
15nF
R542 0RR542 0R
R546 10KR546 10K
C818
22uF
C818
22uF
T130T130
C810
47uF
C810
47uF
D70 RedD70 RedR533 10KR533 10K
U45
EN5339QI
U45
EN5339QI
NC
_SW
11
PGND12PGND23
VOUT0 4VOUT1 5VOUT2 6VOUT3 7
PGND38PGND49
TST210TST111TST012
NC
113
VFB 14AGND15
AVIN16
POK 17ENABLE 18
PVIN119PVIN220
NC
_SW
221
NC
_SW
322
NC
_SW
423
NC
_SW
524
PADGND25
C819
22uF
C819
22uF
T131T131
R534
1R
R534
1R
U46EN5366QIU46EN5366QI
PVIN130PVIN231PVIN332PVIN433PVIN534PVIN635
PGND124PGND225PGND326PGND427PGND528PGND629PGND_PAD59
VOUT1 14VOUT2 15VOUT3 16VOUT4 17VOUT5 18VOUT6 19VOUT7 20
AGND40
XOV 44
XFB 43
AVIN39
SS48
POK46ENABLE52
EAIN 49EAOUT 50COMP 51PWM 53
M/S 55
NC22(SW) 22NC21(SW) 21
NC5(SW) 5NC4(SW) 4
NC
4242
NC45 45NC47 47NC54 54NC56 56NC57 57NC58 58
NC
11
NC
22
NC
33
NC
66
NC
77
NC
88
NC
99
NC
1010
NC
1111
NC
1212
NC
1313
NC
3636
NC
3737
NC
2323
NC
4141
ROCP38T133T133
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.1V_VDD
3.3V_VDD
VBAT
2.5V_AUX
2.5V_AVDD
3.3V_VDD
1.5V_VDD
VREF_FPGA_DDR3
1.8V_VDD
3.3V_VDD
1.1V_AVDD
1.1V_VDD
1.5V_VDD
VREF_HPS_DDR3
1.1V_AVDD
2.5V_AVDD
3.3V_VDD
2.5V_VDD
3.3V_VDD
2.5V_AVDD
2.5V_VDD
3.3V_VDD3.3V_VCCP
2.5V_AUX
2.5V_VDD2.5V_VCCP
2.5V_AVDD
1.8V_VDD1.8V_VCCP
1.1V_VDD1.1V_VCCP
1.1V_AVDD
2.5V_VDD
3.3V_VDD
1.5V_VDD
VREF_HPS_DDR3
1.5V_VDD
VREF_FPGA_DDR3
1.5V_VDD1.5V_VCCP
2.5V_VDD
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
31-CV SoC Powers
B
31 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
31-CV SoC Powers
B
31 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
31-CV SoC Powers
B
31 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
31-CV SoC Powers
FB93 180R,FBFB93 180R,FB
FB85 600R,FBFB85 600R,FB
FB71
180R,FB
FB71
180R,FB
R526
1K
R526
1K
FB58 600R,FBFB58 600R,FBFB86 600R,FBFB86 600R,FB
R5291KR5291K
FB62 180R,FBFB62 180R,FB
FB61 600R,FBFB61 600R,FB
FB91 180R,FBFB91 180R,FB
R588 0RR588 0R
FB57 180R,FBFB57 180R,FB
FB73 180R,FBFB73 180R,FB
Cyclone V GX SoC Power
5CSXFC6D_F896
U1K
Cyclone V GX SoC Power
5CSXFC6D_F896
U1K
VCCIO3AAC11VCCIO3AAD8VCCIO3AAF7VCCIO3AAG4
VCCIO3BAB14VCCIO3BAD13VCCIO3BAE15VCCIO3BAJ13
VCCIO3BAK10
VCCIO4AAA17
VCCIO4AAD18VCCIO4AAE25VCCIO4AAF22
VCCIO4AAH16VCCIO4AAH26VCCIO4AAJ23VCCIO4AAK20
VCCIO5A AD28VCCIO5A AG29VCCIO5A W23
VCCIO5B AA27VCCIO5B AE30
VCCIO8A A7
VCCIO8A C11VCCIO8A D8VCCIO8A E5VCCIO8A F12VCCIO8A G14VCCIO8A G9VCCIO8A H6VCCIO8A J13
VREFB3AN0AD6
VREFB3BN0AJ15VCCIO3BAJ8
VCCIO4AAG19
VCCIO5A AB24
VCCIO8A B4
VREFB4AN0AK17
VREFB5AN0 AC24
VREFB5BN0 AA29
VREFB8AN0 B10
VCCIO4AAC21
FB88
600R,FB
FB88
600R,FBFB89
600R,FB
FB89
600R,FB
FB83 180R,FBFB83 180R,FB
Cyclone V GX SoC Power
5CSXFC6D_F896
U1J
Cyclone V GX SoC Power
5CSXFC6D_F896
U1J
VCCM11VCCM13VCCM9VCCN10VCCN12VCCN14VCCP11VCCP13VCCR10VCCR12VCCR14VCCT11VCCT13VCCU10
VCCPD3A AC10VCCPD3A AA10
VCCPD3B4A AC19VCCPD3B4A AC17VCCPD3B4A AC15VCCPD3B4A AC13VCCPD3B4A AB20VCCPD3B4A AB18
VCCPD3B4A AE21VCCPD3B4A AD16
VCCPD5A V24VCCPD5A V22
VCCA_FPLL AA8VCCA_FPLL V8VCCA_FPLL R7VCCA_FPLL N7
VCCA_FPLL K9VCCA_FPLL Y22
DNU5E26 DNU4AD15
VCCU21 VCCY9 VCCY13 VCCY11 VCCW14 VCCW12 VCCW10 VCCV15 VCCV13 VCCV11 VCCU14 VCCU12 VCCPD5B U23
VCCPD8A K11VCCPD8A K13VCCPD8A L10VCCPD8A L12VCCPD8A L14
VCCBAT H9
VCCPGM J11VCCPGM AA23VCCPGM AB10
VCC_AUX AB11VCC_AUX AB16VCC_AUX AD22VCC_AUX H10VCC_AUX J16
VCC_AUX_SHARED J21
DNU6J15
DNU1F1
DNU3AA7 DNU2G2
FB87 600R,FBFB87 600R,FBFB84 180R,FBFB84 180R,FB
FB80 180R,FBFB80 180R,FB
Cyclone V GX SoCTransceiver & HPS Power
5CSXFC6D_F896
U1L Cyclone V GX SoCTransceiver & HPS Power
5CSXFC6D_F896
U1L
VCCE_GXBLAA5VCCE_GXBLM6VCCE_GXBLN5VCCE_GXBLT6
VCCL_GXBL W5
VCCE_GXBLU5VCCE_GXBLY6 VCCH_GXBL AB6VCCH_GXBL P6VCCH_GXBL V6
VCCL_GXBL L5VCCL_GXBL R5
VCCRSTCLK_HPS J20
VCCPLL_HPS L21
VCCPD6A6B_HPS M21VCCPD6A6B_HPS N22
VCCPD6A6B_HPS R23
VCCPD6A6B_HPs P21VCCPD6A6B_HPS R20
VCCPD7A_HPS K19
VCCPD7D_HPS K16
VCCIO6A_HPSK24 VCCIO6A_HPSH26 VCCIO6A_HPSG29
VCCPD7B_HPS K18
VCCPD7C_HPS J17
VCCIO6A_HPSK30
VCCIO6A_HPSD28
VCCIO6A_HPSN21
VCCIO6B_HPSP23VCCIO6B_HPSP28VCCIO6B_HPSR25VCCIO6B_HPST22
VCCIO6A_HPSL27VCCIO6A_HPSM24
VCC_HPST17
VCCIO7C_HPS D18
VCCIO6B_HPSV26
VCC_HPSN20VCC_HPSM15
VCC_HPSP17
VCC_HPSU18
VCCIO7A_HPS H21VCCIO7A_HPS F22
VCC_HPSP19
VCCIO7D_HPS H16
VCCIO7B_HPS E20
VCCIO7D_HPS E15VCC_HPSL16 VCC_HPSL20
VCCIO7B_HPS G19VCC_HPSR16
VREFB7N0_HPS E22
VCC_HPST19
VCC_HPSU16
VCC_HPSP15
VCC_HPSL18
VCCIO6B_HPSU19
VREFB6AN0_HPSG27
VREFB6BN0_HPSU30
FB63 600R,FBFB63 600R,FB
FB92 180R,FBFB92 180R,FB
FB70 600R,FBFB70 600R,FB
FB81 600R,FBFB81 600R,FB
R525
1K
R525
1K
FB60 180R,FBFB60 180R,FBFB82 600R,FBFB82 600R,FB
R5281KR5281K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
32-CV SoC GND
B
32 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
32-CV SoC GND
B
32 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
32-CV SoC GND
B
32 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
32-CV SoC GND
Cyclone V GX SoC GND
5CSXFC6D_F896
U1HCyclone V GX SoC GND
5CSXFC6D_F896
U1H
GNDJ6GNDJ22GNDD26GNDA26GNDA12GNDA17GNDA2GNDA22GNDA27GNDAA11GNDAA22GNDAA3GNDAA4GNDAA6GNDAA9GNDAB1GNDAB19GNDAB2GNDAB29GNDAB5GNDAB7GNDAC16GNDAC26GNDAC3GNDAC4GNDAC6GNDAC8GNDAD1GNDAD2GNDAD23GNDAD5GNDAE10GNDAE20GNDAE3GNDAE4GNDAF1GNDAF12GNDAF17GNDAF2GNDAF27GNDAF3GNDAG14GNDAG24GNDAG9GNDAH1GNDAH11GNDAH21GNDAH6GNDAJ18GNDAJ28GNDAJ3GNDAJ30GNDAK15GNDAK25GNDAK5GNDB14GNDB19
GND B24GND B29GND B9GND C1GND C16GND C21GND C26GND C6GND D13GND D23GND D3GND E10GND E25GND E30GND F17GND F2GND F27GND F5GND F7GND G24GND G3GND G4GND H1GND H11
GND H2GND H5GND J18GND J28GND J3GND J4GND J8GND K1GND K10GND K15GND K2GND K20GND K25
M5M5
1
M6M6
1
M7M7
1
M8M8
1
Cyclone V GX SoC GND
5CSXFC6D_F896
U1I
Cyclone V GX SoC GND
5CSXFC6D_F896
U1I
GNDK5GNDL11GNDL13GNDL15GNDL17GNDL19GNDL22GNDL3GNDL4GNDL6GNDM1GNDM10GNDM12GNDM14GNDM16GNDM18GNDM2GNDM20GNDM29GNDM5GNDM7GNDM8GNDN11GNDN13GNDN15GNDN17GNDN19GNDN26GNDN3GNDN4GNDN6GNDN8GNDN9GNDP1GNDP10GNDP12GNDP14GNDP16GNDP18GNDP2GNDP20GNDP5GNDP7GNDR11GNDR13GNDR15GNDR17GNDT20
GND U11GND U13GND U15GND U17GND U24GND U29GND U3GND U4GND U6GND U9GND V1GND V10GND V12GND V14GND V19GND V2GND V21GND V5GND V7GND W11GND W13GND W18GND W28GND W3GND W4GND W6GND W9GND Y1GND Y10GND Y12GND Y14
GND Y15GND Y2GND Y20GND Y25GND Y30GND Y5GND Y7GND Y8GND U22GND T18
GND T7
GND T1
GND T12
GND T27
GNDR8
GND T15GND T16
GND R9
GND T10
GND T5
GND T2
GND T14
GNDR4
GND R6
GNDR3GNDR30
M1M1
1
M2M2
1
T112T112
M3M3
1
T113T113 T114T114 T115T115
M4M4
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.1V_VDD
1.1V_VDD
1.1V_AVDD
1.5V_VDD
1.5V_VDD
3.3V_VDD
3.3V_VDD
2.5V_AVDD
2.5V_VDD
2.5V_AUX2.5V_VDD 2.5V_VDD
1.8V_VDD
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
33-Decoupling
B
33 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
33-Decoupling
B
33 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
33-Decoupling
B
33 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
33-Decoupling
C563
4.7uF
C563
4.7uF
C5554.7nFC5554.7nF
C49047nFC49047nF
C45422nFC45422nF
C58810nFC58810nF
C46647nFC46647nF
C54622nFC54622nF
C461100nFC461100nF
C47947nFC47947nF
C47647nFC47647nF
C44322nFC44322nF
C426
4.7uF
C426
4.7uF
C534470nFC534470nF
C5064.7nFC5064.7nF
C52447nFC52447nF
C49922nFC49922nF
C457100nFC457100nF
C413
100uF
C413
100uF
C47547nFC47547nF
C58922nFC58922nF
C423220nFC423220nF
C55222nFC55222nF
C433470nFC433470nF
C48947nFC48947nF
C57247nFC57247nF
C47847nFC47847nF
C5084.7nFC5084.7nF
C5564.7nFC5564.7nF
C4514.7nFC4514.7nF
C428
2.2uF
C428
2.2uF
C5904.7nFC5904.7nF
C48010nFC48010nF
C54722nFC54722nF
C417220nFC417220nF
C48310nFC48310nF
C43610nFC43610nF
C53710nFC53710nF
C50022nFC50022nF
C5094.7nFC5094.7nF
C48847nFC48847nF
C528100nFC528100nF
C424100nFC424100nF
C5914.7nFC5914.7nF
C55322nFC55322nF
C519
100uF
C519
100uF
C56722nFC56722nF
C460100nFC460100nF
C54510nFC54510nF
C416470nFC416470nF
C5104.7nFC5104.7nF
C564
10uF
C564
10uFC51822nFC51822nF
C54410nFC54410nF
C409
100uF
C409
100uF
C456100nFC456100nF
C531
100uF
C531
100uF
C49110nFC49110nF
C448220nFC448220nF
C5574.7nFC5574.7nF
C48747nFC48747nF
C48110nFC48110nF
C5604.7nFC5604.7nF
C418100nFC418100nF
C4444.7nFC4444.7nF
C53810nFC53810nF
C5114.7nFC5114.7nF
C50122nFC50122nF
C462
100uF
C462
100uF
C52947nFC52947nF
C46747nFC46747nF
C42547nFC42547nF
C55422nFC55422nF
C520
4.7uF
C520
4.7uF
C569
1uF
C569
1uF
C48647nFC48647nF
C57310nFC57310nF
C51222nFC51222nF
C43910nFC43910nF
C403
100uF
C403
100uF
C468
100uF
C468
100uF
C532
100uF
C532
100uF
C585
4.7uF
C585
4.7uF
C5584.7nFC5584.7nF
C49210nFC49210nF
C568
100uF
C568
100uF
C5614.7nFC5614.7nF
C430
1uF
C430
1uF
C535220nFC535220nF
C51322nFC51322nF
C582100nFC582100nF
C41947nFC41947nF
C4454.7nFC4454.7nF
C53910nFC53910nF
C406
100uF
C406
100uF
C50722nFC50722nF
C57410nFC57410nF
C54947nFC54947nF
C459100nFC459100nF
C54210nFC54210nF
C43810nFC43810nF
C469
4.7uF
C469
4.7uF
C415
4.7uF
C415
4.7uF
C43410nFC43410nF
C592
1uF
C592
1uF
C533
2.2uF
C533
2.2uF
C521470nFC521470nF
C450220nFC450220nF
C455100nFC455100nF
C57822nFC57822nF
C525
100uF
C525
100uF
C421
100uF
C421
100uF
C44010nFC44010nF
C580
100uF
C580
100uFC470470nFC470470nF
C432470nFC432470nF
C5594.7nFC5594.7nF
C49310nFC49310nF
C48422nFC48422nF
C5934.7nFC5934.7nF
C51422nFC51422nF
C584100nFC584100nF
C446220nFC446220nF
C54022nFC54022nF
C407
100uF
C407
100uF
C50322nFC50322nF
C45222nFC45222nF
C57510nFC57510nF
C447220nFC447220nF
C464470nFC464470nF
C53047nFC53047nF
C55047nFC55047nF
C581470nFC581470nF
C54310nFC54310nF
C472220nFC472220nF
C44210nFC44210nF
C404
100uF
C404
100uF
C427
4.7uF
C427
4.7uF
C43510nFC43510nF
C49722nFC49722nF
C522220nFC522220nF
C59410nFC59410nF
C5764.7nFC5764.7nF
C48210nFC48210nF
C562
1uF
C562
1uF
C526
4.7uF
C526
4.7uF
C583100nFC583100nF
C44110nFC44110nF
C56547nFC56547nF
C458100nFC458100nF
C5044.7nFC5044.7nF
C570220nFC570220nF
C49422nFC49422nF
C51522nFC51522nF
C47347nFC47347nF
C429
1uF
C429
1uF
C43710nFC43710nF
C54122nFC54122nF
C45322nFC45322nF
C414
22uF
C414
22uF
C58647nFC58647nF
C465100nFC465100nF
C5024.7nFC5024.7nF
C54822nFC54822nF
C474100nFC474100nF
C523100nFC523100nF
C49822nFC49822nF
C5774.7nFC5774.7nF
C527470nFC527470nF
C48547nFC48547nF
C58710nFC58710nF
C47147nFC47147nF
C422470nFC422470nF
C56610nFC56610nF
C55122nFC55122nF
C449220nFC449220nF
C5054.7nFC5054.7nF
C571100nFC571100nF
C405
100uF
C405
100uF
C536100nFC536100nF
C47747nFC47747nF
C49522nFC49522nF
C51622nFC51622nF
C463
1uF
C463
1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
<Title>
B
34 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
<Title>
B
34 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.Title
Size Doc Name Ver.
Date Sheet of
Design
Review
Standardize
Authorize
130602 <RevCode>
<Title>
B
34 34Friday, July 11, 2014
Harris Li
<review>
<authorize>
<standardize>
Embest Technology Co., Ltd
Copyright (c) 2013, Embest Corporation. All Rights Reserved.
