Laptop Schematic Diagram (Intel Montevina Mobile Platform)

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www.laptop-schematics.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Pillar Rock Intel Confidential 355659 TITLE PAGE A 1 58 Tuesday, August 28, 2007 1.0 Title Size Document Number Rev Date: Sheet of Pillar Rock Intel Confidential 355659 TITLE PAGE A 1 58 Tuesday, August 28, 2007 1.0 Title Size Document Number Rev Date: Sheet of Pillar Rock Intel Confidential 355659 TITLE PAGE A 1 58 Tuesday, August 28, 2007 1.0 Montevina Mobile Platform CUSTOMER REFERENCE BOARD Merom PILLAR ROCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 TITLE PAGE NOTES Penryn (1 of 2) Penryn (2 of 2) CPU Thermal Sensor CANTIGA (1 OF 6) CANTIGA (2 OF 6) CANTIGA (3 OF 6) CANTIGA (4 OF 6) CANTIGA (5 OF 6) CANTIGA (6 OF 6) CANTIGA STRAP & CAMARILLO DDR2 SODIMM 0 DDR2 SODIMM 1 DDR2 TERMINATION CRT LVDS TVO PCIE GRAPHICS XDP ICH9M (1 of 4) ICH9M (2 of 4) ICH9M (3 of 4) ICH9M (4 of 4) PCI-E Slots (1 & 2) PCI-E Slots (3,4 & 5) High Definition Audio HDA Power Supply USB 1.1/2.0 SATA (1 of 3) SATA (2 and 3 of 3) PCI Edge Connector(Gold finger) LAN Boaz LAN Docking and SPI CK505 DB800 & Buffers FWH and I/O Port Expander SIO Legacy Support H8 2116 KBC(1 of 2) H8 2116 KBC(2 of 2) PS2 LPC Slot, TPM Header, DOCKING TPS51120 SYSTEM POWER VR DDR2 VR CANTIGA VR DDR VREF GRAPHICS CORE VR SYSTEM CHARGER VR SYSTEM CHARGER BATTERY IMVP-6 CONTROLLER IMVP-6 DRIVERS&FETS CPU Decoupling DISCHARGE CIRCUITS Start Up Sequence Sleep control POWER SEQUENCING Page Description Table of Contents Rev. 1.0 Fab 3 www.laptop-schematics.com

Transcript of Laptop Schematic Diagram (Intel Montevina Mobile Platform)

Page 1: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

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Title

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Pillar Rock Intel Confidential

355659

TITLE PAGE

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1 58Tuesday, August 28, 2007

1.0

Title

Size Document Number Rev

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Pillar Rock Intel Confidential

355659

TITLE PAGE

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1.0

Title

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Pillar Rock Intel Confidential

355659

TITLE PAGE

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1 58Tuesday, August 28, 2007

1.0

Montevina Mobile PlatformCUSTOMER REFERENCE BOARD

Merom

PILLAR ROCK

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TITLE PAGENOTESPenryn (1 of 2)Penryn (2 of 2)CPU Thermal Sensor CANTIGA (1 OF 6)CANTIGA (2 OF 6)CANTIGA (3 OF 6)CANTIGA (4 OF 6)CANTIGA (5 OF 6)CANTIGA (6 OF 6)CANTIGA STRAP & CAMARILLODDR2 SODIMM 0DDR2 SODIMM 1DDR2 TERMINATION CRTLVDSTVOPCIE GRAPHICSXDPICH9M (1 of 4)ICH9M (2 of 4)ICH9M (3 of 4)ICH9M (4 of 4)PCI-E Slots (1 & 2)PCI-E Slots (3,4 & 5)High Definition AudioHDA Power SupplyUSB 1.1/2.0SATA (1 of 3)SATA (2 and 3 of 3)PCI Edge Connector(Gold finger)LAN BoazLAN Docking and SPICK505DB800 & BuffersFWH and I/O Port ExpanderSIOLegacy SupportH8 2116 KBC(1 of 2)H8 2116 KBC(2 of 2)PS2LPC Slot, TPM Header, DOCKINGTPS51120 SYSTEM POWER VRDDR2 VRCANTIGA VRDDR VREFGRAPHICS CORE VRSYSTEM CHARGER VRSYSTEM CHARGER BATTERYIMVP-6 CONTROLLERIMVP-6 DRIVERS&FETSCPU DecouplingDISCHARGE CIRCUITSStart Up SequenceSleep controlPOWER SEQUENCING

Page Description

Table of Contents Rev. 1.0

Fab 3

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MONTEVINA CUSTOMER REFERENCE PLATFORM

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

Jumper / Switch Settings

4

2

2

1 1

As seen from top

SOT23-5

3

SOT-235

3

PCB Footprints

Wake Events

State SupportedS3 S3S3S3/M1S3S3S3S3 S3S3S3S3, S4, S5 / M1

Wake EventsRI# from serial portPME# from PCI, mini PCI slot/device, LPC slot/devicePCI Express, mini PCI Express, Express-card wake eventWake on LANLID switch attached to SMCUSBHDA wake on ringSmLink for AOLIIHot Key from Scan matrix keyboardPS/2 Keyboard/mousePWRBTN#Netdetect

AddressDevice

I C / SMB Addresses2

BusHex PageJumper DescriptionDefault

J1G1J1G3J1G5J2B2J2G1J2H2J3C1J3J2J4H1J4J2J5G1J5H2J7A1J7E1J7H1J7H2J8B1J8B2J8C1J8F2J8G1J8G3J8G4J8G5J8G6J8H1J9C1J9D1J9F1J9G2J9H1J9H2J9H3J9H4

BSEL2BSEL1BSEL0CPU CORE VIDForce ShutdownGFX CORE VID CPU thermal sensorPower ON LatchNo ME G3 to M1 supportSATA Power EnableSRTC RSTCMOS ClearIn-circuit SMC ProgrammingSIO ResetSATA interlock switch for port0TPM PHYSICAL PRESENCEPM Lan enableIn-circuit SMC ProgrammingSELCETING SPI0 or SPI1 TO BE PROGRAMMEDBIOS recoverySV SetupSMC MD2CRB/SV DetectSMC MD1KBC disableBoot BIOS StrapPROGRAMMING SPI1PROGRAMMING SPI0KSC EnableBoot Block ProgrammingNMISATA interlock switch for port1LID PositionVirtual Battery

3535355256495565631212139383023403934236340644040313434404242314141

Clock GeneratorDB800 Clock BufferSO-DIMM0SO-DIMM1SO-DIMM0 Thermal SensorSO-DIMM1 Thermal SensorDDR Thermal SensorI2C Bus ExpanderAmbient Lighr SensorEMA DisplayCPU Thermal SensorIMVP6 Amb. Temp. SensorBattery ABattery BBoard ID Port ExpanderDocking Port ExpanderSkin Temperature SensorH8PCI-Slot3PCI-Gold Finger PCI-Express Slot1-5DockingPCIe x16 Slot (PEG)TPM HeaderITP-XDP

Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander.The rest come out of EC.

D2DCA0A430344C3x723C989A1C1E303298TBDTBDTBDTBDTBDTBDTBDTBD

SMB_ICH_M3SMB_ICH_M3SMB_ICH_M2SMB_ICH_M2SMB_ICH_M2SMB_ICH_M2SMB_ICH_M2SMB_ICHALSEMASMB_THRMSMB_THRMSMB_BSSMB_BSSMB_BSSMB_BSSMB_BSSMB_MESMB_ICH_A1SMB_ICH_A1SMB_ICH_A1SMB_ICH_A1SMB_ICH_S4SMB_ICH_S4SMB_ICH_S4

1101 001x1101 110x1010 000x1010 010x0011 000x0011 010x0100 110x0011 xxxx0111 001x0011 110x1001 100x1001 101x0001 110x0001 111x0011 000x0011 001x1001 100xTBDTBDTBDTBDTBDTBDTBDTBD

Interrupts

H = HostM = DDR MemoryTP = Test Point (does not connect anywhere else)

Prefix

# = Active Low Signal

LAN

REQ/GNT #AD18 D, C, A, BSlot 3

Suffix

2 2IDSEL #

(AD24 internal)

PCI Devices

Net Naming Conventions

Device

Power States

Voltage Rails

VOLTAGE DESCRIPTIONACTIVE INPOWER PLANE SL No NO_STUFF STUFF

R5E4, R5T5, R5T8,R5T9, R5T10,R5T12, R5T17

C5E8,C5E9,C5T13,C5U3 with 0 Ohm 0402 size resIPN A93549-001

J2G1(1 2), J2G1(13 14)

U6E2, U6E3, U6E4

L5F1

R5E5, R5F9, R5T16,R5U3, R5U11, R5U14,R5U21, R6V1

C5E8, C5E9, C5E11,C5E12, C5E13, C5E14,C5E15, C5T12, C5T13,C5U1, C5U2, C5U3

FB5F1, FB5F2, FB5T1

J2G1(3 4), J2G1(5 6), J2G1(7 8)

1

2

3

4

5

6

Changes for Pillar Rock with PM GMCH SKU

+VBATA+VBAT+VBATS+V12S-V12A-V12S+V5A+V5+V5S+V3.3A+V3.3M+V3.3M_CK505+V3.3+V3.3S+V1.8+V1.5S+V1.05M+V1.05S+V0.9+VCC_CORE+VCC_GFXCORE

6V-14.1V6V-14.1V6V-14.1V12V-12V-12V5V5V5V3.3V3.3V3.3V3.3V3.3V1.8V1.5V1.05V1.05V0.9V0.35V-1.5V0.7V-1.25V

S0/M0, (S3-S5)/M1, (S3-S5)/M-offS0/M0, (S3-S5)/M1, (S3-S5)/M-offS0/M0S0/M0S0/M0, (S3-S5)/M1, (S3-S5)/M-offS0/M0S0/M0, (S3-S5)/M1, (S3-S5)/M-offS0/M0, S3/M1, S3/M-offS0/M0S0/M0, (S3-S5)/M1, (S3-S5)/M-offS0/M0, (S3-S5)/M1, S3/(M-off w/WOL_EN)S0/M0, (S3-S5)/M1S0/M0, S3/M1, S3/M-offS0/M0S0/M0, (S3-S5)/M1, S3/M-offS0/M0S0/M0, (S3-S5)/M1S0/M0S0/M0, (S3-S5)/M1, S3/M-offS0/M0S0/M0

Battery Rail in Mobile Power ModeBattery Rail in Mobile Power ModeBattery Rail in Mobile Power ModeOnly on in DT Power ModeOnly on in DT Power Mode Only on in DT Power Mode

LANClock, MCH

DDR core

GMCH, ICH core, and FSB railDDR command & control pull up.CPU core railGMCH Graphics core rail

S0 (Full on)/M0

S3 (Suspend to RAM)/M1

S3 (Suspend to RAM)/Moff

S3 (Suspend to RAM)/Moff w/WOL_EN

S4 (Suspend to Disk)/M1

S5 (Soft Off)/M1

S4 (Suspend to Disk)/Moff

S5 (Soft Off)/Moff

SLP_S3#HIGH

LOW

LOW

LOW

LOW

LOW

LOW

LOW

S4_STATE#HIGH

HIGH

HIGH

HIGH

LOW

LOW

LOW

LOW

SLP_S4#HIGH

HIGH

HIGH

HIGH

HIGH

HIGH

LOW

LOW

SLP_S5#HIGH

HIGH

HIGH

HIGH

HIGH

LOW

HIGH

LOW

SLP_M#HIGH

HIGH

LOW

LOW

HIGH

HIGH

LOW

LOW

+V*AON

ON

ON

ON

ON

ON

ON

ON

+V3.3M_WOLON

ON

OFF

ON

ON

ON

OFF

OFF

+V1.05MON

ON

OFF

OFF

ON

ON

OFF

OFF

+V3.3MON

ON

OFF

OFF

ON

ON

OFF

OFF

+V1.8/+V0.9ON

ON

ON

ON

ON

ON

OFF

OFF

+V5/+V3.3ON

ON

ON

ON

OFF

OFF

OFF

OFF

+V*SON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ClocksON

only MCH BCLK

OFF

OFF

only MCH BCLK

only MCH BCLK

OFF

OFF

Power ButtonReset ButtonNet Detect

SW1C1SW1C2SW8E1

565656

ReferencePage

LEDs and Switches

LEDxTA ActivityVID0VID1VID2VID3VID4VID5VID6Num LockScroll LockCaps LockS3M0/M1S4S5S0System Power GoodLT Status

213939393939393940404057575757575764

CR7H1CR1B1CR1B2CR1B3CR1B4CR1B5CR1B6CR1B7CR9G1CR9G3CR9G2CR5H6CR5H3CR5H7CR5H5CR5H4CR7H3CR8G1

Switch Default Description PageSW9H1SW9H3SW9H2SW7J1

1 - 21 - 21 - 21 - 2

Virtual DockingVirtual BatteryLID SwitchHybrid GFX switch

41414141

1-21-21-2All OPEN1-XAll OPEN1-2, 3-41-X1-X1-21-X1-X1-21-21-21-X1-21-21-X1-X1-X1-X1-X1-21-X1-21-X1-X1-21-21-X1-21-X1-X

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D D

C C

B B

A A

H_A#30

H_A#11

H_A#22

H_A#8

H_A#10

H_A#16

H_A#19

H_A#9

H_A#3

H_A#5

H_A#26

H_A#24

H_A#31

H_A#6

H_A#28

H_A#20

H_A#27

H_A#12

H_A#21

H_A#14

H_A#4

H_A#7

H_A#15

H_A#23

H_A#18

H_A#13

H_A#25

H_A#29

H_A#17

H_A#32H_A#33H_A#34H_A#35

H_REQ#0H_REQ#1

H_REQ#4

H_REQ#2H_REQ#3

XDP_TDI

XDP_TMS

XDP_BPM#5

XDP_TCK

H_D#47

H_D#36

H_D#41H_D#40

H_D#42

H_D#34

H_D#37

H_D#45

H_D#39

H_D#33

H_D#35

H_D#32

H_D#46

H_D#38

H_D#44H_D#43

H_D#55

H_D#59H_D#60

H_D#50

H_D#57H_D#58

H_D#56

H_D#48

H_D#61

H_D#63H_D#62

H_D#54

H_D#52

H_D#49

H_D#53

H_D#51

COMP3COMP2COMP1COMP0

TP_CPU_RSVD01

TP_CPU_RSVD03TP_CPU_RSVD04

TP_CPU_RSVD02

TP_CPU_RSVD05

XDP_TRST#

H_RS#2

H_RS#0H_RS#1

H_PROCHOT#_D

H_D#28

H_D#16H_D#17

H_D#27

H_D#29

H_D#18

H_D#31H_D#30

H_D#21H_D#22

H_D#26H_D#25

H_D#23H_D#24

H_D#19

H_D#4

H_D#13H_D#14

H_D#1

H_D#12

H_D#9

H_D#2

H_D#10

H_D#15

H_D#5

H_D#0

H_D#11

H_D#7

H_D#3

H_D#8

H_D#6

H_D#20

H_IERR#_R

TP_CPU_RSVD07TP_CPU_RSVD08

CPU_TEST4

+V1.05S_CPU4,20,35,39,43,52,54

+V1.05S_CPU4,20,35,39,43,52,54

H_D#[63:0] 6

H_DINV#2 6H_DSTBP#2 6H_DSTBN#2 6

H_D#[63:0] 6

H_DSTBP#3 6H_DINV#3 6

H_DSTBN#3 6

H_DPWR# 6

H_ADS# 6

H_DRDY# 6

H_BREQ# 6

H_BNR# 6

H_DBSY# 6

H_HITM# 6H_HIT# 6

XDP_BPM#3 35

H_LOCK# 6

H_PROCHOT# 52

XDP_BPM#0 20

H_A#[35:3]6

H_A#[35:3]6

H_ADSTB#06H_REQ#[4:0]6

H_ADSTB#16

H_D#[63:0]6

H_DINV#06H_DSTBP#06H_DSTBN#06

H_D#[63:0]6

H_DSTBN#16

H_DINV#16H_DSTBP#16

CPU_TEST3

CPU_TEST5

+V1.05S_CPU4,20,35,39,43,52,54

+V1.05S_CPU4,20,35,39,43,52,54

CPU_TEST6

CPU_RSVD06

CPU_RSVD09

CPU_TEST1CPU_TEST2

H_STPCLK#_R

H_NMI21,43H_SMI#21,43

H_A20M#21

H_STPCLK#21,43

H_IGNNE#21

H_INTR21

H_DPSLP# 21,43H_DPRSTP# 7,21,43

H_PWRGD 21,43H_CPUSLP# 6,43

H_BPRI# 6

H_DEFER# 6

H_CPURST# 6,20

H_INIT# 21

XDP_TDI 20

H_TRDY# 6

H_RS#[2:0] 6

XDP_TRST# 20XDP_TMS 20

XDP_TCK 20

H_THERMDA 5

CLK_CPU_BCLK 35CLK_CPU_BCLK# 35

XDP_BPM#5 20

H_GTLREF

H_PROCHOT#_D

PSI# 52

H_IERR#

XDP_BPM#1 35XDP_BPM#2 35

XDP_BPM#4 20

H_PWRGD_XDP 20

H_FERR#21

XDP_DBRESET# 20

XDP_TDO 20

H_THERMDC 5

PM_THRMTRIP# 7,21

CPU_BSEL035CPU_BSEL135CPU_BSEL235

CPU_TEST7

Title

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Penryn (1 of 2)

Custom

3 58Tuesday, August 28, 2007

Title

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Penryn (1 of 2)

Custom

3 58Tuesday, August 28, 2007

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355659 1.0

Penryn (1 of 2)

Custom

3 58Tuesday, August 28, 2007

Layout note: no stub on H_STPCLK TP.H_STPCLK# to be routed in daisychain fashion from ICH to LPC slot and then to CPU.

Layout note:Comp0,2 connect with Zo=27.4ohm, maketrace length shorter than 0.5".Comp1,3 connect with Zo=55ohm, maketrace length shorter than 0.5".

Layout: Connecttest point TP3E2with no stub

Place Series Resistoron H_PWRGD_XDP WithoutStub

Layout Note: TP2F1 should be placedclose to J1G7

Connect H_IERR# with nostub to the connectorJ2H1 and then connectto the 56 ohm pull upResistor R2H2.

Place testpoint onH_IERR# with a GND0.1" away

PM_THRMTRIP# should connectto ICH9 and GMCH withoutT-ing (No stub)

Layout note: Zo=55 ohm,0.5" max for GTLREF.

Place TP1D1 closeto CPU.

Place C1T1 close to the CPU_TEST4 pin.Make sure CPU_TEST4 routing is referenceto GND and away from other noisy signals.

Layout Note: Place R1U6 close to CPU with stub length <200mils.

TP3E2

NO_STUFF

TP3E2

NO_STUFF

R1R161K

.1%

R1R161K

.1%

R1T2 54.91%

R1T2 54.91%

R2R3 27.4 1%R2R3 27.4 1%

R3P

51K

NO

_S

TU

FF

R3P

51K

NO

_S

TU

FF

A[10]#N3

A[11]#P5

A[12]#P2

A[13]#L2

A[14]#P4

A[15]#P1

A[16]#R1

A[17]#Y2

A[18]#U5

A[19]#R3

A[20]#W6

A[21]#U4

A[22]#Y5

A[23]#U1

A[24]#R4

A[25]#T5

A[26]#T3

A[27]#W2

A[28]#W5

A[29]#Y4

A[3]#J4

A[30]#U2

A[31]#V4

RSVD[01]M4

RSVD[02]N5

RSVD[03]T2

RSVD[04]V3

RSVD[05]B2

RSVD[06]D2

RSVD[07]D22

A[4]#L5

A[5]#L4

A[6]#K5

A[7]#M3

A[8]#N2

A[9]#J1

A20M#A6

ADS#H1

ADSTB[0]#M1

ADSTB[1]#V1

RSVD[08]D3

BCLK[0]A22

BCLK[1]A21

BNR#E2

BPM[0]#AD4

BPM[1]#AD3

BPM[2]#AD1

BPM[3]#AC4

BPRI#G5

BR0#F1

DBR#C20

DBSY#E1

DEFER#H5

DRDY#F21

FERR#A5

HIT#G6

HITM#E4

IERR#D20

IGNNE#C4

INIT#B3

LINT0C6

LINT1B4

LOCK#H4

PRDY#AC2

PREQ#AC1

PROCHOT#D21

REQ[0]#K3

REQ[1]#H2

REQ[2]#K2

REQ[3]#J3

REQ[4]#L1

RESET#C1

RS[0]#F3

RS[1]#F4

RS[2]#G3

SMI#A3

STPCLK#D5

TCKAC5

TDIAA6

TDOAB3

THERMTRIP#C7

THERMDAA24

THERMDCB25

TMSAB5

TRDY#G2

TRST#AB6

A[32]#W3

A[33]#AA4

A[34]#AB2

A[35]#AA3

RSVD[09]F6

ADDR GROUP_0

ADDR GROUP_1

CONTROL

XDP/ITP SIGNALS

H CLK

THERMAL

RESERVED

ICH

U2E1A

Penryn_Ball-out_Rev_1p0

ADDR GROUP_0

ADDR GROUP_1

CONTROL

XDP/ITP SIGNALS

H CLK

THERMAL

RESERVED

ICH

U2E1A

Penryn_Ball-out_Rev_1p0

TP1F1NO_STUFF

TP1F1NO_STUFF

COMP[0]R26

COMP[1]U26

COMP[2]AA1

COMP[3]Y1

D[0]#E22

D[1]#F24

D[10]#J24

D[11]#J23

D[12]#H22

D[13]#F26

D[14]#K22

D[15]#H23

D[16]#N22

D[17]#K25

D[18]#P26

D[19]#R23

D[2]#E26

D[20]#L23

D[21]#M24

D[22]#L22

D[23]#M23

D[24]#P25

D[25]#P23

D[26]#P22

D[27]#T24

D[28]#R24

D[29]#L25

D[3]#G22

D[30]#T25

D[31]#N25

D[32]#Y22

D[33]#AB24

D[34]#V24

D[35]#V26

D[36]#V23

D[37]#T22

D[38]#U25

D[39]#U23

D[4]#F23

D[40]#Y25

D[41]#W22

D[42]#Y23

D[43]#W24

D[44]#W25

D[45]#AA23

D[46]#AA24

D[47]#AB25

D[48]#AE24

D[49]#AD24

D[5]#G25

D[50]#AA21

D[51]#AB22

D[52]#AB21

D[53]#AC26

D[54]#AD20

D[55]#AE22

D[56]#AF23

D[57]#AC25

D[58]#AE21

D[59]#AD21

D[6]#E25

D[60]#AC22

D[61]#AD23

D[62]#AF22

D[63]#AC23

D[7]#E23

D[8]#K24

D[9]#G24

TEST5AF1

DINV[0]#H25

DINV[1]#N24

DINV[2]#U22

DINV[3]#AC20

DPRSTP#E5

DPSLP#B5

DPWR#D24

DSTBN[0]#J26

DSTBN[1]#L26

DSTBN[2]#Y26

DSTBN[3]#AE25

DSTBP[0]#H26

DSTBP[1]#M26

DSTBP[2]#AA26

DSTBP[3]#AF24

GTLREFAD26

PSI#AE6

PWRGOODD6

SLP#D7

TEST3C24

BSEL[0]B22

BSEL[1]B23

BSEL[2]C21

TEST2D25

TEST4AF26

TEST6A26

TEST1C23

TEST7C3

DATA GRP 0

DATA GRP 1

DATA GRP 2

DATA GRP 3

MISC

U2E1B

Penryn_Ball-out_Rev_1p0

DATA GRP 0

DATA GRP 1

DATA GRP 2

DATA GRP 3

MISC

U2E1B

Penryn_Ball-out_Rev_1p0

R2U110

.

R2U110

.

R1R172K

.1%

R1R172K

.1%

R2U2 54.9 1%R2U2 54.9 1%

R1R468

.

5%

R1R468

.

5%

TP2F1NO_STUFF TP2F1NO_STUFF

R1U6 54.91%

R1U6 54.91%

R1T3649

.

1%

R1T3649

.

1%

R2H256R2H256

R2H3

56

R2H3

56

TP1D1

NO_STUFF

TP1D1

NO_STUFF

R1D10

.

R1D10

.

R2R2 54.9 1%R2R2 54.9 1%

R2U4 54.91%

R2U4 54.91%

R3P

61K

NO

_S

TU

FF

R3P

61K

NO

_S

TU

FF

R2U1 27.4 1%R2U1 27.4 1%

R1U151K

.5%

R1U151K

.5%

R2U3 54.91%

R2U3 54.91%

C1T1

0.1uF

NO_STUFF10%

C1T1

0.1uF

NO_STUFF10%

www.laptop-schematics

.com

Page 4: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCCA_PROC

CPU_G21

+VCC_CORE53,54,55

+V1.05S_CPU3,20,35,39,43,52,54

+VCC_CORE53,54,55

+V1.05S9,10,24,47,55

+VCC_CORE53,54,55

+V1.5S10,11,24,28,47,55,57

H_VID6 52

H_VID4 52H_VID5 52

H_VID1 52

H_VID3 52

H_VID0 52

H_VID2 52

VSSSENSE 52

VCCSENSE 52

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Penryn (2 of 2)

Custom

4 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Penryn (2 of 2)

Custom

4 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Penryn (2 of 2)

Custom

4 58Tuesday, August 28, 2007

R3T2 is for test purpose only.

Layout Note:Route VCCSENSE and VSSSENSE traces at27.4 Ohms with 50 mil spacing.Place PU and PD within 1 inch of CPU.

Layout Note:Place C3R3 near pin-B26

R1T14100

.1%

R1T14100

.1%

12R3U2

0NO_STUFF

R3U2

0NO_STUFF

12R3U1

0NO_STUFF

R3U1

0NO_STUFF

VCC[001]A7

VCC[002]A9

VCC[003]A10

VCC[004]A12

VCC[005]A13

VCC[006]A15

VCC[007]A17

VCC[008]A18

VCC[009]A20

VCC[010]B7

VCC[011]B9

VCC[012]B10

VCC[013]B12

VCC[014]B14

VCC[015]B15

VCC[016]B17

VCC[017]B18

VCC[018]B20

VCC[019]C9

VCC[020]C10

VCC[021]C12

VCC[022]C13

VCC[023]C15

VCC[024]C17

VCC[025]C18

VCC[026]D9

VCC[027]D10

VCC[028]D12

VCC[029]D14

VCC[030]D15

VCC[031]D17

VCC[032]D18

VCC[033]E7

VCC[034]E9

VCC[035]E10

VCC[036]E12

VCC[037]E13

VCC[038]E15

VCC[039]E17

VCC[040]E18

VCC[041]E20

VCC[042]F7

VCC[043]F9

VCC[044]F10

VCC[045]F12

VCC[046]F14

VCC[047]F15

VCC[048]F17

VCC[049]F18

VCC[050]F20

VCC[051]AA7

VCC[052]AA9

VCC[053]AA10

VCC[054]AA12

VCC[055]AA13

VCC[056]AA15

VCC[057]AA17

VCC[058]AA18

VCC[059]AA20

VCC[060]AB9

VCC[061]AC10

VCC[062]AB10

VCC[063]AB12

VCC[064]AB14

VCC[065]AB15

VCC[066]AB17

VCC[067]AB18

VCC[068]AB20

VCC[069]AB7

VCC[070]AC7

VCC[071]AC9

VCC[072]AC12

VCC[073]AC13

VCC[074]AC15

VCC[075]AC17

VCC[076]AC18

VCC[077]AD7

VCC[078]AD9

VCC[079]AD10

VCC[080]AD12

VCC[081]AD14

VCC[082]AD15

VCC[083]AD17

VCC[084]AD18

VCC[085]AE9

VCC[086]AE10

VCC[087]AE12

VCC[088]AE13

VCC[089]AE15

VCC[090]AE17

VCC[091]AE18

VCC[092]AE20

VCC[093]AF9

VCC[094]AF10

VCC[095]AF12

VCC[096]AF14

VCC[097]AF15

VCC[098]AF17

VCC[099]AF18

VCC[100]AF20

VCCA[01]B26

VCCP[03]J6

VCCP[04]K6

VCCP[05]M6

VCCP[06]J21

VCCP[07]K21

VCCP[08]M21

VCCP[09]N21

VCCP[10]N6

VCCP[11]R21

VCCP[12]R6

VCCP[13]T21

VCCP[14]T6

VCCP[15]V21

VCCP[16]W21

VCCSENSEAF7

VID[0]AD6

VID[1]AF5

VID[2]AE5

VID[3]AF4

VID[4]AE3

VID[5]AF3

VID[6]AE2

VSSSENSEAE7

VCCA[02]C26

VCCP[01]G21

VCCP[02]V6

U2E1C

Penryn_Ball-out_Rev_1p0

.

U2E1C

Penryn_Ball-out_Rev_1p0

.

C3R30.01uF

.10%

C3R30.01uF

.10%

R3T20

.

R3T20

.

R3R13 0.011%

R3R13 0.011%

R1T16100

.1%

R1T16100

.1%

C2U2270uF

.20%

C2U2270uF

.20%

TP3E1NO_STUFF

TP3E1NO_STUFF

VSS[082]P6

VSS[148]AE11

VSS[002]A8

VSS[003]A11

VSS[004]A14

VSS[005]A16

VSS[006]A19

VSS[007]A23

VSS[008]AF2

VSS[009]B6

VSS[010]B8

VSS[011]B11

VSS[012]B13

VSS[013]B16

VSS[014]B19

VSS[015]B21

VSS[016]B24

VSS[017]C5

VSS[018]C8

VSS[019]C11

VSS[020]C14

VSS[021]C16

VSS[022]C19

VSS[023]C2

VSS[024]C22

VSS[025]C25

VSS[026]D1

VSS[027]D4

VSS[028]D8

VSS[029]D11

VSS[030]D13

VSS[031]D16

VSS[032]D19

VSS[033]D23

VSS[034]D26

VSS[035]E3

VSS[036]E6

VSS[037]E8

VSS[038]E11

VSS[039]E14

VSS[040]E16

VSS[041]E19

VSS[042]E21

VSS[043]E24

VSS[044]F5

VSS[045]F8

VSS[046]F11

VSS[047]F13

VSS[048]F16

VSS[049]F19

VSS[050]F2

VSS[051]F22

VSS[052]F25

VSS[053]G4

VSS[054]G1

VSS[055]G23

VSS[056]G26

VSS[057]H3

VSS[058]H6

VSS[059]H21

VSS[060]H24

VSS[061]J2

VSS[062]J5

VSS[063]J22

VSS[064]J25

VSS[065]K1

VSS[066]K4

VSS[067]K23

VSS[068]K26

VSS[069]L3

VSS[070]L6

VSS[071]L21

VSS[072]L24

VSS[073]M2

VSS[074]M5

VSS[075]M22

VSS[076]M25

VSS[077]N1

VSS[078]N4

VSS[079]N23

VSS[080]N26

VSS[081]P3

VSS[162]A25

VSS[161]AF21

VSS[160]AF19

VSS[159]AF16

VSS[158]AF13

VSS[157]AF11

VSS[156]AF8

VSS[155]AF6

VSS[154]A2

VSS[153]AE26

VSS[152]AE23

VSS[151]AE19

VSS[083]P21

VSS[084]P24

VSS[085]R2

VSS[086]R5

VSS[087]R22

VSS[088]R25

VSS[089]T1

VSS[090]T4

VSS[091]T23

VSS[092]T26

VSS[093]U3

VSS[094]U6

VSS[095]U21

VSS[096]U24

VSS[097]V2

VSS[098]V5

VSS[099]V22

VSS[100]V25

VSS[101]W1

VSS[102]W4

VSS[103]W23

VSS[104]W26

VSS[105]Y3

VSS[107]Y21

VSS[108]Y24

VSS[109]AA2

VSS[110]AA5

VSS[111]AA8

VSS[112]AA11

VSS[113]AA14

VSS[114]AA16

VSS[115]AA19

VSS[116]AA22

VSS[117]AA25

VSS[118]AB1

VSS[119]AB4

VSS[120]AB8

VSS[121]AB11

VSS[122]AB13

VSS[123]AB16

VSS[124]AB19

VSS[125]AB23

VSS[126]AB26

VSS[127]AC3

VSS[128]AC6

VSS[129]AC8

VSS[130]AC11

VSS[131]AC14

VSS[132]AC16

VSS[133]AC19

VSS[134]AC21

VSS[135]AC24

VSS[136]AD2

VSS[137]AD5

VSS[138]AD8

VSS[139]AD11

VSS[140]AD13

VSS[141]AD16

VSS[142]AD19

VSS[143]AD22

VSS[144]AD25

VSS[145]AE1

VSS[146]AE4

VSS[106]Y6

VSS[001]A4

VSS[149]AE14

VSS[150]AE16

VSS[147]AE8

VSS[163]AF25

U2E1D

Penryn_Ball-out_Rev_1p0

.

U2E1D

Penryn_Ball-out_Rev_1p0

.

C3R210uF

.20%

C3R210uF

.20%

www.laptop-schematics

.com

Page 5: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ADT_THERM_DXN

ADT_THERM_DXP

ADT_THM# THRM_ALERT#

OPA567_POSIN

OP

A5

67

_IS

IN_

R

VOUT_OPAMP

OPA567_NEGIN

CPU_TACHO_R_FAN

THERM_DXP

THERM_DXN

+V5S11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

SMB_THRM_DATA 12,40,43

SMB_THRM_CLK 12,40,43

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

H_THERMDC3

CPU_PWM_FAN40,43

H_THERMDA3

PM_THRM# 12,23,40,43

CPU_TACHO_FAN 40,43

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CPU Thermal Sensor & Fan

A

5 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CPU Thermal Sensor & Fan

A

5 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CPU Thermal Sensor & Fan

A

5 58Tuesday, August 28, 2007

CPU Fan Power Control

Layout Note:Route H_THERMDA andH_THERMDC on same layer w/10 mil trace & 10 milspacing. Route away fromnoise sources with groundguard tracks on each side.

Thermal Diode Connector

J3C1

1-2 3-4

1-X 3-X

CPU Thermal Sensor

Note: No-Stuff R3N20 for normal operation, NoStuff (R9G11, Sheet 40) if R3N20 is stuffed

Connects the Internal CPUThermal sensor to theADT7461A (Default)

Connect an externalThermal sensor to theADT7461A

Note: No-Stuff R2N4 to Disable PWM control of FAN

NOTE : R3N27, R3N26, C3N11 are placeholders forthe new thermal sensor (NS LM95245).

R3N620K

.5%

R3N620K

.5%

R3N103.32K

.1%

R3N103.32K

.1%

C3N11

1000pF

NO_STUFF

5%

C3N11

1000pF

NO_STUFF

5%

R3N1415K

.1%

R3N1415K

.1%

11

33

22

CONN3_HDR.

J2B3

CONN3_HDR.

J2B3

VDD1

D+2

D-3

T_CRIT#4

GND5

OS#/A06

SMBDAT7

SMBCLK8

U3B3

LM95245C

U3B3

LM95245C

C3N40.1uF

.10%

C3N40.1uF

.10%

R3N81.74K

.1%

R3N81.74K

.1%

R3B1910K

.5%

R3B1910K

.5%

C3N64.7uF

.10%

C3N64.7uF

.10%

R3N270

.

R3N270

.

1

3

CR2N2BAT54CR2N2BAT54

R3N2210K

.5%

R3N2210K

.5%

R2N61K

.1%

R2N61K

.1%

12

3 4 5 6

THERMDNTHERMDP

GND0GND1

GND2GND3

J4A13Pin_Recepticle

NO_STUFF

THERMDNTHERMDP

GND0GND1

GND2GND3

J4A13Pin_Recepticle

NO_STUFF

R3N260

.

R3N260

.

R2N40

.

R2N40

.

13

24

J3C1

2X2HDR

J3C1

2X2HDR

1

2

3

4 5 6 7

8

9

10

11

12

13

_

+

V+

V-

TFEN

OUT

ISIFHS

EU3B1

OPA567

.

_

+

V+

V-

TFEN

OUT

ISIFHS

EU3B1

OPA567

.

C3N100.1uF20%.

C3N100.1uF20%.

R3N2110K

NO_STUFF5%

R3N2110K

NO_STUFF5%

C3B51uF

.10%

C3B51uF

.10%

R3N200

NO_STUFF

R3N200

NO_STUFF

R3N1910K

.5%

R3N1910K

.5%

www.laptop-schematics

.com

Page 6: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_SWING

H_RCOMP

H_D#2

H_D#57

H_D#52

H_D#45

H_D#20

H_D#6

H_D#49

H_D#32

H_D#0

H_D#51

H_D#5

H_D#8

H_D#43

H_D#56

H_D#38

H_D#30

H_D#13

H_D#34

H_D#39

H_D#26

H_D#24

H_D#21

H_D#58

H_D#4

H_D#14

H_D#60

H_D#63

H_D#9

H_D#16

H_SWING

H_REQ#3H_REQ#4

H_RS#1

H_REQ#0

H_RS#2

H_D#1

H_D#10

H_D#40

H_D#50

H_D#11H_D#12

H_D#15

H_D#17H_D#18H_D#19

H_D#22H_D#23

H_D#25

H_D#27H_D#28H_D#29

H_D#3

H_D#31

H_D#33

H_D#35H_D#36H_D#37

H_D#41H_D#42

H_D#44

H_D#46H_D#47H_D#48

H_D#53H_D#54H_D#55

H_D#59

H_D#61H_D#62

H_D#7

H_RCOMP

H_REQ#2H_REQ#1

H_RS#0

H_A#9

H_A#11

H_A#13

H_A#8

H_A#34

H_A#4

H_A#6

H_A#17

H_A#31

H_A#21H_A#22

H_A#24

H_A#19

H_A#10

H_A#15

H_A#32

H_A#35

H_A#14

H_A#7

H_A#28

H_A#25

H_A#29

H_A#33

H_A#27

H_A#12

H_A#26

H_A#3

H_A#18

H_A#16

H_A#30

H_A#20

H_A#23

H_A#5

H_ADSTB#0 3H_ADS# 3

H_BNR# 3

H_BREQ# 3

H_DBSY# 3

H_DPWR# 3

H_ADSTB#1 3

H_HIT# 3

H_REQ#[4:0] 3

H_HITM# 3

H_DINV#0 3

H_DRDY# 3

H_A#[35:3] 3

H_DINV#1 3H_DINV#2 3H_DINV#3 3

H_DSTBN#0 3H_DSTBN#1 3H_DSTBN#2 3H_DSTBN#3 3

H_DSTBP#0 3H_DSTBP#1 3H_DSTBP#2 3H_DSTBP#3 3

H_D#[63:0]3

+VCCP_GMCH10

+VCCP_GMCH10

H_SWING

H_DVREF

CLK_MCH_BCLK 35

H_LOCK# 3

CLK_MCH_BCLK# 35

H_AVREF

H_CPURST#3,20H_CPUSLP#3,43

H_DEFER# 3

H_BPRI# 3

H_RS#[2:0] 3

H_TRDY# 3

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (1 OF 6)

A

6 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (1 OF 6)

A

6 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (1 OF 6)

A

6 58Tuesday, August 28, 2007

Default= R4E6(STUFF) R4E3, R4F1(NO_STUFF) on Sheet # 65

H_VREF & H_DVREF

For EV= R4E6(NO_STUFF) R4E3, R4F1 (STUFF) on Sheet # 65

H_AVREF & H_DVREF shorted togther (same voltage divider)

H_AVREF & H_DVREF can be schoomed independently for EV (separate voltage divider)

R4E71K

.1%

R4E71K

.1%

C4F10.1uF20%.

C4F10.1uF20%.

R4E5100

.1%

R4E5100

.1%

H_A#_10P16

H_A#_11R16

H_A#_12N17

H_A#_13M13

H_A#_14E17

H_A#_15P17

H_A#_16F17

H_A#_17G20

H_A#_18B19

H_A#_19J16

H_A#_20E20

H_A#_21H16

H_A#_22J20

H_A#_23L17

H_A#_24A17

H_A#_25B17

H_A#_26L16

H_A#_27C21

H_A#_28J17

H_A#_29H20

H_A#_3A14

H_A#_30B18

H_A#_31K17

H_A#_4C15

H_A#_5F16

H_A#_6H13

H_A#_7C18

H_A#_8M16

H_A#_9J13

H_ADS#H12

H_ADSTB#_0B16

H_ADSTB#_1G17

H_BNR#A9

H_BPRI#F11

H_BREQ#G12

HPLL_CLK#AH6

H_CPURST#C12

HPLL_CLKAH7

H_D#_0F2

H_REQ#_2F13

H_REQ#_3B13

H_D#_1G8

H_D#_10M9

H_D#_20L6

H_D#_30N10

H_D#_40AA8

H_D#_50AA2

H_D#_60AE11

H_D#_8D4

H_D#_9H3

H_DBSY#B10

H_D#_11M11

H_D#_12J1

H_D#_13J2

H_D#_14N12

H_D#_15J6

H_D#_16P2

H_D#_17L2

H_D#_18R2

H_D#_19N9

H_D#_2F8

H_D#_21M5

H_D#_22J3

H_D#_23N2

H_D#_24R1

H_D#_25N5

H_D#_26N6

H_D#_27P13

H_D#_28N8

H_D#_29L7

H_D#_3E6

H_D#_31M3

H_D#_32Y3

H_D#_33AD14

H_D#_34Y6

H_D#_35Y10

H_D#_36Y12

H_D#_37Y14

H_D#_38Y7

H_D#_39W2

H_D#_4G2

H_D#_41Y9

H_D#_42AA13

H_D#_43AA9

H_D#_44AA11

H_D#_45AD11

H_D#_46AD10

H_D#_47AD13

H_D#_48AE12

H_D#_49AE9

H_D#_5H6

H_D#_51AD8

H_D#_52AA3

H_D#_53AD3

H_D#_54AD7

H_D#_55AE14

H_D#_56AF3

H_D#_57AC1

H_D#_58AE3

H_D#_59AC3

H_D#_6H2

H_D#_61AE8

H_D#_62AG2

H_D#_63AD6

H_D#_7F6

H_DEFER#E9

H_DINV#_0J8

H_DINV#_1L3

H_DINV#_2Y13

H_DINV#_3Y1

H_DPWR#J11

H_DRDY#F9

H_DSTBN#_0L10

H_DSTBN#_1M7

H_DSTBN#_2AA5

H_DSTBN#_3AE6

H_DSTBP#_0L9

H_DSTBP#_1M8

H_DSTBP#_2AA6

H_DSTBP#_3AE5

H_AVREFA11

H_DVREFB11

H_TRDY#C9

H_HIT#H9

H_HITM#E12

H_LOCK#H11

H_REQ#_0B15

H_REQ#_1K13

H_REQ#_4B14

H_A#_32B20

H_A#_33F21

H_A#_34K21

H_A#_35L20

H_SWINGC5

H_CPUSLP#E11

H_RCOMPE3

H_RS#_0B6

H_RS#_1F12

H_RS#_2C8

HOST

U5E1A

CANTIGA_1p2

HOST

U5E1A

CANTIGA_1p2

R4E224.9

.1%

R4E224.9

.1%

C4E120.1uF

NO

_S

TU

FF

10%

C4E120.1uF

NO

_S

TU

FF

10%R4E60

.

R4E60

.

R4E8221

.1%

R4E8221

.1%

R4E42K

.1%

R4E42K

.1%

www.laptop-schematics

.com

Page 7: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SM_RCOMP

DMI_RXP1

DMI_RXN2DMI_RXN1

DMI_RXP2

DMI_TXN2DMI_TXN3

PM_EXTTS#0_EC

DMI_TXN1

DMI_RXP3

SM_RCOMP#

DMI_RXP0

DMI_RXN3

DMI_RXN0

SM_RCOMP#

DMI_TXN0

SM_RCOMP_VOLSM_RCOMP_VOH

DMI_TXP0DMI_TXP1

DMI_TXP3DMI_TXP2

VSYNC

CRTIREFHSYNC

CLK_MCH_OE#

MCH_CFG_8

MCH_CFG_4

MCH_CFG_13

MCH_CFG_11

TP_MCH_NC9

MCH_CFG_12

MCH_CFG_7

TP_MCH_NC15TP_MCH_NC14

TP_MCH_NC1

THRMTRIP#_R

MCH_CFG_16

TP_MCH_NC8

MCH_CFG_6

TP_MCH_NC13

MCH_CFG_17

MCH_CFG_14

TP_MCH_NC7

MCH_CFG_5

TP_MCH_NC11TP_MCH_NC10

MCH_CFG_9

TP_MCH_NC12

TP_MCH_NC5

MCH_CFG_15

MCH_CFG_10

TP_MCH_NC6

MCH_CFG_3

RST_IN#_MCH

DPRSLPVR_R

PEG_COMP

PEG_RX#9

PEG_RX5

PEG_TX#15

PEG_TX#10

PEG_TX7

PEG_TX#5

PEG_RX#7

PEG_TX3

PEG_TX11

PEG_RX#2

PEG_RX8

PEG_TX#3

PEG_RX#4

PEG_TX5

PEG_TX#2

PEG_TX#11

PEG_TX9

PEG_TX#6

PEG_RX#3

PEG_TX#9

PEG_RX9

PEG_RX11

PEG_TX#1

PEG_TX14

PEG_RX15

PEG_TX#8

PEG_RX#10

PEG_TX#7

PEG_RX4

PEG_TX13

PEG_TX2

PEG_RX14

PEG_TX10

PEG_TX#14

PEG_RX1

PEG_RX#15

PEG_RX3

PEG_RX#6

PEG_TX12

PEG_TX6

PEG_TX4

PEG_TX1

PEG_RX13

PEG_RX7

PEG_RX#8

PEG_RX#1

PEG_TX#13

PEG_RX0

PEG_RX#14

PEG_RX#12

PEG_RX2

PEG_RX#5

PEG_TX0

PEG_TX#4

PEG_RX12

PEG_RX10

PEG_RX6

PEG_RX#0

PEG_TX15

PEG_TX#0

PEG_TX8

PEG_TX#12

PEG_RX#13

PEG_RX#11

TP_MCH_NC4TP_MCH_NC3TP_MCH_NC2

MCH_CFG_20_R

PM_EXTTS#1_R

TP_MCH_NC16

MCH_CLVREF_R

PM_SYNC#_RPM_DPRSTP#_R

LVDS_VBG

L_VDD_EN_R

MCH_TVB_DACMCH_TVA_DAC

MCH_TVC_DAC

TP_MCH_RSVD9

TP_MCH_NC17TP_MCH_NC18TP_MCH_NC19TP_MCH_NC20TP_MCH_NC21TP_MCH_NC22TP_MCH_NC23TP_MCH_NC24TP_MCH_NC25

SM_REXT

SM_RCOMP_VOH

SM_RCOMP_VOL

HDA_SDIN

HDA_CODEC_BCLK

HDA_CODEC_SDATAOUT

HDA_CODEC_RST#

HDA_CODEC_SYNC

TP_MCH_RSVD15

TP_MCH_RSVD17

TP_SM_DRAMRST#

TP_MCH_RSVD20

TP_MCH_RSVD22TP_MCH_RSVD23

SM_RCOMP

+VCC_PEG10

+V1.25S_1.05M_CANTIGA9,10

SDVO_CTRLCLK 19SDVO_CTRLDATA 19

L_CTRL_CLK17,20

CRT_DDC_DATA_MCH16CRT_DDC_CLK_MCH16

MCH_BSEL135MCH_BSEL035

MCH_BSEL235

+V1.8_GMCH9,10

+V1.8_GMCH9,10

+V3.3S5,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V1.8_GMCH9,10

CL_CLK0 23CL_DATA0 23

LVDS_DDC_CLK17LVDS_DDC_DATA17

L_CTRL_DATA17,20

DMI_TXP[3:0] 22

DMI_TXN[3:0] 22

EV_VCC_V1.05_CLVREF0

DDPC_CTRLDATA 19

DREFSSCLK 35DREFSSCLK# 35

DREFCLK 35DREFCLK# 35

M_VREF_MCH 46,48

TS#_DIMM0_113,14PM_EXTTS#0_EC40

DELAY_VR_PWRGOOD23

PM_DPRSLPVR23,43,52

H_DPRSTP#3,21,43

CLK_PCIE_3GPLL 35CLK_PCIE_3GPLL# 35

PEG_RX#[15:0] 19

PEG_RX[15:0] 19

MPWROK 23,46

PM_EXTTS#1_R 15

DMI_RXN[3:0] 22

M_CLK_DDR#1 13M_CLK_DDR#0 13

M_CLK_DDR0 13

M_CLK_DDR3 14M_CLK_DDR1 13

M_CLK_DDR#3 14

M_CLK_DDR4 14

M_CLK_DDR#4 14

CRT_HSYNC16

CRT_BLUE16

CRT_RED16

CRT_VSYNC16

CRT_GREEN16

M_ODT1 13,15

M_CKE1 13,15

M_ODT0 13,15

M_CKE4 14,15

M_CS#1 13,15

M_CKE3 14,15

M_ODT3 14,15

M_CKE0 13,15

M_CS#2 14,15

M_ODT2 14,15

M_CS#3 14,15

M_CS#0 13,15

DMI_RXP[3:0] 22 PEG_TX[15:0] 19

PEG_TX#[15:0] 19

TVA_DAC18TVB_DAC18TVC_DAC18

HDA_SDIN3 21,27

L_BKLT_EN17L_BKLT_CTRL17

MCH_RSVD_1MCH_RSVD_2MCH_RSVD_3MCH_RSVD_4

MCH_RSVD_6MCH_RSVD_5

MCH_RSVD_8MCH_RSVD_7

CL_RST#0 23

CLK_MCH_OE# 35MCH_ICH_SYNC# 23

MCH_CFG_[17:3]12

MCH_RSVD_14

MCH_TMS15

MCH_TDO15

MCH_TDI15

MCH_TCK15

MCH_CFG_18MCH_CFG_1912MCH_CFG_2012,19

GFXVR_EN 49

GFXVR_VID_0 49GFXVR_VID_1 49GFXVR_VID_2 49GFXVR_VID_3 49GFXVR_VID_4 49

LVDSB_DATA017LVDSB_DATA117LVDSB_DATA217

LVDSB_DATA#117LVDSB_DATA#017

LVDSB_DATA#217

LVDSA_DATA017LVDSA_DATA117LVDSA_DATA217

LVDSA_DATA#017LVDSA_DATA#117LVDSA_DATA#217

LVDSA_CLK#17LVDSA_CLK17LVDSB_CLK#17LVDSB_CLK17

LVDS_VDD_EN17

TV_DCONSEL1_MCH18TV_DCONSEL0_MCH18

PM_THRMTRIP#3,21

LVDSB_DATA317

LVDSB_DATA#317

LVDSA_DATA317

LVDSA_DATA#317

DDPC_CTRLCLK 19

MCH_RSVD_24MCH_RSVD_25

MCH_TSATN# 41

LVDS_IBG

PLT_RST# 19,22,25,26,38,41,57

SM_PWROK 46

PM_SYNC#23

HDA_RST# 21,27HDA_SYNC 21,27

HDA_SDOUT 21,27

HDA_BIT_CLK 21,27

MCH_CLVREF

MCH_RSVD_21

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (2 OF 6)

A

7 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (2 OF 6)

A

7 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (2 OF 6)

A

7 58Tuesday, August 28, 2007

Layout Note:Place 150 Ohm termination resistorsclose to GMCH

Layout Note:Place 150 Ohm terminationresistors close to GMCH

NOTE: All LVDS datasignals/and its complimentsSHOULD BE ROUTEDDIFFERENTIALLY

****

When the Resistors R8E7, R7H3 (Page-28) are mounted, then theresistors R7V4, R7V3, R7V8, R7V23, R5F9 should be NO_STUFF.

IMPORTANT NOTE:

NOTE:SM_DRAMRST# Would be needed for DDR3 only

R4R7 499. 1%

R4R7 499. 1%

R5R41K

NO_STUFF

1%

R5R41K

NO_STUFF

1%

R5D51K0.10%

R5D51K0.10%

R5F9 0 NO_STUFFR5F9 0 NO_STUFF

R5D110

NO_STUFF

R5D110

NO_STUFF

C5R10.01uF10%402

C5R10.01uF10%402

R5U8 0

.

5%R5U8 0

.

5%

TP5F1NO_STUFFTP5F1NO_STUFF

R5U31 0

.

R5U31 0

.

R5F130

.

R5F130

.

C5R42.2uF

.10%

C5R42.2uF

.10%

TP5F2 NO_STUFFTP5F2 NO_STUFF

R7V8 33 NO_STUFFR7V8 33 NO_STUFF

R4R11 100R4R11 100

R7V3 33 NO_STUFFR7V3 33 NO_STUFF

R5U180

.

R5U180

.

R7V4 33 NO_STUFFR7V4 33 NO_STUFF C5R32.2uF

.10%

C5R32.2uF

.10%

R5T4 150 1%R5T4 150 1%

R5U13 10KR5U13 10K

R5T3 49.9R5T3 49.9

R5F100

.

R5F100

.

C5D30.1uF

.10%

C5D30.1uF

.10%

R5U5 0

.

5%R5U5 0

.

5%

R5R1

20

NO_STUFF

1%

R5R1

20

NO_STUFF

1%

R5P20.

R5P20.

R7V23 33 NO_STUFFR7V23 33 NO_STUFF

R5D4

80.6

.

1%

R5D4

80.6

.

1%

R5T112.37K

.1%

R5T112.37K

.1%

R5R51K

NO_STUFF1%

R5R51K

NO_STUFF1%

R4T3 0

.

R4T3 0

.

R5U9 0

.

5%R5U9 0

.

5%

R5D83.01k1%

R5D83.01k1%

R5D120

NO

_S

TU

FF

1%

R5D120

NO

_S

TU

FF

1%

R5U10 30.1.

R5U10 30.1.R5T7 1.02k

0.5% .R5T7 1.02k

0.5% .

C5R20.01uF10%402

C5R20.01uF10%402

R5U12 10KR5U12 10K

R5D90

NO_STUFF

R5D90

NO_STUFF

R5U6 150 1%R5U6 150 1%

R5D61K0.10%

R5D61K0.10%

R4T20

.

R4T20

.

R5U11 30.1.

R5U11 30.1.

R5T6 150 1%R5T6 150 1%

R5U4 150 1%R5U4 150 1%

R5P5 10KR5P5 10K

R5T5 150 1%R5T5 150 1%

R5D380.6

.

1%

R5D380.6

.

1%

SA_CK_0AP24

SA_CK_1AT21

SB_CK_0AV24

SA_CK#_0AR24

SA_CK#_1AR21

SB_CK#_0AU24

SA_CKE_0BC28

SA_CKE_1AY28

SB_CKE_0AY36

SB_CKE_1BB36

SA_CS#_0BA17

SA_CS#_1AY16

SB_CS#_0AV16

SB_CS#_1AR13

SM_DRAMRST#BC36

SA_ODT_0BD17

SA_ODT_1AY17

SB_ODT_0BF15

SB_ODT_1AY13

SM_RCOMPBG22

SM_RCOMP#BH21

CFG_18P29

CFG_19R28

CFG_2P25

CFG_0T25

CFG_1R25

CFG_20T28

CFG_3P20

CFG_4P24

CFG_5C25

CFG_6N24

CFG_7M24

CFG_8E21

CFG_9C23

CFG_10C24

CFG_11N21

CFG_12P21

CFG_13T21

CFG_14R20

CFG_15M20

CFG_16L21

CFG_17H21

PM_SYNC#R29

PM_EXT_TS#_0N33

PM_EXT_TS#_1P32

PWROKAT40

RSTIN#AT11

DPLL_REF_CLKB38

DPLL_REF_CLK#A38

DPLL_REF_SSCLKE41

DPLL_REF_SSCLK#F41

DMI_RXN_0AE41

DMI_RXN_1AE37

DMI_RXN_2AE47

DMI_RXN_3AH39

DMI_RXP_0AE40

DMI_RXP_1AE38

DMI_RXP_2AE48

DMI_RXP_3AH40

DMI_TXN_0AE35

DMI_TXN_1AE43

DMI_TXN_2AE46

DMI_TXN_3AH42

DMI_TXP_0AD35

DMI_TXP_1AE44

DMI_TXP_2AF46

DMI_TXP_3AH43

ME_JTAG_TCKAL34

ME_JTAG_TDOAN35

ME_JTAG_TDIAK34

ME_JTAG_TMSAM35

RSVD22BG23

RSVD23BF23

RSVD24BH18

RSVD25BF18

PM_DPRSTP#B7

SB_CK_1AU20

SB_CK#_1AV20

RSVD20AY21

RSVD5AH9

RSVD6AH10

RSVD7AH12

RSVD8AH13

RSVD1M36

RSVD2N36

RSVD3R33

RSVD4T33

GFX_VID_0B33

GFX_VID_1B32

GFX_VID_2G33

GFX_VID_3F33

GFX_VR_ENC34

SM_RCOMP_VOHBF28

SM_RCOMP_VOLBH28

THERMTRIP#T20

DPRSLPVRR32

RSVD9K12

CL_CLKAH37

CL_DATAAH36

CL_PWROKAN36

CL_RST#AJ35

CL_VREFAH34

NC_1BG48

NC_2BF48

NC_3BD48

NC_4BC48

NC_5BH47

NC_6BG47

NC_7BE47

NC_8BH46

NC_9BF46

NC_10BG45

NC_11BH44

NC_12BH43

NC_13BH6

NC_14BH5

NC_15BG4

SDVO_CTRLCLKG36

SDVO_CTRLDATAE36

CLKREQ#K36

RSVD14T24

ICH_SYNC#H36

TSATN#B12

PEG_CLK#E43

PEG_CLKF43

NC_16BH3

GFX_VID_4E33

RSVD15B31

DDPC_CTRLCLKN28

NC_17BF3

NC_18BH2

NC_19BG2

NC_20BE2

NC_21BG1

NC_22BF1

NC_23BD1

NC_24BC1

NC_25F1

SM_VREFAV42

SM_PWROKAR36

SM_REXTBF17

RSVD17M1

HDA_BCLKB28

HDA_RST#B30

HDA_SDIB29

HDA_SDOC29

HDA_SYNCA28

DDPC_CTRLDATAM28

RSVD21B2

PM

MISC

NC

DDR CLK/ CONTROL/COMPENSATION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

ME JTAG

U5E1B

CANTIGA_1p2

PM

MISC

NC

DDR CLK/ CONTROL/COMPENSATION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

ME JTAG

U5E1B

CANTIGA_1p2

R5D101K1%

R5D101K1%

R5D125111%

.

R5D125111%

.

R5U7 150 1%R5U7 150 1%

PEG_COMPIT37

PEG_COMPOT36

PEG_RX#_0H44

PEG_RX#_1J46

PEG_RX#_2L44

PEG_RX#_3L40

PEG_RX#_4N41

PEG_RX#_5P48

PEG_RX#_6N44

PEG_RX#_7T43

PEG_RX#_8U43

PEG_RX#_9Y43

PEG_RX#_10Y48

PEG_RX#_11Y36

PEG_RX#_12AA43

PEG_RX#_13AD37

PEG_RX#_14AC47

PEG_RX#_15AD39

PEG_RX_0H43

PEG_RX_1J44

PEG_RX_2L43

PEG_RX_3L41

PEG_RX_4N40

PEG_RX_5P47

PEG_RX_6N43

PEG_RX_7T42

PEG_RX_8U42

PEG_RX_9Y42

PEG_RX_10W47

PEG_RX_11Y37

PEG_RX_12AA42

PEG_RX_13AD36

PEG_RX_14AC48

PEG_RX_15AD40

PEG_TX#_0J41

PEG_TX#_10Y40

PEG_TX#_3M40

PEG_TX#_4M42

PEG_TX#_5R48

PEG_TX#_6N38

PEG_TX#_7T40

PEG_TX#_8U37

PEG_TX#_9U40

PEG_TX#_1M46

PEG_TX#_11AA46

PEG_TX#_12AA37

PEG_TX#_13AA40

PEG_TX#_14AD43

PEG_TX#_15AC46

PEG_TX#_2M47

PEG_TX_0J42

PEG_TX_1L46

PEG_TX_2M48

PEG_TX_3M39

PEG_TX_4M43

PEG_TX_5R47

PEG_TX_6N37

PEG_TX_7T39

PEG_TX_8U36

PEG_TX_9U39

PEG_TX_10Y39

PEG_TX_11Y46

PEG_TX_12AA36

PEG_TX_13AA39

PEG_TX_14AD42

PEG_TX_15AD46

L_CTRL_CLKM32

L_CTRL_DATAM33

L_DDC_CLKK33

L_DDC_DATAJ33

L_VDD_ENM29

LVDS_IBGC44

LVDS_VBGB43

LVDS_VREFHE37

LVDS_VREFLE38

LVDSA_CLK#C41

LVDSA_CLKC40

LVDSA_DATA#_0H47

LVDSA_DATA#_1E46

LVDSA_DATA#_2G40

LVDSA_DATA_1D45

LVDSA_DATA_2F40

LVDSB_CLK#B37

LVDSB_CLKA37

LVDSB_DATA#_0A41

LVDSB_DATA#_1H38

LVDSB_DATA#_2G37

LVDSB_DATA_1G38

LVDSB_DATA_2F37

L_BKLT_ENG32

TVA_DACF25

TVB_DACH25

TVC_DACK25

TV_RTNH24

CRT_BLUEE28

CRT_DDC_CLKH32

CRT_DDC_DATAJ32

CRT_GREENG28

CRT_HSYNCJ29

CRT_TVO_IREFE29

CRT_REDJ28

CRT_IRTNG29

CRT_VSYNCL29

LVDSA_DATA_0H48

LVDSB_DATA_0B42

L_BKLT_CTRLL32

TV_DCONSEL_0C31

TV_DCONSEL_1E32

LVDSA_DATA#_3A40

LVDSA_DATA_3B40

LVDSB_DATA#_3J37

LVDSB_DATA_3K37

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

U5E1C

CANTIGA_1p2

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

U5E1C

CANTIGA_1p2

www.laptop-schematics

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Page 8: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_DQ51

M_B_DQ21

M_B_DQ25

M_B_DQ33

M_B_DQ37

M_B_DQ18

M_B_DQ20

M_B_DQ29

M_B_DQ41

M_B_DQ2M_B_DQ3

M_B_DQ63

M_B_DQ0

M_B_DQ26

M_B_DQ4

M_B_DQ44

M_B_DQ56

M_B_DQ9

M_B_DQ46

M_B_DQ7

M_B_DQ14

M_B_DQ23M_B_DQ24

M_B_DQ28

M_B_DQ31

M_B_DQ34

M_B_DQ50

M_B_DQ59

M_B_DQ40

M_B_DQ1

M_B_DQ54

M_B_DQ57

M_B_DQ6

M_B_DQ32

M_B_DQ52

M_B_DQ55

M_B_DQ60M_B_DQ61

M_B_DQ11

M_B_DQ15

M_B_DQ22

M_B_DQ35

M_B_DQ39

M_B_DQ5

M_B_DQ53

M_B_DQ8

M_B_DQ62

M_B_DQ10

M_B_DQ13

M_B_DQ16M_B_DQ17

M_B_DQ27

M_B_DQ45

M_B_DQ47

M_B_DQ58

M_B_DQ43

M_B_DQ12

M_B_DQ38

M_B_DQ42

M_B_DQ19

M_B_DQ30

M_B_DQ36

M_B_DQ48M_B_DQ49

M_A_DQ57

M_A_DQ46

M_A_DQ44

M_A_DQ30

M_A_DQ21

M_A_DQ60

M_A_DQ2

M_A_DQ5

M_A_DQ22

M_A_DQ13

M_A_DQ61

M_A_DQ56M_A_DQ55

M_A_DQ39

M_A_DQ20

M_A_DQ1

M_A_DQ49M_A_DQ48

M_A_DQ40

M_A_DQ38

M_A_DQ32

M_A_DQ0

M_A_DQ53

M_A_DQ3

M_A_DQ43

M_A_DQ23

M_A_DQ8

M_A_DQ47

M_A_DQ18

M_A_DQ11

M_A_DQ9

M_A_DQ63

M_A_DQ4

M_A_DQ25

M_A_DQ59

M_A_DQ52M_A_DQ51

M_A_DQ45

M_A_DQ27

M_A_DQ17

M_A_DQ62

M_A_DQ58

M_A_DQ54

M_A_DQ37M_A_DQ36M_A_DQ35

M_A_DQ6

M_A_DQ31

M_A_DQ16

M_A_DQ7

M_A_DQ50

M_A_DQ26

M_A_DQ15M_A_DQ14

M_A_DQ42M_A_DQ41

M_A_DQ33

M_A_DQ10

M_A_DQ34

M_A_DQ29M_A_DQ28

M_A_DQ19

M_A_DQ24

M_A_DQ12

M_A_A14

M_A_DQS#1

M_A_A6

M_A_DQS#6

M_A_DQS7

M_A_DQS#2

M_A_A12

M_A_DQS4

M_A_A3

M_A_DM4

M_A_DQS6

M_A_A11

M_A_DQS2

M_A_A10

M_A_DM0

M_A_DQS#4

M_A_DQS0

M_A_A8

M_A_A0

M_A_A4

M_A_A9

M_A_DQS#3

M_A_DM2

M_A_DM6

M_A_A7

M_A_A13

M_A_DQS#5

M_A_DM3

M_A_DQS3

M_A_DM5

M_A_DM1

M_A_A5

M_A_A1

M_A_DQS5

M_A_DM7

M_A_A2

M_A_DQS#7

M_A_DQS1

M_A_DQS#0

M_B_A14

M_B_A8

M_B_A0

M_B_DQS1

M_B_DQS#5

M_B_DQS6

M_B_DQS0

M_B_DQS#4

M_B_A12M_B_A13

M_B_A4

M_B_DM0M_B_DM1

M_B_A6M_B_A7

M_B_DM4

M_B_DQS#7

M_B_DQS4

M_B_DQS7

M_B_DM5

M_B_A9

M_B_DQS2

M_B_DM3

M_B_A10

M_B_A5

M_B_DQS#0

M_B_DQS#2

M_B_DQS3

M_B_A1

M_B_DQS5

M_B_DQS#3

M_B_A11

M_B_DM7

M_B_A3

M_B_DQS#1

M_B_DM2

M_B_A2

M_B_DM6

M_B_DQS#6

M_A_DQ[63:0]13 M_B_DQ[63:0]14

M_B_CAS# 14,15

M_B_BS2 14,15M_B_BS1 14,15M_B_BS0 14,15M_A_BS0 13,15

M_A_BS2 13,15M_A_BS1 13,15

M_B_WE# 14,15

M_B_RAS# 14,15

M_A_A[14:0] 13,15

M_A_DQS[7:0] 13

M_A_DQS#[7:0] 13

M_A_DM[7:0] 13

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[14:0] 14,15

M_B_DM[7:0] 14

M_A_CAS# 13,15M_A_RAS# 13,15

M_A_WE# 13,15

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (3 OF 6)

A

8 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (3 OF 6)

A

8 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (3 OF 6)

A

8 58Tuesday, August 28, 2007

SB_DQ_0AK47

SB_DQ_1AH46

SB_DQ_10BA48

SB_DQ_11AY48

SB_DQ_12AT47

SB_DQ_13AR47

SB_DQ_14BA47

SB_DQ_15BC47

SB_DQ_16BC46

SB_DQ_17BC44

SB_DQ_18BG43

SB_DQ_19BF43

SB_DQ_2AP47

SB_DQ_20BE45

SB_DQ_21BC41

SB_DQ_22BF40

SB_DQ_23BF41

SB_DQ_24BG38

SB_DQ_25BF38

SB_DQ_26BH35

SB_DQ_27BG35

SB_DQ_28BH40

SB_DQ_29BG39

SB_DQ_3AP46

SB_DQ_30BG34

SB_DQ_31BH34

SB_DQ_32BH14

SB_DQ_33BG12

SB_DQ_34BH11

SB_DQ_35BG8

SB_DQ_36BH12

SB_DQ_37BF11

SB_DQ_38BF8

SB_DQ_39BG7

SB_DQ_4AJ46

SB_DQ_40BC5

SB_DQ_41BC6

SB_DQ_42AY3

SB_DQ_43AY1

SB_DQ_44BF6

SB_DQ_45BF5

SB_DQ_46BA1

SB_DQ_47BD3

SB_DQ_48AV2

SB_DQ_49AU3

SB_DQ_5AJ48

SB_DQ_50AR3

SB_DQ_51AN2

SB_DQ_52AY2

SB_DQ_53AV1

SB_DQ_54AP3

SB_DQ_55AR1

SB_DQ_56AL1

SB_DQ_57AL2

SB_DQ_58AJ1

SB_DQ_59AH1

SB_DQ_6AM48

SB_DQ_60AM2

SB_DQ_61AM3

SB_DQ_62AH3

SB_DQ_63AJ3

SB_DQ_7AP48

SB_DQ_8AU47

SB_DQ_9AU46

SB_BS_0BC16

SB_BS_1BB17

SB_BS_2BB33

SB_CAS#BG16

SB_DM_0AM47

SB_DM_1AY47

SB_DM_2BD40

SB_DM_3BF35

SB_DM_4BG11

SB_DM_5BA3

SB_DM_6AP1

SB_DM_7AK2

SB_DQS_0AL47

SB_DQS_1AV48

SB_DQS_2BG41

SB_DQS_3BG37

SB_DQS_4BH9

SB_DQS_5BB2

SB_DQS_6AU1

SB_DQS_7AN6

SB_DQS#_0AL46

SB_DQS#_1AV47

SB_DQS#_2BH41

SB_DQS#_3BH37

SB_DQS#_4BG9

SB_DQS#_5BC2

SB_DQS#_6AT2

SB_DQS#_7AN5

SB_MA_0AV17

SB_MA_1BA25

SB_MA_10BB16

SB_MA_11AW33

SB_MA_12AY33

SB_MA_13BH15

SB_MA_2BC25

SB_MA_3AU25

SB_MA_4AW25

SB_MA_5BB28

SB_MA_6AU28

SB_MA_7AW28

SB_MA_8AT33

SB_MA_9BD33

SB_MA_14AU33

SB_RAS#AU17

SB_WE#BF14

DDR SYSTEM MEMORY B

U5E1E

CANTIGA_1p2

DDR SYSTEM MEMORY B

U5E1E

CANTIGA_1p2

SA_DQ_0AJ38

SA_DQ_1AJ41

SA_DQ_10AU40

SA_DQ_11AT38

SA_DQ_12AN41

SA_DQ_13AN39

SA_DQ_14AU44

SA_DQ_15AU42

SA_DQ_16AV39

SA_DQ_17AY44

SA_DQ_18BA40

SA_DQ_19BD43

SA_DQ_2AN38

SA_DQ_20AV41

SA_DQ_21AY43

SA_DQ_22BB41

SA_DQ_23BC40

SA_DQ_24AY37

SA_DQ_25BD38

SA_DQ_26AV37

SA_DQ_27AT36

SA_DQ_28AY38

SA_DQ_29BB38

SA_DQ_3AM38

SA_DQ_30AV36

SA_DQ_31AW36

SA_DQ_32BD13

SA_DQ_33AU11

SA_DQ_34BC11

SA_DQ_35BA12

SA_DQ_36AU13

SA_DQ_37AV13

SA_DQ_38BD12

SA_DQ_39BC12

SA_DQ_4AJ36

SA_DQ_40BB9

SA_DQ_41BA9

SA_DQ_42AU10

SA_DQ_43AV9

SA_DQ_44BA11

SA_DQ_45BD9

SA_DQ_46AY8

SA_DQ_47BA6

SA_DQ_48AV5

SA_DQ_49AV7

SA_DQ_5AJ40

SA_DQ_50AT9

SA_DQ_51AN8

SA_DQ_52AU5

SA_DQ_53AU6

SA_DQ_54AT5

SA_DQ_55AN10

SA_DQ_56AM11

SA_DQ_57AM5

SA_DQ_58AJ9

SA_DQ_59AJ8

SA_DQ_6AM44

SA_DQ_60AN12

SA_DQ_61AM13

SA_DQ_62AJ11

SA_DQ_63AJ12

SA_DQ_7AM42

SA_DQ_8AN43

SA_DQ_9AN44

SA_BS_0BD21

SA_BS_1BG18

SA_BS_2AT25

SA_CAS#BD20

SA_DM_0AM37

SA_DM_1AT41

SA_DM_2AY41

SA_DM_3AU39

SA_DM_4BB12

SA_DM_5AY6

SA_DM_6AT7

SA_DQS_0AJ44

SA_DQS_1AT44

SA_DQS_2BA43

SA_DQS_3BC37

SA_DQS_4AW12

SA_DQS_5BC8

SA_DQS_6AU8

SA_DQS_7AM7

SA_DM_7AJ5

SA_DQS#_0AJ43

SA_DQS#_1AT43

SA_DQS#_2BA44

SA_DQS#_3BD37

SA_DQS#_4AY12

SA_DQS#_5BD8

SA_DQS#_6AU9

SA_DQS#_7AM8

SA_MA_0BA21

SA_MA_1BC24

SA_MA_10BC21

SA_MA_11BG26

SA_MA_12BH26

SA_MA_13BH17

SA_MA_2BG24

SA_MA_3BH24

SA_MA_4BG25

SA_MA_5BA24

SA_MA_6BD24

SA_MA_7BG27

SA_MA_8BF25

SA_MA_9AW24

SA_RAS#BB20

SA_WE#AY20

SA_MA_14AY25

DDR SYSTEM MEMORY A

U5E1D

CANTIGA_1p2

DDR SYSTEM MEMORY A

U5E1D

CANTIGA_1p2

www.laptop-schematics

.com

Page 9: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCCSM_LF1

+VCCSM_LF7+VCCSM_LF6

+VCCSM_LF4

+VCCSM_LF2+VCCSM_LF3

+VCCSM_LF5

VCC_SM_42

VCC_SM_38

VCC_SM_36

+VCC_MCH_35

VCC_SM_37

VCC_SM_40

VC

C_

SM

_3

6

VC

C_

SM

_3

7

VC

C_

SM

_3

8

VC

C_

SM

_4

0

VC

C_

SM

_4

2

+V1.8 10,13,14,46,48,55,57

+VCC_GMCH+V1.05M10,15,35,47,55

+VGFX_CORE

+V1.8_GMCH 7,10

+VGFX_CORE49+VCC_GFXCORE49

+VGFX_CORE49

+V1.8_GMCH7,10

+VCC_GMCH

+V1.05S4,10,24,47,55

VCC_AXG_SENSE49VSS_AXG_SENSE49

+VCC_GFXCORE49 +V1.25S_1.05M_CANTIGA7,10

+V1.05M10,15,35,47,55

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (4 OF 6)

A

9 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (4 OF 6)

A

9 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (4 OF 6)

A

9 58Tuesday, August 28, 2007

PLACE ON THE EDGE

Place C5C7 where LVDSand DDR2 taps.

Cavity Capacitors

Place close tothe GMCH Cavity Capacitors

Place close tothe GMCH

Route VCC_AXG_SENSE andVSS_AXG_SENSEdifferentially

R5T1 is used for internaltest purpose only

NO_STUFF: R4F6STUFF: R3F1

+V1.25S_1.05M_CANTIGAFor Teenah

For Cantiga STUFF: R4F6NO_STUFF: R3F1

R4U5 TO BE STUFFED ONLY AS BACKUP OPTION FOR +VGFX_CORE

Pins BA36, BB24, BD16,BB21, AW16, AW13, AT13could be left NC forDDR2 boards

C4R100.1uF10%

C4R100.1uF10%

C5T322uF

.20%SMC0805

C5T322uF

.20%SMC0805

R4U5 0.0021%

NO_STUFF

R4U5 0.0021%

NO_STUFF

C4R60.22uF

SMC0402

C4R60.22uF

SMC0402

C5R71.0uF20%SMC0402

C5R71.0uF20%SMC0402

VCC_SM_10AY32

VCC_SM_20BF31

VCC_SM_30AW29

VCC_SM_6BD32

VCC_SM_7BC32

VCC_SM_8BB32

VCC_SM_9BA32

VCC_SM_11AW32

VCC_SM_12AV32

VCC_SM_13AU32

VCC_SM_14AT32

VCC_SM_15AR32

VCC_SM_16AP32

VCC_SM_17AN32

VCC_SM_18BH31

VCC_SM_19BG31

VCC_SM_2AN33

VCC_SM_21BG30

VCC_SM_22BH29

VCC_SM_23BG29

VCC_SM_24BF29

VCC_SM_25BD29

VCC_SM_26BC29

VCC_SM_27BB29

VCC_SM_28BA29

VCC_SM_29AY29

VCC_SM_3BH32

VCC_SM_31AV29

VCC_SM_32AU29

VCC_SM_33AT29

VCC_SM_34AR29

VCC_AXG_NCTF_10V23

VCC_AXG_NCTF_11AM21

VCC_AXG_NCTF_12AL21

VCC_AXG_NCTF_13AK21

VCC_AXG_NCTF_14W21

VCC_AXG_NCTF_15V21

VCC_AXG_NCTF_16U21

VCC_AXG_NCTF_17AM20

VCC_AXG_NCTF_18AK20

VCC_AXG_NCTF_19W20

VCC_AXG_NCTF_2V28

VCC_AXG_NCTF_20U20

VCC_AXG_NCTF_21AM19

VCC_AXG_NCTF_22AL19

VCC_AXG_NCTF_23AK19

VCC_AXG_NCTF_24AJ19

VCC_AXG_NCTF_25AH19

VCC_AXG_NCTF_26AG19

VCC_AXG_NCTF_27AF19

VCC_AXG_NCTF_28AE19

VCC_AXG_NCTF_29AB19

VCC_AXG_NCTF_3W26

VCC_AXG_NCTF_30AA19

VCC_AXG_NCTF_31Y19

VCC_AXG_NCTF_32W19

VCC_AXG_NCTF_33V19

VCC_AXG_NCTF_34U19

VCC_AXG_NCTF_35AM17

VCC_AXG_NCTF_36AK17

VCC_AXG_NCTF_37AH17

VCC_AXG_NCTF_38AG17

VCC_AXG_NCTF_39AF17

VCC_AXG_NCTF_4V26

VCC_AXG_NCTF_40AE17

VCC_AXG_NCTF_41AC17

VCC_AXG_NCTF_42AB17

VCC_AXG_NCTF_43Y17

VCC_AXG_NCTF_44W17

VCC_AXG_NCTF_45V17

VCC_AXG_NCTF_46AM16

VCC_AXG_NCTF_47AL16

VCC_AXG_NCTF_48AK16

VCC_AXG_NCTF_49AJ16

VCC_AXG_NCTF_5W25

VCC_AXG_NCTF_50AH16

VCC_AXG_NCTF_51AG16

VCC_AXG_NCTF_52AF16

VCC_AXG_NCTF_53AE16

VCC_AXG_NCTF_54AC16

VCC_AXG_NCTF_55AB16

VCC_AXG_NCTF_56AA16

VCC_AXG_NCTF_6V25

VCC_AXG_NCTF_7W24

VCC_AXG_NCTF_8V24

VCC_AXG_NCTF_9W23

VCC_SM_35AP29

VCC_SM_4BG32

VCC_SM_5BF32

VCC_AXG_NCTF_1W28

VCC_SM_1AP33

VCC_AXG_1Y26

VCC_AXG_2AE25

VCC_AXG_3AB25

VCC_AXG_4AA25

VCC_AXG_5AE24

VCC_AXG_6AC24

VCC_AXG_7AA24

VCC_AXG_8Y24

VCC_AXG_9AE23

VCC_AXG_10AC23

VCC_AXG_11AB23

VCC_AXG_12AA23

VCC_AXG_13AJ21

VCC_AXG_14AG21

VCC_AXG_15AE21

VCC_AXG_16AC21

VCC_AXG_17AA21

VCC_AXG_18Y21

VCC_AXG_19AH20

VCC_AXG_20AF20

VCC_AXG_21AE20

VCC_AXG_22AC20

VCC_AXG_23AB20

VCC_AXG_24AA20

VCC_AXG_25T17

VCC_AXG_27AM15

VCC_AXG_28AL15

VCC_AXG_30AJ15

VCC_AXG_31AH15

VCC_AXG_33AF15

VCC_AXG_34AB15

VCC_SM_LF1AV44

VCC_SM_LF2BA37

VCC_SM_LF3AM40

VCC_SM_LF4AV21

VCC_SM_LF5AY5

VCC_SM_LF6AM10

VCC_SM_LF7BB13

VCC_AXG_26T16

VCC_AXG_32AG15

VCC_AXG_35AA15

VCC_AXG_36Y15

VCC_AXG_37V15

VCC_AXG_38U15

VCC_AXG_39AN14

VCC_AXG_40AM14

VCC_AXG_41U14

VCC_AXG_42T14

VCC_AXG_SENSEAJ14

VSS_AXG_SENSEAH14

VCC_AXG_NCTF_57Y16

VCC_AXG_NCTF_58W16

VCC_AXG_NCTF_59V16

VCC_AXG_NCTF_60U16

VCC_SM_36/NCBA36

VCC_SM_37/NCBB24

VCC_SM_38/NCBD16

VCC_SM_39/NCBB21

VCC_SM_40/NCAW16

VCC_SM_41/NCAW13

VCC_SM_42/NCAT13

VCC_AXG_29AE15

POWER

VCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

U5E1G

CANTIGA_1p2

POWER

VCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

U5E1G

CANTIGA_1p2

C4R110.1uF10%

C4R110.1uF10%

C5T101.0uF20%

NO_STUFF

402

C5T101.0uF20%

NO_STUFF

402

C5T10.22uF20%

SMC0603

C5T10.22uF20%

SMC0603

R5C6 0.0021%

R5C6 0.0021%

C4R120.1uF10%

C4R120.1uF10%

C4R40.1uF

.10%SMC0402

C4R40.1uF

.10%SMC0402

C5U4270uF20%

SMC7343

C5U4270uF20%

SMC7343

C4R50.22uF

SMC0402

C4R50.22uF

SMC0402

C5C8330uF20%

SMC7343_75h

C5C8330uF20%

SMC7343_75h

C4R130.1uF

NO_STUFF

10%

C4R130.1uF

NO_STUFF

10%

12

3

+ C4T7330uF20%

smc7343_TAK

+ C4T7330uF20%

smc7343_TAK

12R3F1

0.002NO_STUFF

R3F1

0.002NO_STUFF

C4T40.1uF

.10%SMC0402

C4T40.1uF

.10%SMC0402

C4R91uF

.20%

SMC0603

C4R91uF

.20%

SMC0603

C4T30.47uF

SMC0603

C4T30.47uF

SMC0603

C5D222uF

.20%

SMC0805

C5D222uF

.20%

SMC0805

R3F2 0.0021%

R3F2 0.0021%

VCC_NCTF_1AM32

VCC_NCTF_20AC30

VCC_NCTF_29AJ29

VCC_NCTF_42AK25

VCC_NCTF_9AA32

VCC_NCTF_10Y32

VCC_NCTF_11W32

VCC_NCTF_12U32

VCC_NCTF_13AM30

VCC_NCTF_14AL30

VCC_NCTF_15AK30

VCC_NCTF_17AG30

VCC_NCTF_18AF30

VCC_NCTF_19AE30

VCC_NCTF_2AL32

VCC_NCTF_24W30

VCC_NCTF_25V30

VCC_NCTF_3AK32

VCC_NCTF_30AH29

VCC_NCTF_31AG29

VCC_NCTF_32AE29

VCC_NCTF_38AL28

VCC_NCTF_39AK28

VCC_NCTF_40AL26

VCC_NCTF_41AK26

VCC_NCTF_4AJ32

VCC_NCTF_43AK24

VCC_NCTF_5AH32

VCC_NCTF_6AG32

VCC_NCTF_7AE32

VCC_NCTF_8AC32

VCC_NCTF_33AC29

VCC_NCTF_34AA29

VCC_NCTF_35Y29

VCC_NCTF_36W29

VCC_NCTF_37V29

VCC_NCTF_26U30

VCC_NCTF_27AL29

VCC_NCTF_28AK29

VCC_NCTF_16AH30

VCC_NCTF_21AB30

VCC_NCTF_22AA30

VCC_NCTF_23Y30

VCC_1AG34

VCC_2AC34

VCC_3AB34

VCC_4AA34

VCC_5Y34

VCC_6V34

VCC_7U34

VCC_8AM33

VCC_9AK33

VCC_10AJ33

VCC_11AG33

VCC_12AF33

VCC_13AE33

VCC_14AC33

VCC_15AA33

VCC_16Y33

VCC_17W33

VCC_18V33

VCC_19U33

VCC_20AH28

VCC_21AF28

VCC_22AC28

VCC_23AA28

VCC_24AJ26

VCC_25AG26

VCC_26AE26

VCC_27AC26

VCC_28AH25

VCC_29AG25

VCC_30AF25

VCC_31AG24

VCC_32AJ23

VCC_33AH23

VCC_34AF23

VCC_35T32

VCC_NCTF_44AK23

POWER

VCC NCTF

VCC CORE

U5E1F

CANTIGA_1p2

POWER

VCC NCTF

VCC CORE

U5E1F

CANTIGA_1p2

C4T622uF

.20%SMC0805

C4T622uF

.20%SMC0805

R5U3 0.0021%

R5U3 0.0021%

C5R100.47uF

SMC0402

C5R100.47uF

SMC0402

C5T40.1uF

.10%SMC0402

C5T40.1uF

.10%SMC0402

C4R80.1uF

.10%SMC0402

C4R80.1uF

.10%SMC0402

C5T20.1uF

.10%SMC0402

C5T20.1uF

.10%SMC0402

12

3

+ C4T5330uF20%

smc7343_TAK

+ C4T5330uF20%

smc7343_TAK

C5R130.1uF

NO_STUFF

10%

C5R130.1uF

NO_STUFF

10%

C5C70.1uF

.10%

SMC0402

C5C70.1uF

.10%

SMC0402

12R4F6

0.002.

R4F6

0.002.

R5T10

.

R5T10

.

C5R110.22uF20%

SMC0603

C5R110.22uF20%

SMC0603

C5R120.1uF10%

C5R120.1uF10%

C5D122uF

.20%

SMC0805

C5D122uF

.20%

SMC0805

C4T210uF

.20%

SMC0805

C4T210uF

.20%

SMC0805

C5R81.0uF20%SMC0402

C5R81.0uF20%SMC0402

www.laptop-schematics

.com

Page 10: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V

1.0

5M

_M

CH

_P

LL

+V

1.0

5M

_M

CH

_P

LL

2

+V1.05M_PEGPLL_R

+V1.05M_PEGPLL_RC

+V1_05S_SD

+V3.3S_A_DAC_BG

+VTTLF_CAP2+VTTLF_CAP1

+VTTLF_CAP3

+V1.05M_A_SM_CK

+V1.05M_MPLL_RC

+V1.05M_A_SM

+V1.05M_DMI_LR

+V1.8_SM_CK_RR

+V_TXLVDS_PM

+V1.8_SMCK_RC

+V1.05M_A_SM_R

+V1.05M_A_SM_CK_R

+V1.05M_AXF_R

+V1.05M_PEG_LR

+V1.5S_LDO_QDAC_R

+V1.05M_DPLLB

+V1.05M_DPLLA

+V1.05M_HPLL

+V1.05M_MPLL

+V1.05M_DPLLA

+V1.05M_DPLLB

+V1.05M_HPLL

+V1.05M_MPLL

+V1.5S_TVDAC+V1.05M_MCH_PLL2

+V1.05M_PEGPLL

+V3.3S+V3.3S_HV

+V1.5S_QDAC

+V1.8_TXLVDS

+V1.05M_PEGPLL

+V1.05M_PEGPLL

+V1.5S_QDAC

+V1.25S_1.05M_CANTIGA7,9

+V1.25S_1.05M_CANTIGA

+V3.3S_TVDAC11,48,55

+V1.5S4,11,24,28,47,55,57

+V1.25S_1.05M_CANTIGA

+V1.05S4,9,24,47,55

+V1.5S4,11,24,28,47,55,57

+V1.25S_1.05M_CANTIGA7,9

+VCCP_GMCH6 +V1.05S4,9,24,47,55

+V3.3S_A_TV_CRT_BG

+V1.5S_TVDAC

+V1.05M9,15,35,47,55+VCC_DMI

+V1.8_DLVDS+V1.89,13,14,46,48,55,57

+V3.3S_A_TV_DAC

+VCC_DMI+VCC_PEG7

+VCC_PEG7 +V1.05M9,15,35,47,55

+V3.3S_HV

+V1.8_SM_CK+V1.8_GMCH7,9

+V1.89,13,14,46,48,55,57

+VCC_HDA

+V1.8_LDO46

+V3.3S_A_TV_CRT_BG +V3.3S_A_TV_DAC

+V1.5S4,11,24,28,47,55,57

+V1.05M_AXF

+V1.8_TXLVDS

+VCC_HDA

+V1.25S_1.05M_CANTIGA7,9

+V1.25S_1.05M_CANTIGA7,9

+V3.3S_A_CRT_DAC

+V1.05S4,9,24,47,55

+V1.8_LDO46

+V1.5S_LDO_QDAC28

+V3.3S

+VCCA_PEG_BG

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (5 OF 6)

A

10 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (5 OF 6)

A

10 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA (5 OF 6)

A

10 58Tuesday, August 28, 2007

NOTE: CAPS USED IN+V3.3S_TVDAC should bewithin 250mils of edgeof MCH

Topside Cap

C4R3: Edge Cap

C5R7:Cavity Cap

To use seperate filters for VCC_PEG & VCC_DMI rails No-Stuff R5E1 and stuff L5D1 ,C5C9 & R5D7

R4U2 to be stuffed & R4U4 to be no_stuffed , if val needs to bedone from switcher

R4E1 0.511%

SMR0402

R4E1 0.511%

SMR0402

R5E70

NO_STUFF

R5E70

NO_STUFF

1 2R5D7

0.002

NO_STUFF

R5D7

0.002

NO_STUFF

FB5T1

220ohm_at_100MHz

SMF0805FB5T1

220ohm_at_100MHz

SMF0805

C4R34.7uF

.10%SMC0603

C4R34.7uF

.10%SMC0603

12

R5F140.002

.

R5F140.002

.

C4E80.47uF

SMC0402

C4E80.47uF

SMC0402

C5E20.1uF

.10%SMC0402

C5E20.1uF

.10%SMC0402C4E4

4.7uF

.10%SMC0603

C4E44.7uF

.10%SMC0603

C4T122uF

.20%SMC0805

C4T122uF

.20%SMC0805

C5E120.1uF

.10%SMC0402

C5E120.1uF

.10%SMC0402

1 2L5E10.10uH

.

20%

SML0805

L5E10.10uH

.

20%

SML0805

C5E130.1uF

.10%SMC0402

C5E130.1uF

.10%SMC0402

+ C6E11220uF10%

SMC7343

.

+ C6E11220uF10%

SMC7343

.

C5E80.1uF

.10%SMC0402

C5E80.1uF

.10%SMC0402

C4R71.0uF20%SMC0402

C4R71.0uF20%SMC0402

C5T810uF

.20%SMC0805

C5T810uF

.20%SMC0805

C4E30.1uF

.10%SMC0402

C4E30.1uF

.10%SMC0402

C4E130.47uF

SMC0402

C4E130.47uF

SMC0402

1 2R5F6

0.002

R5F6

0.002

C4E50.47uF

SMC0402

C4E50.47uF

SMC0402

+ C5F1220uF10%.

+ C5F1220uF10%.

1 2R5F4

0.002

R5F4

0.002

1 2

L5F1 10uH

10%201005-548

L5F1 10uH

10%201005-548

1 2

R4F2 0

SMR1210

R4F2 0

SMR1210

1 2

R5E3 0

SMR1210

R5E3 0

SMR1210FB4F1

180ohm@100MHz

SMF0603

FB4F1

180ohm@100MHz

SMF0603

C4D30.1uF

.10%SMC0402

C4D30.1uF

.10%SMC0402

C4E74.7uF

.10%SMC0805

C4E74.7uF

.10%SMC0805

C5E50.1uF

.10%SMC0402

C5E50.1uF

.10%SMC0402

C5R622uF

.20%SMC0805

C5R622uF

.20%SMC0805

R5D130NO_STUFF

R5D130NO_STUFF

1 2R4U3

0.002

R4U3

0.002

R4D2

1.001%SMR0402

R4D2

1.001%SMR0402

C5E170.01uF10%SMC0402

C5E170.01uF10%SMC0402

C5E10.1uF

.10%SMC0402

C5E10.1uF

.10%SMC0402

+ C5C9220uF10%

NO_STUFF

SMC7343

+ C5C9220uF10%

NO_STUFF

SMC7343

VTT_19V3

VTT_20U3

VTT_21V2

VTT_22U2

VCCA_PEG_BGAD48

VCCA_PEG_PLLAA48

VCCA_CRT_DAC_1B27

VCCA_CRT_DAC_2A26

VCCA_DPLLAF47

VCCA_DPLLBL48

VCCA_HPLLAD1

VCCA_LVDSJ48

VCCA_MPLLAE1

VCCA_TV_DAC_1B24

VCCA_TV_DAC_2A24

VCCD_PEG_PLLAA47

VTT_15U6

VTT_16T6

VTT_17U5

VTT_18T5

VTT_12T8

VTT_13U7

VTT_14T7

VCCD_HPLLAF1

VTT_1U13

VTT_2T13

VTT_4T12

VTT_5U11

VTT_6T11

VTT_7U10

VTT_8T10

VTT_9U9

VTT_10T9

VTT_11U8

VTT_3U12

VCCA_SM_CK_1AP28

VCCA_SM_CK_2AN28

VCCA_DAC_BGA25

VCCD_TVDACM25

VTTLF1A8

VTTLF2L1

VTTLF3AB2

VCC_DMI_1AH48

VCC_DMI_2AF48

VCC_SM_CK_1BF21

VCC_SM_CK_2BH20

VCC_SM_CK_3BG20

VCC_SM_CK_4BF20

VCCD_LVDS_1M38

VCCD_QDACL28

VCC_AXF_1B22

VCC_AXF_2B21

VCC_AXF_3A21

VCCA_SM_1AR20

VCCA_SM_2AP20

VCCA_SM_3AN20

VCCA_SM_4AR17

VCCA_SM_5AP17

VCCA_SM_7AT16

VCCA_SM_8AR16

VCCA_SM_9AP16

VCC_TX_LVDSK47

VSSA_LVDSJ47

VCC_HV_1C35

VCC_HV_2B35

VCC_PEG_1V48

VCCD_LVDS_2L37

VCC_PEG_2U48

VCC_PEG_3V47

VCC_PEG_4U47

VCC_PEG_5U46

VCCA_SM_6AN17

VCCA_SM_CK_3AP25

VCCA_SM_CK_4AN25

VCCA_SM_CK_5AN24

VCCA_SM_CK_NCTF_1AM28

VCCA_SM_CK_NCTF_2AM26

VCCA_SM_CK_NCTF_3AM25

VCCA_SM_CK_NCTF_4AL25

VCCA_SM_CK_NCTF_5AM24

VCCA_SM_CK_NCTF_6AL24

VCCA_SM_CK_NCTF_7AM23

VTT_23T2

VTT_24V1

VTT_25U1

VCC_HV_3A35

VCC_DMI_3AH47

VCC_DMI_4AG47

VSSA_DAC_BGB25

VCCA_SM_CK_NCTF_8AL23

VCC_HDAA32

POWER

CRT

PLL

A PEG

A SM

TV

D TV/CRT

LVDS

VTTLF

PEG

SM CK

AXF

VTT

DMI

HV

A CK

A LVDS

HDA

U5E1H

CANTIGA_1p2

POWER

CRT

PLL

A PEG

A SM

TV

D TV/CRT

LVDS

VTTLF

PEG

SM CK

AXF

VTT

DMI

HV

A CK

A LVDS

HDA

U5E1H

CANTIGA_1p2

12

R5U19105%

R5U19105%

R5E60

NO_STUFF

R5E60

NO_STUFF

C4E141.0uF20%SMC0402

C4E141.0uF20%SMC0402

C5T90.01uF10%SMC0402

C5T90.01uF10%SMC0402

1 2R6E3

0.002.

R6E3

0.002.

R5T100

NO

_S

TU

FF

5%

R5T100

NO

_S

TU

FF

5%

C5E160.01uF10%SMC0402

C5E160.01uF10%SMC0402

1 2

R5E1

0.002

R5E1

0.002

C5E140.01uF10%SMC0402

C5E140.01uF10%SMC0402

C4E92.2uF

.10%SMC0805

C4E92.2uF

.10%SMC0805

12

R5F30.002

NO

_S

TU

FF

R5F30.002

NO

_S

TU

FF

1 2

L4D1

1uH30%SML0805

L4D1

1uH30%SML0805

C4E1510uF

NO

_S

TU

FF

20%SMC0805

C4E1510uF

NO

_S

TU

FF

20%SMC0805

1 2R4F5

0.002

R4F5

0.002

C5E322uF

.20%SMC0805

C5E322uF

.20%SMC0805

1 2

L6F1 10uH

10%201005-548

L6F1 10uH

10%201005-548

C5E100.1uF

.10%SMC0402

C5E100.1uF

.10%SMC0402

1 2R5F1

0.002

R5F1

0.002

12

R4U4

0.002

R4U4

0.002

1 2R4F4

0.002.

R4F4

0.002.

1 2R4R2

0.002

.

R4R2

0.002

.

R4E9

0.

R4E9

0.

R4R30

.

SMR0603

R4R30

.

SMR0603

C5R90.1uF

.10%SMC0402

C5R90.1uF

.10%SMC0402

C4E104.7uF

.10%SMC0805

C4E104.7uF

.10%SMC0805

R5R30

.SMR0603

R5R30

.SMR0603

C5E61000pF10%.SMC0402

C5E61000pF10%.SMC0402

C4E10.1uF

.10%SMC0402

C4E10.1uF

.10%SMC0402

C5U30.1uF

.10%SMC0402

C5U30.1uF

.10%SMC0402

C4R222uF

.20%SMC0805

C4R222uF

.20%SMC0805

R5E50

NO_STUFF

R5E50

NO_STUFF

R4U20NO_STUFF

R4U20NO_STUFF

C5T50.1uF

.10%SMC0402

C5T50.1uF

.10%SMC0402

1 2R5F2

0.002

R5F2

0.002

1 2R5T8

0.002.

R5T8

0.002.

C4D20.1uF

.10%SMC0402

C4D20.1uF

.10%SMC0402

C5E91.0uF20%SMC0402

C5E91.0uF20%SMC0402

1 2R4F3

0.002

R4F3

0.002

R5T21.00

1%SMR0402

R5T21.00

1%SMR0402

1 2R4D1

0.002

R4D1

0.002

C4E60.47uFSMC0603

C4E60.47uFSMC0603

1

3

CR5F1BAT54CR5F1BAT54

C5R52.2uF

NO

_S

TU

FF

10%SMC0603

C5R52.2uF

NO

_S

TU

FF

10%SMC0603

C5U20.01uF10%SMC0402

C5U20.01uF10%SMC0402

FB5U1

180ohm@100MHzSMF0603

FB5U1

180ohm@100MHzSMF0603

C5E110.1uF

.10%SMC0402

C5E110.1uF

.10%SMC0402

1 2R6E1

0.002.

R6E1

0.002.

12

+

C4E2100uFSMC7343

+

C4E2100uFSMC7343

C5E1522uF

.20%SMC0805

C5E1522uF

.20%SMC0805

R5E40

NO_STUFF5%

R5E40

NO_STUFF5%

C4R122uF

NO

_S

TU

FF

20%SMC0805

C4R122uF

NO

_S

TU

FF

20%SMC0805

1 2R6E2

0.002

NO_STUFF

R6E2

0.002

NO_STUFF

C4F2270uF20%

SMC7343

C4F2270uF20%

SMC7343

C5T60.1uF

.10%SMC0402

C5T60.1uF

.10%SMC0402

12

R5F5

0.002NO_STUFF

R5F5

0.002NO_STUFF

R5U20

NO_STUFF

R5U20

NO_STUFF

FB4E1

120ohm@100MHz

SMF0603FB4E1

120ohm@100MHz

SMF0603

+ C5U7220uF10%.

+ C5U7220uF10%.

1 2R5U1

0.002

R5U1

0.002

C5E180.1uF

.10%SMC0402

C5E180.1uF

.10%SMC0402

C5U10.1uF

.10%SMC0402

C5U10.1uF

.10%SMC0402

1 2R5F8

0.002

R5F8

0.002

C5E44.7uF

.10%SMC0805

C5E44.7uF

.10%SMC0805

C4T8

0.47uF

NO_STUFF

C4T8

0.47uF

NO_STUFF

C4D110uF

.20%SMC0805

C4D110uF

.20%SMC0805

C5E71000pF10%.SMC0402

C5E71000pF10%.SMC0402

R5T90

NO_STUFF

5%

R5T90

NO_STUFF

5%

1 2R4R1

0.002.

R4R1

0.002.

12

R4D60.002

.

R4D60.002

.

C4T90.47uF

NO_STUFF

C4T90.47uF

NO_STUFF

L5D1

91nH

NO_STUFF

20%SML1210-STD

L5D1

91nH

NO_STUFF

20%SML1210-STD

www.laptop-schematics

.com

Page 11: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TVDAC_ADJ2

V1_5SFOLLOW

V3.3S_TVDAC_R2

PM

_S

LP

_S

3_S

HD

N2

MCH_VSS_351MCH_VSS_352MCH_VSS_353MCH_VSS_354MCH_VSS_355

+V5S 5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+V5S 5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+V1.5S4,10,24,28,47,55,57

+V3.3S_TVDAC10,48,55

PM_SLP_S3#

23,40,43,44,46,47,49,55,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

CANTIGA (6 OF 6)

A

11 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

CANTIGA (6 OF 6)

A

11 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

CANTIGA (6 OF 6)

A

11 58Tuesday, August 28, 2007

R3R1010K1%

R3R1010K1%

C3D122uFC3D122uF

R4T4 0R4T4 0

12

R3R810

NO_STUFF5%

R3R810

NO_STUFF5%

C3R10.1uF

.10%

C3R10.1uF

.10%

R3R717.8K1%

R3R717.8K1%

VSS_1AU48

VSS_198A23

VSS_2AR48

VSS_3AL48

VSS_4BB47

VSS_5AW47

VSS_6AN47

VSS_7AJ47

VSS_8AF47

VSS_9AD47

VSS_10AB47

VSS_11Y47

VSS_12T47

VSS_13N47

VSS_14L47

VSS_15G47

VSS_16BD46

VSS_17BA46

VSS_19AV46

VSS_20AR46

VSS_21AM46

VSS_22V46

VSS_23R46

VSS_24P46

VSS_25H46

VSS_26F46

VSS_27BF44

VSS_28AH44

VSS_29AD44

VSS_30AA44

VSS_31Y44

VSS_32U44

VSS_33T44

VSS_34M44

VSS_35F44

VSS_36BC43

VSS_37AV43

VSS_38AU43

VSS_39AM43

VSS_40J43

VSS_41C43

VSS_42BG42

VSS_43AY42

VSS_44AT42

VSS_45AN42

VSS_46AJ42

VSS_47AE42

VSS_48N42

VSS_49L42

VSS_50BD41

VSS_51AU41

VSS_52AM41

VSS_53AH41

VSS_54AD41

VSS_55AA41

VSS_56Y41

VSS_57U41

VSS_58T41

VSS_59M41

VSS_60G41

VSS_61B41

VSS_62BG40

VSS_63BB40

VSS_64AV40

VSS_65AN40

VSS_66H40

VSS_67E40

VSS_68AT39

VSS_69AM39

VSS_70AJ39

VSS_71AE39

VSS_72N39

VSS_73L39

VSS_74B39

VSS_75BH38

VSS_76BC38

VSS_77BA38

VSS_78AU38

VSS_79AH38

VSS_80AD38

VSS_81AA38

VSS_82Y38

VSS_83U38

VSS_84T38

VSS_85J38

VSS_86F38

VSS_87C38

VSS_97BD36

VSS_100AM36

VSS_101AE36

VSS_102P36

VSS_103L36

VSS_104J36

VSS_105F36

VSS_106B36

VSS_107AH35

VSS_108AA35

VSS_109Y35

VSS_110U35

VSS_111T35

VSS_112BF34

VSS_113AM34

VSS_114AJ34

VSS_115AF34

VSS_116AE34

VSS_117W34

VSS_118B34

VSS_119A34

VSS_120BG33

VSS_121BC33

VSS_122BA33

VSS_123AV33

VSS_124AR33

VSS_125AL33

VSS_126AH33

VSS_127AB33

VSS_128P33

VSS_129L33

VSS_130H33

VSS_131N32

VSS_132K32

VSS_133F32

VSS_134C32

VSS_135A31

VSS_136AN29

VSS_137T29

VSS_138N29

VSS_139K29

VSS_140H29

VSS_141F29

VSS_142A29

VSS_143BG28

VSS_144BD28

VSS_145BA28

VSS_146AV28

VSS_147AT28

VSS_148AR28

VSS_149AJ28

VSS_150AG28

VSS_151AE28

VSS_152AB28

VSS_153Y28

VSS_154P28

VSS_155K28

VSS_156H28

VSS_157F28

VSS_158C28

VSS_159BF26

VSS_160AH26

VSS_161AF26

VSS_162AB26

VSS_163AA26

VSS_164C26

VSS_165B26

VSS_166BH25

VSS_167BD25

VSS_168BB25

VSS_169AV25

VSS_170AR25

VSS_171AJ25

VSS_172AC25

VSS_173Y25

VSS_174N25

VSS_175L25

VSS_176J25

VSS_177G25

VSS_178E25

VSS_179BF24

VSS_88BF37

VSS_89BB37

VSS_90AW37

VSS_91AT37

VSS_92AN37

VSS_93AJ37

VSS_94H37

VSS_95C37

VSS_96BG36

VSS_99AU36

VSS_182AT24

VSS_184AH24

VSS_186AB24

VSS_188L24

VSS_18AY46

VSS_191G24

VSS_193E24

VSS_195AG23

VSS_197B23

VSS_181AY24

VSS_183AJ24

VSS_185AF24

VSS_187R24

VSS_189K24

VSS_190J24

VSS_192F24

VSS_194BH23

VSS_196Y23

VSS_98AK15

VSS_180AD12

VSS

U5E1I

CANTIGA_1p2

VSS

U5E1I

CANTIGA_1p2

VSS_199BG21

VSS_201AW21

VSS_202AU21

VSS_203AP21

VSS_204AN21

VSS_205AH21

VSS_206AF21

VSS_207AB21

VSS_208R21

VSS_209M21

VSS_210J21

VSS_211G21

VSS_212BC20

VSS_213BA20

VSS_214AW20

VSS_215AT20

VSS_216AJ20

VSS_217AG20

VSS_218Y20

VSS_219N20

VSS_220K20

VSS_221F20

VSS_222C20

VSS_223A20

VSS_224BG19

VSS_225A18

VSS_226BG17

VSS_227BC17

VSS_228AW17

VSS_229AT17

VSS_230R17

VSS_231M17

VSS_232H17

VSS_233C17

VSS_235BA16

VSS_237AU16

VSS_238AN16

VSS_239N16

VSS_240K16

VSS_241G16

VSS_242E16

VSS_243BG15

VSS_245W15

VSS_246A15

VSS_247BG14

VSS_248AA14

VSS_249C14

VSS_250BG13

VSS_251BC13

VSS_252BA13

VSS_255AN13

VSS_256AJ13

VSS_257AE13

VSS_258N13

VSS_259L13

VSS_260G13

VSS_261E13

VSS_262BF12

VSS_263AV12

VSS_264AT12

VSS_265AM12

VSS_266AA12

VSS_267J12

VSS_268A12

VSS_269BD11

VSS_270BB11

VSS_271AY11

VSS_272AN11

VSS_273AH11

VSS_275Y11

VSS_276N11

VSS_277G11

VSS_278C11

VSS_279BG10

VSS_280AV10

VSS_281AT10

VSS_282AJ10

VSS_283AE10

VSS_284AA10

VSS_293BH8

VSS_292B9

VSS_291G9

VSS_290AD9

VSS_289AM9

VSS_288AN9

VSS_287BC9

VSS_285M10

VSS_286BF9

VSS_297AH8

VSS_298Y8

VSS_299L8

VSS_300E8

VSS_301B8

VSS_302AY7

VSS_303AU7

VSS_304AN7

VSS_305AJ7

VSS_306AE7

VSS_307AA7

VSS_308N7

VSS_309J7

VSS_310BG6

VSS_311BD6

VSS_312AV6

VSS_313AT6

VSS_244AC15

VSS_314AM6

VSS_315M6

VSS_316C6

VSS_317BA5

VSS_318AH5

VSS_319AD5

VSS_320Y5

VSS_321L5

VSS_322J5

VSS_323H5

VSS_324F5

VSS_325BE4

VSS_327BC3

VSS_328AV3

VSS_329AL3

VSS_NCTF_1AF32

VSS_NCTF_2AB32

VSS_NCTF_3V32

VSS_NCTF_4AJ30

VSS_NCTF_5AM29

VSS_NCTF_6AF29

VSS_NCTF_7AB29

VSS_NCTF_8U26

VSS_NCTF_9U23

VSS_NCTF_10AL20

VSS_NCTF_11V20

VSS_NCTF_12AC19

VSS_NCTF_13AL17

VSS_NCTF_14AJ17

VSS_NCTF_15AA17

VSS_NCTF_16U17

VSS_SCB_1BH48

VSS_SCB_2BH1

VSS_SCB_3A48

VSS_SCB_4C1

VSS_SCB_6A3

NC_26E1

NC_27D2

NC_28C3

NC_29B4

NC_30A5

NC_31A6

NC_32A43

NC_33A44

NC_34B45

NC_35C46

NC_36D47

NC_37B47

NC_38A46

NC_39F48

NC_40E48

NC_41C48

NC_42B48

VSS_330R3

VSS_331P3

VSS_333BA2

VSS_336AR2

VSS_335AU2

VSS_337AP2

VSS_332F3

VSS_334AW2

VSS_341AE2

VSS_340AF2

VSS_339AH2

VSS_338AJ2

VSS_342AD2

VSS_343AC2

VSS_344Y2

VSS_345M2

VSS_346K2

VSS_347AM1

VSS_348AA1

VSS_349P1

VSS_350H1

VSS_294BB8

VSS_295AV8

VSS_296AT8

VSS_351U24

VSS_352U28

VSS_353U25

VSS_354U29

VSS_200L12

VSS_355AJ6

NC_43A47

VSS

VSS NCTF

VSS SCB

NC

U5E1J

CANTIGA_1p2

VSS

VSS NCTF

VSS SCB

NC

U5E1J

CANTIGA_1p2

R5T13 0R5T13 0

1

3

CR3R2BAT54

NO_STUFF

CR3R2BAT54

NO_STUFF

R4T5 0R4T5 0

C3D21.0uF10%

C3D21.0uF10%

R3R11100

NO_STUFF5%

R3R11100

NO_STUFF5%

3

1

2

Q3D1BSS138Q3D1BSS138

R5T12 0R5T12 0

R3R910K5%

R3R910K5%

SHDN1

IN5

OUT4

GND

2

ADJ

3

U3D1 SC1563U3D1 SC1563

R3D20.011%R3D20.011%

R4R13 0

.

R4R13 0

.

www.laptop-schematics

.com

Page 12: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OPA567_NEGIN_R

MCH_TACHO_OP_FAN

OP

A5

67

_IS

IN_

MC

H_

R

OPA567_POSIN_R

7481_D1P7481_D1N

7481_D1P_Q

7481_D2N_Q

7481_THRM2#

7481_D1N_Q

7481_THRM#

MCH_TACHO_R_FAN

7481_D2P 7481_D2P_Q

7481_D2N

MCH_CFG_6_R

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

SMB_THRM_CLK 5,40,43SMB_THRM_DATA 5,40,43

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

MCH_CFG_57

MCH_CFG_167

MCH_CFG_97

MCH_CFG_207,19

MCH_CFG_137

MCH_CFG_127

MCH_PWM_FAN40,43

MCH_CFG_197

MCH_CFG_107

MCH_TACHO_FAN 40,43

PM_THRM# 5,23,40,43

MCH_CFG_77

MCH_CFG_67

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA STRAPPING

A

12 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA STRAPPING

A

12 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CANTIGA STRAPPING

A

12 58Tuesday, August 28, 2007

Low = DMIx2High = DMIx4 (default)

Layout Note:Location of all MCH_CFG strap resistorsneeds to be close to trace to minimize stub

GMCH Fan Power Control

Place in IMVP_6Hot Spot

Place ADT7481 near Air inlet not under SODIMM

Spare sensor, ForAmb. temp sensor

IMVP6 & Amb Thermal sensors

MCH_CFG_5

DMI X2 Select

Low = Dynamic ODT DisabledHigh = Dynamic ODT Enabled (default)

MCH_CFG_16

FSB Dynamic ODT

MCH_CFG_9 Low = Reverse Lane (default)High = Normal operation

PCI Express Graphics Lane

Low = Normal (default)High = Lanes Reversed

MCH_CFG_19

DMI Lane Reversal

ReservedXOR Mode Enabled

Normal Operation (Default)All-Z Mode Enabled

XOR / ALLZ / Clock Un-gatingMCH_CFG_13 MCH_CFG_12 Configuration

MCH_CFG_20 Low = Only Digital Display Port (SDVO/DP/iHDMI) or PCIE or is operational (Default)High = Digital Display Port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

Low = EnabledHigh = Disabled (Default)

MCH_CFG_10 (PCIE Loopback enable)

0101

0011

Design Note:Only one of the CFG10/CFG12/CFG13 straps can beenabled at any time

Low = AMT Firmware will use TLS cipher suite with noconfidentiality (Isolators are bypassed]High = AMT Firmware will use TLS cipher suite withConfidentiality {Isolators are active (Default)}

MCH_CFG_7 ME TLS Confidentiality (Isolation Bypass Enable)

Low = iTPM Host Interface is enabledHigh = iTPM Host Interface is Disabled (default)

MCH_CFG_6 (iTPM Host Interface)

stuff J1C3 to enable ITPM

R1T112.21K

NO_STUFF1%

R1T112.21K

NO_STUFF1%

R4P215K

.1%

R4P215K

.1%

C4C191uF

.10%

C4C191uF

.10%

C3B70.1uF20%

C3B70.1uF20%

R3P31K

.1%

R3P31K

.1%

R1T152.21K

NO_STUFF1%

R1T152.21K

NO_STUFF1%

C3N91000pF10%

C3N91000pF10%

R3B2010K1%

NO

_S

TU

FF R3B20

10K1%

NO

_S

TU

FF

1

3

CR3P1BAT54CR3P1BAT54

R1T72.21K

.1%

R1T72.21K

.1%

12

J1

C3

J1

C3

R3B170

.

R3B170

.

C3N81000pF10%

C3N81000pF10%

R3B160

.

R3B160

.R3B150

.

R3B150

.

R1E12.21K

NO_STUFF1%

R1E12.21K

NO_STUFF1%

R3B2110K1%

NO_STUFF

R3B2110K1%

NO_STUFF

R5F114.02K

NO_STUFF1%

R5F114.02K

NO_STUFF1%

R5P74.02K

NO_STUFF1%

R5P74.02K

NO_STUFF1%

R4C253.32K1%

R4C253.32K1%

R3P40

.

R3P40

.

C3P40.1uF

.10%

C3P40.1uF

.10%

R3N230

NO_STUFF

R3N230

NO_STUFF

R3P21.74K1%

R3P21.74K1%

R1T172.21K

NO_STUFF1%

R1T172.21K

NO_STUFF1%

1

3

2

Q3B12N3904Q3B12N3904

1

3

2

Q3C32N3904

Q3C32N3904

1

2

3

4 5 6 7

8

9

10

11

12

13

_

+

V+

V-

TFEN

OUT

ISIFHS

EU4C1

OPA567

.

_

+

V+

V-

TFEN

OUT

ISIFHS

EU4C1

OPA567

.

R1T122.21K

NO_STUFF1%

R1T122.21K

NO_STUFF1%

R4P120K5%

R4P120K5%

R3N240

NO_STUFF

R3N240

NO_STUFF

R1T92.21K

NO_STUFF1%

R1T92.21K

NO_STUFF1%

R1U42.21K

.1%

R1U42.21K

.1%

R3B180

.

R3B180

.

C3C134.7uF

.10%

C3C134.7uF

.10%

VDD1

D1+2

D1-3

THM#4

GND5

ALRT#/THM2#8

D2+7

D2-6

SDATA9

SCLK10

U3B2

ADT7481ARMZ-1 TEMP MON

U3B2

ADT7481ARMZ-1 TEMP MON

11

33

22

CONN3_HDR

J3C2

CONN3_HDR

J3C2

www.laptop-schematics

.com

Page 13: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SA0_DIM0

M_A_DQS5

M_A_DQS2

M_A_DQS#1

M_A_DM5

M_A_DQS#0

M_A_DM1

M_A_DQS7

M_A_DQS#3

M_A_DM3M_A_DM4

M_A_DQS0

M_A_DM2

M_A_DQS6

M_A_DQS3

M_A_DQS#6

M_A_DM0

M_A_DQS#7

M_A_DQS#5

M_A_DQS1

M_A_DM6

M_A_DQS#2

M_A_DM7

M_A_DQS#4

M_A_DQS4

SA1_DIM0

M_A_DQ18

M_A_DQ26

M_A_DQ57

M_A_DQ30

M_A_DQ37

M_A_DQ48

M_A_DQ16M_A_DQ15

M_A_DQ56

M_A_DQ0M_A_DQ1

M_A_DQ32

M_A_DQ3

M_A_DQ31

M_A_DQ55

M_A_DQ39

M_A_DQ2

M_A_DQ43

M_A_DQ5

M_A_DQ7

M_A_DQ29

M_A_DQ35

M_A_DQ12

M_A_DQ54

M_A_DQ60

M_A_DQ27

M_A_DQ14

M_A_DQ53

M_A_DQ59

M_A_DQ19

M_A_DQ9

M_A_DQ20

M_A_DQ47

M_A_DQ44

M_A_DQ62

M_A_DQ36

M_A_DQ63

M_A_DQ34

M_A_DQ25

M_A_DQ33

M_A_DQ6

M_A_DQ40

M_A_DQ10

M_A_DQ4

M_A_DQ8

M_A_DQ22

M_A_DQ13

M_A_DQ51

M_A_DQ49

M_A_DQ21

M_A_DQ58

M_A_DQ23

M_A_DQ52

M_A_DQ45

M_A_DQ38

M_A_DQ17

M_A_DQ50

M_A_DQ61

M_A_DQ28

M_A_DQ24

M_A_DQ46

M_A_DQ11

M_A_DQ41M_A_DQ42

M_A_A0

M_A_A10

M_A_A3

M_A_A5

M_A_A12

M_A_A4

M_A_A9

M_A_A1

M_A_A11

M_A_A2

M_A_A7

M_A_A13

M_A_A6

M_A_A8

+V3.3M_DIMM0

M_A_A14

M_A_DQ[63:0] 8

M_A_DQS[7:0]8

M_A_DQS#[7:0]8

+V3.3M14,15,23,35,55,57

+V1.8_DIMM0

+V1.8_DIMM0

+V1.8_DIMM0

+V1.89,10,14,46,48,55,57

+V3.3S

M_CLK_DDR17

M_A_CAS#8,15

M_CLK_DDR07

M_A_BS18,15

M_A_DM[7:0]8

M_ODT17,15M_ODT07,15

SMB_CLK_M214,15,23

M_A_WE#8,15

M_A_BS08,15

M_CKE17,15

M_CLK_DDR#07

M_CLK_DDR#17

SMB_DATA_M214,15,23

M_CS#17,15M_CS#07,15

M_A_BS28,15

M_A_RAS#8,15

M_CKE07,15

M_A_A[14:0]8,15

M_VREF_DIMM048

TS#_DIMM0_17,14

PM_EXTTS#0_DIMM0_115,40

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 SODIMM 0

A

13 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 SODIMM 0

A

13 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 SODIMM 0

A

13 58Tuesday, August 28, 2007

Layout Note: Place these Caps near SO-DIMM0.

Layout Note: Place these Caps near SO-DIMM0.

Note: SO-DIMM0 SPD Address is 0xA0SO-DIMM0 TS Address is 0x30

To connect TS on DIMM0&1 o/p to H8,stuff R5P3 and no-stuff R5P1

C4C112.2uF

.10%

C4C112.2uF

.10%

C5C42.2uF

.10%

C5C42.2uF

.10%

C4C132.2uF

.10%

C4C132.2uF

.10%

C6P12.2uF

.10%

C6P12.2uF

.10%

C4C100.1uF

.10%

C4C100.1uF

.10%

C3C70.1uF

.10%

C3C70.1uF

.10%

R5P1 10KR5P1 10K

R5C3 0.0021%

R5C3 0.0021%

VDD3117

VDD496

VDD595

VDD6118

VDD781

VDD882

VDD987

VDD10103

VDD1188

VDD12104

VDDSPD199

NC183

NC2120

EVENT#50

NC469

NCTEST163

VREF1

VSS147

VSS2133

VSS3183

VSS477

VSS512

VSS648

VSS7184

VSS878

VSS971

VSS1072

VSS11121

VSS12122

VSS13196

VSS14193

VSS158

VSS1618

VSS1724

VSS1841

VSS1953

VSS2042

VSS2154

VSS2259

VSS2365

VSS2460

VSS2566

VSS26127

VSS27139

VSS28128

VSS29145

VSS30165

VSS31171

VSS32172

VSS33177

VSS34187

VSS35178

VSS36190

VSS379

VSS3821

VSS3933

VSS40155

VSS4134

VSS42132

VSS43144

VSS44156

VSS45168

VSS462

VSS473

VSS4815

VSS4927

VSS5039

VSS51149

VSS52161

VSS5328

VSS5440

VSS55138

VSS56150

VSS57162

VDD1112

VDD2111

GND1202

GND0201

J5P1B CON200_DDR2-SODIMM-STANJ5P1B CON200_DDR2-SODIMM-STAN

R3C510K

.

5%

R3C510K

.

5%

C5C50.1uF

.10%

C5C50.1uF

.10%

C4C122.2uF

.10%

C4C122.2uF

.10%

R5P30NO_STUFF

R5P30NO_STUFF

C4C90.1uF

.10%

C4C90.1uF

.10%

R3C610K

.

5%

R3C610K

.

5%

C5C1330uF20%

2.5V

C5C1330uF20%

2.5V

C4C80.1uF

.10%

C4C80.1uF

.10%

R4C1 0.022R4C1 0.022

A0102

A1101

A2100

A399

A498

A597

A694

A792

A893

A991

A10/AP105

A1190

A1289

A13116

A1486

A1584

A16_BA285

BA0107

BA1106

S0#110

S1#115

ODT0114

ODT1119

CK030

CK0#32

CK1164

CK1#166

CKE079

CKE180

CAS#113

RAS#108

WE#109

SA0198

SA1200

SCL197

SDA195

DM010

DM126

DM252

DM367

DM4130

DM5147

DM6170

DM7185

DQS013

DQS131

DQS251

DQS370

DQS4131

DQS5148

DQS6169

DQS7188

DQS#011

DQS#129

DQS#249

DQS#368

DQS#4129

DQS#5146

DQS#6167

DQS#7186

DQ05

DQ17

DQ217

DQ319

DQ44

DQ56

DQ614

DQ716

DQ823

DQ925

DQ1035

DQ1137

DQ1220

DQ1322

DQ1436

DQ1538

DQ1643

DQ1745

DQ1855

DQ1957

DQ2044

DQ2146

DQ2256

DQ2358

DQ2461

DQ2563

DQ2673

DQ2775

DQ2862

DQ2964

DQ3074

DQ3176

DQ32123

DQ33125

DQ34135

DQ35137

DQ36124

DQ37126

DQ38134

DQ39136

DQ40141

DQ41143

DQ42151

DQ43153

DQ44140

DQ45142

DQ46152

DQ47154

DQ48157

DQ49159

DQ50173

DQ51175

DQ52158

DQ53160

DQ54174

DQ55176

DQ56179

DQ57181

DQ58189

DQ59191

DQ60180

DQ61182

DQ62192

DQ63194

J5P1A CON200_DDR2-SODIMM-STANJ5P1A CON200_DDR2-SODIMM-STAN

C6P20.1uF

.10%

C6P20.1uF

.10%

C4C72.2uF

.10%

C4C72.2uF

.10%

C5C32.2uF

.10%

C5C32.2uF

.10%

www.laptop-schematics

.com

Page 14: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V3.3M_DIMM1

M_B_DQ63

M_B_DQ57

M_B_DQ14

M_B_DQ7

M_B_DM7

M_B_DM1

SA0_DIM1

M_B_A13

M_B_A4

M_B_DQ31

M_B_DQ20

M_B_DQS5

M_B_DQ15

M_B_DQ13

M_B_DQ5M_B_DQ4

M_B_DQS#4

M_B_DQS6

M_B_A6

M_B_DQ60M_B_DQ59

M_B_DQ55

SA1_DIM1

M_B_DQ51

M_B_DQ41

M_B_DQ37

M_B_DQ21

M_B_DQ1

M_B_DM3

M_B_A0

M_B_DQ54

M_B_DQ48

M_B_DQ29

M_B_DQ11

M_B_DQS#2

M_B_DQS4

M_B_DM2

M_B_DM0

M_B_A3

M_B_DQ42

M_B_DQ19

M_B_DQS0

M_B_DQ58

M_B_DQ47

M_B_DQ45

M_B_DQ39

M_B_DQ17

M_B_DQ8

M_B_DQS3

M_B_DQ49

M_B_DQ34

M_B_DQ30

M_B_DQS#6

M_B_A12

M_B_DQ36

M_B_DQ33

M_B_DQ25

M_B_DQ22

M_B_DQS#3

M_B_DQS#0

M_B_DM6M_B_DM5

M_B_DQ56

M_B_DQ32

M_B_DQ6

M_B_DQ3

M_B_DQS#7

M_B_A8

M_B_A2

M_B_DQ35

M_B_DQ27

M_B_DQ23

M_B_DQ18

M_B_DQ16

M_B_DQ10

M_B_DQS2

M_B_A7

M_B_DQ62M_B_DQ61

M_B_DQ2

M_B_A10M_B_A9

M_B_DQ24

M_B_DQS1

M_B_DM4

M_B_DQ53M_B_DQ52

M_B_DQ46

M_B_DQ40

M_B_DQ12

M_B_DQ0

M_B_DQS#1

M_B_A1

M_B_DQ50

M_B_DQ43

M_B_DQ28

M_B_DQ9

M_B_DQS7

M_B_DQ44

M_B_DQ38

M_B_DQ26

M_B_DQS#5

M_B_A11

M_B_A5

M_B_A14

M_B_DQ[63:0] 8

M_B_DQS#[7:0]8

M_B_DQS[7:0]8

+V1.8_DIMM1

+V1.8_DIMM1

+V1.8_DIMM1

+V1.89,10,13,46,48,55,57

+V3.3M13,15,23,35,55,57

+V3.3M13,15,23,35,55,57

M_B_WE#8,15

M_B_BS18,15

SMB_CLK_M213,15,23

M_CS#27,15

SMB_DATA_M213,15,23

M_B_BS28,15

M_ODT27,15

M_CLK_DDR#47

M_B_CAS#8,15

M_CKE37,15

M_B_RAS#8,15

M_CLK_DDR37

M_ODT37,15

M_B_DM[7:0]8

M_CLK_DDR#37

M_B_BS08,15

M_CS#37,15

M_CKE47,15

M_CLK_DDR47

M_VREF_DIMM148

M_B_A[14:0]8,15

TS#_DIMM0_17,13

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 SODIMM 1

A

14 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 SODIMM 1

A

14 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 SODIMM 1

A

14 58Tuesday, August 28, 2007

SO-DIMM1 is placed farther fromthe GMCH than SO-DIMM0

Layout Note: Place these Caps near SO-DIMM1.

Layout Note: Place these Caps near SO-DIMM1.

Note: SO-DIMM1 SPD Address is 0xA4SO-DIMM1 TS Address is 0x34

C5B5330uF20%

C5B5330uF20%

C4B172.2uF

.10%

C4B172.2uF

.10%

R5B6 0.0021%

R5B6 0.0021%

C6N112.2uF

.10%

C6N112.2uF

.10%

R4B23 0.022R4B23 0.022

C4B230.1uF

.10%

C4B230.1uF

.10%

C5B42.2uF

.10%

C5B42.2uF

.10%

C4B182.2uF

.10%

C4B182.2uF

.10%

C6N100.1uF

.10%

C6N100.1uF

.10%R3B2310K

.

5%R3B2310K

.

5%

A0102

A1101

A2100

A399

A498

A597

A694

A792

A893

A991

A10/AP105

A1190

A1289

A13116

A1486

A1584

A16_BA285

BA0107

BA1106

S0#110

S1#115

ODT0114

ODT1119

CK030

CK0#32

CK1164

CK1#166

CKE079

CKE180

CAS#113

RAS#108

WE#109

SA0198

SA1200

SCL197

SDA195

DM010

DM126

DM252

DM367

DM4130

DM5147

DM6170

DM7185

DQS013

DQS131

DQS251

DQS370

DQS4131

DQS5148

DQS6169

DQS7188

DQS#011

DQS#129

DQS#249

DQS#368

DQS#4129

DQS#5146

DQS#6167

DQS#7186

DQ05

DQ17

DQ217

DQ319

DQ44

DQ56

DQ614

DQ716

DQ823

DQ925

DQ1035

DQ1137

DQ1220

DQ1322

DQ1436

DQ1538

DQ1643

DQ1745

DQ1855

DQ1957

DQ2044

DQ2146

DQ2256

DQ2358

DQ2461

DQ2563

DQ2673

DQ2775

DQ2862

DQ2964

DQ3074

DQ3176

DQ32123

DQ33125

DQ34135

DQ35137

DQ36124

DQ37126

DQ38134

DQ39136

DQ40141

DQ41143

DQ42151

DQ43153

DQ44140

DQ45142

DQ46152

DQ47154

DQ48157

DQ49159

DQ50173

DQ51175

DQ52158

DQ53160

DQ54174

DQ55176

DQ56179

DQ57181

DQ58189

DQ59191

DQ60180

DQ61182

DQ62192

DQ63194

J5N1A CON200_DDR2-SODIMM-REVJ5N1A CON200_DDR2-SODIMM-REV

C4B200.1uF

.10%

C4B200.1uF

.10%

C3B80.1uF

.10%

C3B80.1uF

.10%

VDD3117

VDD496

VDD595

VDD6118

VDD781

VDD882

VDD987

VDD10103

VDD1188

VDD12104

VDDSPD199

NC183

NC2120

EVENT#50

NC469

NCTEST163

VREF1

VSS147

VSS2133

VSS3183

VSS477

VSS512

VSS648

VSS7184

VSS878

VSS971

VSS1072

VSS11121

VSS12122

VSS13196

VSS14193

VSS158

VSS1618

VSS1724

VSS1841

VSS1953

VSS2042

VSS2154

VSS2259

VSS2365

VSS2460

VSS2566

VSS26127

VSS27139

VSS28128

VSS29145

VSS30165

VSS31171

VSS32172

VSS33177

VSS34187

VSS35178

VSS36190

VSS379

VSS3821

VSS3933

VSS40155

VSS4134

VSS42132

VSS43144

VSS44156

VSS45168

VSS462

VSS473

VSS4815

VSS4927

VSS5039

VSS51149

VSS52161

VSS5328

VSS5440

VSS55138

VSS56150

VSS57162

VDD1112

VDD2111

GND1202

GND0201

J5N1B CON200_DDR2-SODIMM-REVJ5N1B CON200_DDR2-SODIMM-REV

C3B92.2uF

.10%

C3B92.2uF

.10%

C4B212.2uF

.10%

C4B212.2uF

.10%

C4B220.1uF

.10%

C4B220.1uF

.10%

R4B2410K

.

5%

R4B2410K

.

5%

C5B62.2uF

.10%

C5B62.2uF

.10%

C4B190.1uF

.10%

C4B190.1uF

.10%

www.laptop-schematics

.com

Page 15: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_A14

M_A_A11

M_B_A6

M_A_A13

M_B_A2

M_A_A3

M_A_A6

M_B_A11

M_A_A9

M_B_A1

M_A_A12

M_A_A2

M_B_A3

M_A_A1

M_A_A5

M_B_A4

M_B_A9

M_A_A4

M_A_A10

M_A_A0

M_B_A7

M_A_A7

M_B_A8

M_B_A10

M_B_A0

M_A_A8

M_B_A5

M_B_A12

PM_EXTTS#0_D

PM_EXTTS#1_D

DDR_THERM1

DDR_THERM2

M_B_A13

M_A_A14

TP_GTL2005_JTAG_B1

GTL2005_JTAG_REF2GTL2005_JTAG_DIR2

ME_JTAG_TDO_BUFFER_R

GTL2005_JTAG_A2GTL2005_JTAG_A3

GTL2005_JTAG_A1

TP_GTL2005_JTAG_B3TP_GTL2005_JTAG_B2

ME_JTAG_TDO_BUFFER

MCH_TDI_R

ME_JTAG_TDO_BUFFER

MCH_TCK_R

MCH_TMS_R

ME_JTAG_TDI_BUFFERME_JTAG_TCK_BUFFER

ME_JTAG_TMS_BUFFERGTL2005_JTAG_REF

GTL2005_JTAG_DIR1 ME_JTAG_TCK_BUFFER

GTL2005_JTAG_B3

ME_JTAG_TDI_BUFFER

TP_GTL2005_JTAG_A3ME_JTAG_TMS_BUFFER

SMB_CLK_M2 13,14,23

SMB_DATA_M2 13,14,23

+V3.3M 13,14,23,35,55,57

+V0.9 46,55

+V0.9 46,55

M_A_A[14:0] 8,13

M_B_A[14:0] 8,14

M_CKE4 7,14

M_CKE1 7,13M_CKE3 7,14

M_CKE0 7,13

M_CS#0 7,13

M_CS#2 7,14M_CS#1 7,13

M_CS#3 7,14

M_ODT0 7,13

M_ODT2 7,14M_ODT1 7,13

M_ODT3 7,14

M_A_BS1 8,13M_A_BS2 8,13

M_A_BS0 8,13

M_B_BS0 8,14

M_B_BS2 8,14M_B_BS1 8,14

M_A_WE# 8,13

M_A_RAS# 8,13M_A_CAS# 8,13

M_B_RAS# 8,14M_B_CAS# 8,14M_B_WE# 8,14

PM_EXTTS#0_DIMM0_1 13,40

PM_EXTTS#1_R7

+V1.05M9,10,35,47,55+V3.3M13,14,23,35,55,57

+V3.3M13,14,23,35,55,57

+V3.3M13,14,23,35,55,57

+V3.3M13,14,23,35,55,57

MCH_TDO7

MCH_TCK7MCH_TDI7

MCH_TMS7

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 TERMINATION, THERMAL SENSOR AND ME JTAG

A

15 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 TERMINATION, THERMAL SENSOR AND ME JTAG

A

15 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DDR2 TERMINATION, THERMAL SENSOR AND ME JTAG

A

15 58Tuesday, August 28, 2007

Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9

On Board DDR2 Thermal SensorLayout Note:Place Q5N2under DIMM0

Layout Note:Place U5P1under DIMM1

MCH_RSVD_10 JTAG_TCKMCH_RSVD_11 JTAG_TDIMCH_RSVD_12 JTAG_TDOMCH_RSVD_13 JTAG_TMS

Voltage Buffer Translator for MCH ME JTAG

R4B25 56R4B25 56

C4B250.1uF

.10%

C4B250.1uF

.10%

C5C20.1uF

.10%

C5C20.1uF

.10%

R6

M3

10K

R6

M3

10K

R4B15 56R4B15 56

R4C10 56R4C10 56

C4C150.1uF

.10%

C4C150.1uF

.10%

R5P60

NO_STUFF

R5P60

NO_STUFF

R6A1210K

.

R6A1210K

.

C6A10.1uF20%

C6A10.1uF20%

R4C15 56R4C15 56

R4B33 56R4B33 56

C4B90.1uF

.10%

C4B90.1uF

.10%

R6

A6

1K

.

R6

A6

1K

.

R4C19 56R4C19 56

R4B13 56R4B13 56

C4C10.1uF

.10%

C4C10.1uF

.10%

R6A3806

.

1%

R6A3806

.

1%

R4B19 56R4B19 56

C4B150.1uF

.10%

C4B150.1uF

.10%

R4B12 56R4B12 56

DIR1

A02

A13

GTLREF4

A25

A36

GND17

GND28

B39

B210

GND311

B112

B013

VCC14

U6M1

GTL2005

U6M1

GTL2005

R6M1210K

NO_STUFF

R6M1210K

NO_STUFF

R4C7 56R4C7 56

R4B22 56R4B22 56

R4C3 56R4C3 56

R5C5 56R5C5 56

R4C18 56R4C18 56

R4C9 56R4C9 56

R6

A2

1K

.

R6

A2

1K

.

VDD1

D-3

THERM#4

GND5

SCLK8

SDATA7

ALERT#6

D+2

U5P1

ADM1032AR

U5P1

ADM1032AR

R4B26 56R4B26 56

C6M20.1uF20%

C6M20.1uF20%

C4B100.1uF

.10%

C4B100.1uF

.10%

R4B18 56R4B18 56

R6

A7

1K

.

5%

R6

A7

1K

.

5%

R5C2 56R5C2 56

R5B7 56R5B7 56

R4B27 56R4B27 56

R4B21 56R4B21 56

R4B16 56R4B16 56

DIR1

A02

A13

GTLREF4

A25

A36

GND17

GND28

B39

B210

GND311

B112

B013

VCC14

U6M2

GTL2005

U6M2

GTL2005

R4B20 56R4B20 56

R4C12 56R4C12 56

R6

A5

1K

.

R6

A5

1K

.

R4C24 56R4C24 56

R6M11 22R6M11 22

C4B120.1uF

.10%

C4B120.1uF

.10%

R6M2 100R6M2 100

R4C8 56R4C8 56R4C2 56R4C2 56

R4B34 56R4B34 56

C4B240.1uF

.10%

C4B240.1uF

.10%

R4B17 56R4B17 56

C6M70.1uF20%

C6M70.1uF20%

C4B280.1uF

.10%

C4B280.1uF

.10%

R4B11 56R4B11 56

R5C1 56R5C1 56

C4B110.1uF

.10%

C4B110.1uF

.10%

R6M42.37K1%

R6M42.37K1%

R4C6 56R4C6 56

R6

M9

10K

NO_STUFF

R6

M9

10K

NO_STUFF

R4B28 56R4B28 56

12

6543

J5A2

RJ-11_JACK_Vertical-Mount

.

J5A2

RJ-11_JACK_Vertical-Mount

.

C4B140.1uF

.10%

C4B140.1uF

.10%

R5C4 56R5C4 56

C6M6220PFC6M6220PF

R4C11 56R4C11 56

C4C30.1uF

.10%

C4C30.1uF

.10%

C4C140.1uF

.10%

C4C140.1uF

.10%

R4C21 56R4C21 56

R6A19

10K5%

R6A19

10K5%

C4B270.1uF

.10%

C4B270.1uF

.10%

R6A1310KNO_STUFF

R6A1310KNO_STUFF

C4C40.1uF

.10%

C4C40.1uF

.10%

R6

A1

11

K

.

5%

R6

A1

11

K

.

5%

C4B290.1uF

.10%

C4B290.1uF

.10%

C4C60.1uF

.10%

C4C60.1uF

.10%

R6

M5

10KR

6M

510K

1

3

2

Q5N22N3904

Q5N22N3904

C4C20.1uF

.10%

C4C20.1uF

.10%

R4C16 56R4C16 56

R6A17

10K5%

R6A17

10K5%

R5B5 56R5B5 56

R4C17 56R4C17 56

R4C23 56R4C23 56

C5C60.1uF

.10%

C5C60.1uF

.10%

R6M101K

.5%

R6M101K

.5%

R4B14 56R4B14 56

R6M6 100R6M6 100

R4C20 56R4C20 56

R6M11K

.5%

R6M11K

.5%

C4B260.1uF

.10%

C4B260.1uF

.10%

R4C4 56R4C4 56

R5B8 56R5B8 56

R4B31 56R4B31 56

R6A18

10K NO_STUFF5%

R6A18

10K NO_STUFF5%

R4C14 56R4C14 56

R5P40

.

R5P40

.

C6M50.1uFC6M50.1uF

C4C160.1uF

.10%

C4C160.1uF

.10%

R6

A9

1K

.

5%

R6

A9

1K

.

5%

R6A83.24K

.1%

R6A83.24K

.1%

R4C13 56R4C13 56

R4C22 56R4C22 56

C5B30.1uF

.10%

C5B30.1uF

.10%

R4B30 56R4B30 56

C4C170.1uF

.10%

C4C170.1uF

.10%

R4C5 56R4C5 56

R4B32 56R4B32 56

C4C50.1uF

.10%

C4C50.1uF

.10%

R4B35 56R4B35 56

C4B160.1uF

.10%

C4B160.1uF

.10%

R6A410K

NO_STUFF

R6A410K

NO_STUFF

R4B29 56R4B29 56

R5B4 56R5B4 56

R6M8 100R6M8 100

C4C180.1uF

.10%

C4C180.1uF

.10%

R6M710K

.

R6M710K

.

R6

A1

02

2.1

KR

6A

10

22

.1K

www.laptop-schematics

.com

Page 16: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CRT_Q_BLUE

CRT_Q_HSYNC

CRT_L2_RED

DDC_GATE

CRT_Q_VSYNC

CRT_Q_RED

CRT_Q_GREEN CRT_L2_GREEN

CRT_L2_BLUE

+V

5S

_L

_D

AC

CRT_L2_RED

CRT_L2_GREENCRT_Q_VSYNC

CRT_L2_BLUE

CRT_Q_HSYNC

CRT_Q_GREENCRT_Q_BLUECRT_Q_VSYNCCRT_Q_HSYNC

CRT_Q_RED

CRT_L_BLUE

DOCK_CRT_EN#_R CRT_EN#

CRT_DDC_CLK_ISO

DOCK_CRT_EN#_R

CRT_DDC_DATA_ISO

CRT_L_RED

CRT_L_GREEN

DOCK_CRT_EN#_R

DDC_SRC

CRT_DDC_DATA_ISO

CRT_DDC_CLK_ISO

CRT_DDC_DATA_DOCK44

CRT_DDC_CLK_DOCK44

+V3.3S

+V3.3S5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S

+V3.3S

+V3.3S5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+VBATS19,27,30,31,55,57 +V5S_F_DAC

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

CRT_DDC_DATA_MCH7

+V3.3S

+V3.3S

CRT_DDC_CLK_MCH7

CRT_BLUE7CRT_GREEN7

CRT_HSYNC7

CRT_RED7

CRT_VSYNC7

DOCK_CRT_EN#41

CRT_BLUE_DOCK 44CRT_GRN_DOCK 44CRT_RED_DOCK 44

CRT_HSYNC_DOCK 44CRT_VSYNC_DOCK 44

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CRT

A

16 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CRT

A

16 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CRT

A

16 58Tuesday, August 28, 2007

Note:For video bandwidths > 200MHz:C3B1, C3A4, C2B1, C2A5, C2B2, C2N1 = 3.3pFC3M3, C2A4, C2A6 = No_StuffFB3A1, FB2A4, FB2B1 = Short

R2M32.2K

.

R2M32.2K

.

C3M310pF5%.

C3M310pF5%.

SEL12

Y_A2

I_A024

Y_B5

Y_C6

Y_D8

Y_E11

GND27

GND310

GND420

VDD24

VDD39

VDD419

I_B022

I_C018

I_D017

I_E014

I_A123

I_B121

I_C116

I_D115

I_E113

GND13

VDD11

U6E4

PI3V512QE

U6E4

PI3V512QE

C3M433pF5%NO_STUFF

C3M433pF5%NO_STUFF

C6T60.1uF20%

C6T60.1uF20%

C6T40.1uF20%

C6T40.1uF20%

R6T510K

NO_STUFF

R6T510K

NO_STUFF

C6T30.1uF20%

C6T30.1uF20%

C2B210pF5%.

C2B210pF5%.

C3A422pF5%.

C3A422pF5%.

C2A522pF5%.

C2A522pF5%.

R2B11501%

R2B11501%

C6T20.1uF20%

C6T20.1uF20%

C3B110pF5%.

C3B110pF5%.

C6T50.1uF20%

C6T50.1uF20%

3

1

2

Q2A1BSS138Q2A1BSS138

R2N11KR2N11K

FB3B1

47ohm@100MHz

FB3B1

47ohm@100MHz

21

Clamping-Diode

CR2N1

Clamping-Diode

CR2N1

C2B110pF5%.

C2B110pF5%.

FB3A1

47ohm@100MHz

FB3A1

47ohm@100MHz

C2N30.1uF20%

C2N30.1uF20%

R6T41KNO_STUFF

R6T41KNO_STUFF

R6T22.2KR6T22.2K

1 2+F2A1

1.1A

+F2A1

1.1A

FB3B2

47ohm@100MHz

FB3B2

47ohm@100MHz

C6T70.1uF20%

C6T70.1uF20%

C6E90.1uF20%

C6E90.1uF20%

R2M42.2K

.

R2M42.2K

.

R6T12.2KR6T12.2K

I/O11

I/O22

I/O33

I/O810

I/O79

I/O67

I/O56

I/O44

VN

5V

P8

U2M2

ESD DIODE ARRAY

U2M2

ESD DIODE ARRAY

C2A610pF5%.

C2A610pF5%.

FB2B2

47ohm@100MHz

FB2B2

47ohm@100MHz

19141813171216111510 20

21

22

23

24

GND1REDGND2GRNGND3BLUVCCNC1GND4GND5 CLK

VSYNC

HSYNC

DATA

NC2

J2A2B

2IN1

GND1REDGND2GRNGND3BLUVCCNC1GND4GND5 CLK

VSYNC

HSYNC

DATA

NC2

J2A2B

2IN1

R3B21501%

R3B21501%

2 4

5

3

U6T1

INVERTER

U6T1

INVERTER

1OE#1

1A2

1B3

GND4

VCC8

2OE#7

2B6

2A5

U6E3

SN74CBTD3306C

U6E3

SN74CBTD3306C

R6T30

.

R6T30

.

C2N122pF5%.

C2N122pF5%.

1OE#1

1A2

1B3

GND4

VCC8

2OE#7

2B6

2A5

U6E1

SN74CBTD3306C

U6E1

SN74CBTD3306C

FB2B1

47ohm@100MHz

FB2B1

47ohm@100MHz

C3M533pF5%NO_STUFF

C3M533pF5%NO_STUFF

FB2M150OHMFB2M150OHM

21

Clamping-Diode

CR2M1

Clamping-Diode

CR2M1

R2N2100KR2N2100K

C2A410pF5%.

C2A410pF5%.

FB2A4

47ohm@100MHz

FB2A4

47ohm@100MHz

R3B11501%

R3B11501%

www.laptop-schematics

.com

Page 17: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

L_BKLTSEL1#

L_

VD

DE

N#

L_VDDEN_D#

L_BRIGHTNESS

+VDD_VDL_L

DBL_CLK

+VDD_VDL_L

+VDD_VDL

TP_+V2.5

ALS_DATA40ALS_CLK40

L_BKLTSEL0#38L_BKLT_CTRL7

L_BKLT_EN7

LVDS_DDC_CLK7LVDS_DDC_DATA7

L_CTRL_DATA 7,20

L_CTRL_CLK7,20

LVDS_VDD_EN7

L_BKLTSEL1# 38

LVDSA_DATA#07LVDSA_DATA07

LVDSA_DATA#17LVDSA_DATA17

LVDSA_DATA27LVDSA_DATA#27

LVDSA_DATA#37LVDSA_DATA37

LVDSA_CLK#7LVDSA_CLK7

LVDSB_DATA07LVDSB_DATA#07

LVDSB_DATA#17LVDSB_DATA17

LVDSB_DATA#27LVDSB_DATA27

LVDSB_DATA37LVDSB_DATA#37

LVDSB_CLK7LVDSB_CLK#7

ALS_INTR#40

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S_LVDS_DDC

+V5S_LVDS_BKLT

+V5S_LVDS_BKLT

+VCC_LVDS_BKLT+V3.3S_LVDS_DDC

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+VBAT49,53,55,56,57

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

+VCC_LVDS_BKLT

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LVDS

A

17 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LVDS

A

17 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LVDS

A

17 58Tuesday, August 28, 2007

GM_CLK_D Support

GM_Data_D Support

GMCH_PWM Support

LVDS Panel BacklightBIOS Note: Disable both BKLTSELlines before enabling one.

For 2.5V panel support, connect an externalsource to net TP_+V2.5.

+VDD_VDL

STUFF R6V2NO_STUFF R6U26, R6V4

+V3.3S(DEFAULT)

+V5S STUFF R6U26NO_STUFF R6V2, R6V4

TP_+V2.5 STUFF R6V4NO_STUFF R6V2, R6U26

STRAPPING

1 2

R6V40.002

NO_STUFF

R6V40.002

NO_STUFF

1

32

SI2

30

7D

S

Q6U3

SI2

30

7D

S

Q6U3

R6U190.0021%

R6U190.0021%

C6U100.1uF20%

C6U100.1uF20%

R6U1510K5%

R6U1510K5%

3

1

2

Q6F2BSS138Q6F2BSS138

C6U10.1uF20%

C6U10.1uF20%

R6U252.2K5%

R6U252.2K5%

OE#1

A2

GND3

Y4

VCC5

U6F1

74CBTLV1G125

U6F1

74CBTLV1G125

R6U18100KR6U18100K

C6F522UFC6F522UF

VDD_BLI1

VSS_BLI2

VSS_DBC3

VDD_DBC4

DBL_CLK5

DBL_DATA6

ENA_BL7

NC18

VDD_ALS9

VSS_ALS10

ALS_CLK11

ALS_DATA12

ALS_INTR13

NC214

VSS_VDL15

VDD_VDL116

VDD_VDL217

VDD_VCL18

RSVD19

VCL_CLK20

VCL_DATA21

A0M22

A0P23

VSS_SHIELD124

A1M25

A1P26

VSS_SHIELD227

A2M28

A2P29

VSS_SHIELD330

VDL_CLKAM34

VDL_CLKAP35

VSS36

B0M37

B0P38

VSS_SHIELD433

B1M40

B1P41

VSS_SHIELD539

B2M43

B2P44

VSS_SHIELD642

VDL_CLKBM49

VDL_CLKBP50

A3M31

A3P32

VSS_SHIELD745

B3M46

VSS_SHIELD848

B3P47

J6F1

LVDS,CONN50

J6F1

LVDS,CONN50

R6U281MR6U281M

R6U200.0021%

R6U200.0021%

R6V2 0.0021%

R6V2 0.0021%

C6F60.1uF10%

C6F60.1uF10%

C7T190.1uF20%

C7T190.1uF20%

R7U210K5%

R7U210K5%

R6U23 100KR6U23 100K

C6V11000pF10%

C6V11000pF10%

R6V1100KR6V1100K

C6U90.1uF20%

C6U90.1uF20%

R6U242.2K5%

R6U242.2K5%

TP6G1 NO_STUFFTP6G1 NO_STUFF

OE1#1

1A2

1B3

GND4

2A5

2B6

OE2#7

VCC8

U7E6

74CBT3306

U7E6

74CBT3306

C6U20.1uF20%

C6U20.1uF20%

R6F150.0021%

R6F150.0021%

12

R6U260.002

NO_STUFF

R6U260.002

NO_STUFF

www.laptop-schematics

.com

Page 18: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DACB_L

DACC DACC_L

DACA_L

DLINE2DLINE3

DLINE1

DACA

DACBDACB

DACA

DACC

TV_DCONSEL1_LVLTV_DCONSEL0_LVL

I2C

_R

ST

#

DACA_LDACB_LDACC_L

DOCK_TV_EN#

TV_DCONSEL1_LVL

TV_DCONSEL0_LVL

TV_EN#

TV_DCONSEL1_DOCK44

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

+V5S

+V5S

TV_DCONSEL1_MCH7

+V3.3S

+V3.3S

TVB_DAC7

TVA_DAC7

TVC_DAC7

DOCK_TV_EN#41

TV_DCONSEL0_MCH7

TV_DCONSEL0_DOCK44

TV_DACA_OUT_DOCK 44

TV_DACB_OUT_DOCK 44

TV_DACC_OUT_DOCK 44

DLINE3_IODLINE2_IODLINE1_IO

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

DLINE1_IODLINE2_IODLINE3_IO

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

TV

A

18 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

TV

A

18 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

TV

A

18 58Tuesday, August 28, 2007

Layout Note:Place 150 Ohm terminationresistors, ferrite beads andcapicators close toconnector

Note:Pins 12 & 14 are shortedinside D-Connector plug.

Note:ESD Diode Array for the TVDAC A, DAC B, DAC C signalslocated on CRT page.

1125p (1080)

5V

5V

0 1 0b

0V2.2V

4:35V

2.2V

16:9

525i (480)0 0 1b

5V

0 0 0bLine3

4:30V

0V5V

0V

0V

4:3

Letterbox

0V4:3

Line2

0V525p (480)

4:3

0V

5V

1125i (1080)

4:35V

0V

525i (480)

16:9

16:9

X 1 0b

5V

IO2 IO1 IO0

Letterbox 2.2V

Aspect RatioPort Value

0 1 Xb

1125i (1080)

5V

0V

0V

0 0 Xb

Voltage

5V

16:9

1 1 0b

4:3

0V

X 1 1b

1 1 1b

1 0 0b750p (720)

0 1 1b

Line1

5V

1 0 1b

525p (480)

0V

2.2V5V

5V

5V

525p (480)

1125p (1080)

Format0V

525i (480)

750p (720) 0V

5V

0V16:9

5V

TV-OUT DAC Channel Definition

Channel A (DACA)

Channel C (DACC)

Composite Video S-Video Component VideoCVBS Signal

Channel B(DACB) Luminance (Y)Chrominance (C)

Chrominance (Pb)

Chrominance (Pr)Luminance (Y)X

X

X

R2M1 10KR2M1 10K

C2A21.0uF10%

C2A21.0uF10%

12

C2A35.6pF8.9%.

C2A35.6pF8.9%.

C2M10.1uF20%

C2M10.1uF20%

1OE#1

1A2

1B3

GND4

VCC8

2OE#7

2B6

2A5

U6D2

SN74CBTD3306C

U6D2

SN74CBTD3306C

C6T10.1uF20%

C6T10.1uF20%

R2M21501%

R2M21501%

C6N40.1uF20%

C6N40.1uF20%

I/O11

I/O22

I/O33

I/O810

I/O79

I/O67

I/O56

I/O44

VN

5V

P8

U2A2

ESD DIODE ARRAY

U2A2

ESD DIODE ARRAY

IO_01

IO_12

IO_23

IO_34

VSS5

RESET#6

INT#7

SCL8

SDA9

VDD10

U2A1

I2C - PCA9537

U2A1

I2C - PCA9537

FB2A1

150ohm@100MHz

FB2A1

150ohm@100MHz

C6R10.1uF20%

C6R10.1uF20%

C2M20.1uF20%

C2M20.1uF20%

R2A4 10KR2A4 10K

C6N80.1uF20%

C6N80.1uF20%

R6D52.2K

5%

R6D52.2K

5%

12

C1A25.6pF8.9%.

C1A25.6pF8.9%.

R2A610K1%

R2A610K1%

1234567

891011121314

J2A1

CON14_DCONN-CP4120

J2A1

CON14_DCONN-CP4120

12

C2A15.6pF8.9%.

C2A15.6pF8.9%.

R1M11501%

R1M11501%

C6D80.1uF20%

C6D80.1uF20%

FB1A1

150ohm@100MHz

FB1A1

150ohm@100MHz

R1M21501%

R1M21501%

R6D62.2K

5%

.R6D62.2K

5%

.

R2A15.90KR2A15.90K

FB2A2

150ohm@100MHz

FB2A2

150ohm@100MHz

1OE#1

1A2

1B3

GND4

VCC8

2OE#7

2B6

2A5

U6D1

SN74CBTD3306C

U6D1

SN74CBTD3306C

R6D72.2K

5%

R6D72.2K

5%

SEL12

Y_A2

I_A024

Y_B5

Y_C6

Y_D8

Y_E11

GND27

GND310

GND420

VDD24

VDD39

VDD419

I_B022

I_C018

I_D017

I_E014

I_A123

I_B121

I_C116

I_D115

I_E113

GND13

VDD11

U6B1

PI3V512QE

U6B1

PI3V512QE

R2A54.7KR2A54.7K

I/O11

I/O22

I/O33

I/O810

I/O79

I/O67

I/O56

I/O44

VN

5V

P8

U2M1

ESD DIODE ARRAY

U2M1

ESD DIODE ARRAY

C6N60.1uF20%

C6N60.1uF20%

C6N50.1uF20%

C6N50.1uF20%

R2A2 10KR2A2 10K

12

C1A15.6pF8.9%.

C1A15.6pF8.9%.

R2A75.90KR2A75.90K

R2A34.7KR2A34.7K

R6D42.2K

5%

.R6D42.2K

5%

.

12

C1A45.6pF8.9%.

C1A45.6pF8.9%.

2 4

5

3

U6R1

INVERTER

U6R1

INVERTER

12

C1A35.6pF8.9%.

C1A35.6pF8.9%.

www.laptop-schematics

.com

Page 19: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PEG_TX#13

PEG_RX#6

PEG_TX#15

PEG_RX0

PEG_RX#10

PEG_C_TX13

PEG_RX#13

PEG_RX1

PEG_TX#0

PEG_TX#2

PEG_RX#5

PEG_RX#8

PEG_C_TX0

PEG_RX#0

PEG_TX#4

PEG_C_TX#12

PEG_RX10

PEG_RX13

PEG_C_TX#11

PEG_C_TX5

PEG_RX#1

PEG_RX7

PEG_TX#6

PEG_TX#3

PEG_C_TX#8

PEG_C_TX11

PEG_C_TX#10

PEG_RX#14

PEG_RX#7

PEG_TX#11

PEG_RX9PEG_TX#9

PEG_C_TX14

PEG_C_TX#0

PEG_RX3

PEG_C_TX#9

PEG_C_TX12

PEG_TX#10

PEG_RX#9

PEG_C_TX#14

PEG_C_TX#15

PEG_RX#3

PEG_RX14

PEG_C_TX#13

PEG_C_TX#3

PEG_RX5

PEG_C_TX4

PEG_C_TX9

PEG_RX8

PEG_C_TX10

PEG_RX4

PEG_C_TX15

PEG_RX#2

PEG_C_TX#4

PEG_C_TX#5

PEG_TX#7

PEG_C_TX8

PEG_RX12

PEG_RX#15

PEG_C_TX#6

PEG_C_TX#7

PEG_C_TX#1

PEG_RX2

PEG_TX#8

PEG_C_TX#2

PEG_C_TX1

PEG_RX#12

PEG_C_TX7

PEG_TX#12

PEG_RX6

PEG_TX#14

PEG_RX15

PEG_C_TX2

PEG_RX#11PEG_RX11

PEG_RX#4

PEG_TX#1

PEG_C_TX6

PEG_SLT_RST#

PEG_TX2

PEG_TX11

PEG_TX9

PEG_TX14

PEG_TX15

PEG_TX12

PEG_TX0

PEG_TX1

PEG_TX8

PEG_TX6

PEG_TX3

PEG_TX4

PEG_TX7

PEG_TX13

PEG_C_TX3

PEG_TX10

PEG_TX#5PEG_TX5

SDVO_CTRLDATA7

SMB_DATA_S423,43

SDVO_CTRLCLK7

SMB_CLK_S423,43

+V3.327,32,39,41,42,43,55,57

+V3.3S_PEG23

+VBATS_PEG

+VBATS16,27,30,31,55,57

+V3.3A21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3S_PEG 23

+VBATS_PEG

+VBATS_PEG

+V3.3S5,7,10,12,13,16,17,18,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S_PEG23

+VBAT_S455,57

DDPC_CTRLCLK 7

CLK_PCIE_PEG 35PEG_TX[15:0]7PEG_TX#[15:0]7 CLK_PCIE_PEG# 35

PLT_GATED_RST# 41

PLT_RST# 7,22,25,26,38,41,57

MCH_CFG_207,12

PEG_RX#[15:0] 7

PCIE_WAKE#23,25,26,44

PEG_RX[15:0] 7

DDPC_CTRLDATA7

PEG_RSVD2

PEG_RSVD5

PEG_SLT_RST#

PEG_RSVD4

PEG_RSVD3

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCIE GRAPHICS

A

19 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCIE GRAPHICS

A

19 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCIE GRAPHICS

A

19 58Tuesday, August 28, 2007

For D3 HOT/ D3 ON: Stuff R6N5, R6P2, and R6N7,unstuff R6N9, R6C1 and R6N6.

C6D110.1uF

.10%

C6D110.1uF

.10%

C6E20.1uF

.10%

C6E20.1uF

.10%

C6D60.1uF

.10%

C6D60.1uF

.10%

C6D140.1uF

.10%

C6D140.1uF

.10%

C6E40.1uF

.10%

C6E40.1uF

.10%

R6N90.0021%

R6N90.0021%

C6D10.1uF

.10%

C6D10.1uF

.10%

C6D100.1uF

.10%

C6D100.1uF

.10%

C6D50.1uF

.10%

C6D50.1uF

.10%

C6C130.1uF

.10%

C6C130.1uF

.10%

C6C122uFC6C122uF

C6C140.1uF

.10%

C6C140.1uF

.10%

C6C100.1uF

.10%

C6C100.1uF

.10%

C6D40.1uF

.10%

C6D40.1uF

.10%

R6N60.002

NO_STUFF

1%

R6N60.002

NO_STUFF

1%

C6C30.1uF

.10%

C6C30.1uF

.10%

+12V1B1

+12V2B2

+12V3B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

+3.3V1B8

JTAG1B9

3.3VAUXB10

WAKE#B11

RSVD2B12

GND3B13

HSOP_0B14

HSON_0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

+12V4A2

+12V5A3

GND6A4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PWRGDA11

GND7A12

REFCLK+A13

REFCLK-A14

GND8A15

HSIP_0A16

HSIN_0A17

GND9A18

HSOP_1B19

HSON_1B20

GND10B21

GND11B22

HSOP_2B23

HSON_2B24

GND12B25

GND13B26

HSOP_3B27

HSON_3B28

GND14B29

RSVD3B30

PRSNT2#1B31

GND15B32

HSOP_4B33

HSON_4B34

GND22B35

GND23B36

HSOP_5B37

HSON_5B38

GND24B39

GND25B40

HSOP_6B41

HSON_6B42

GND26B43

GND27B44

HSOP_7B45

HSON_7B46

GND28B47

PRSNT2#2B48

GND29B49

HSOP_8B50

HSON_8B51

GND38B52

GND39B53

HSOP_9B54

HSON_9B55

GND40B56

GND41B57

HSOP_10B58

HSON_10B59

GND42B60

GND43B61

HSOP_11B62

HSON_11B63

GND44B64

GND45B65

HSOP_12B66

HSON_12B67

GND46B68

GND47B69

HSOP_13B70

HSON_13B71

GND48B72

GND49B73

HSOP_14B74

HSON_14B75

GND50B76

GND51B77

HSOP_15B78

HSON_15B79

GND52B80

PRSNT2#3B81

RSVD4B82

RSVD5A19

GND16A20

HSIP_1A21

HSIN_1A22

GND17A23

GND18A24

HSIP_2A25

HSIN_2A26

GND19A27

GND20A28

HSIP_3A29

HSIN_3A30

GND21A31

RSVD6A32

RSVD7A33

GND30A34

HSIP_4A35

HSIN_4A36

GND31A37

GND32A38

HSIP_5A39

HSIN_5A40

GND33A41

GND34A42

HSIP_6A43

HSIN_6A44

GND35A45

GND36A46

HSIP_7A47

HSIN_7A48

GND37A49

RSVD8A50

GND54A51

HSIP_8A52

HSIN_8A53

GND55A54

GND56A55

HSIP_9A56

HSIN_9A57

GND57A58

GND58A59

HSIP_10A60

HSIN_10A61

GND59A62

GND60A63

HSIP_11A64

HSIN_11A65

GND61A66

GND62A67

HSIP_12A68

HSIN_12A69

GND63A70

GND64A71

HSIP_13A72

HSIN_13A73

GND65A74

GND66A75

HSIP_14A76

HSIN_14A77

GND67A78

GND68A79

HSIP_15A80

HSIN_15A81

GND69A82

Key

J6B2

PCIE_X16

Key

J6B2

PCIE_X16

C6B90.1uF

.10%

C6B90.1uF

.10%

C6D90.1uF

.10%

C6D90.1uF

.10%

C6D70.1uF

.10%

C6D70.1uF

.10%

C6E70.1uF

.10%

C6E70.1uF

.10%

C6C60.1uF

.10%

C6C60.1uF

.10%

C6C80.1uF

.10%

C6C80.1uF

.10%

C6B622UFC6B622UF

C6A422UFC6A422UF

C6C40.1uF

.10%

C6C40.1uF

.10%

C6E80.1uF

.10%

C6E80.1uF

.10%

C6B50.1uF10%.

C6B50.1uF10%.

C6D120.1uF

.10%

C6D120.1uF

.10%

C6E10.1uF

.10%

C6E10.1uF

.10%

12

+

C6B11100uF

+

C6B11100uF

C6E60.1uF

.10%

C6E60.1uF

.10%

C6B322UFC6B322UF

R6P20.002

NO_STUFF

1%

R6P20.002

NO_STUFF

1%

C6C70.1uF

.10%

C6C70.1uF

.10%

C6E30.1uF

.10%

C6E30.1uF

.10%

R6N80

NO_STUFF

R6N80

NO_STUFF

C6C110.1uF

.10%

C6C110.1uF

.10%

R6N70

.

R6N70

.

C6B120.1uF

.10%

C6B120.1uF

.10%

C6B80.1uF

.10%

C6B80.1uF

.10%

C6C90.1uF

.10%

C6C90.1uF

.10%

C6E50.1uF

.10%

C6E50.1uF

.10%

C6N90.1uF10%.

C6N90.1uF10%.

C6C20.1uF

.10%

C6C20.1uF

.10%

C6D130.1uF

.10%

C6D130.1uF

.10%

C6D20.1uF

.10%

C6D20.1uF

.10%

C6C50.1uF

.10%

C6C50.1uF

.10%

C6B122UFC6B122UF

12

R6C1

0.002

.

R6C1

0.002

.

www.laptop-schematics

.com

Page 20: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDP_OBS3_R

RST_SNS1

+V1.05S_CPU3,4,35,39,43,52,54 +V3.3S+V1.05S_CPU3,4,35,39,43,52,54

XDP_OBS5

XDP_OBS11

XDP_OBS12

XDP_OBS6

L_CTRL_DATA7,17

XDP_OBS16

XDP_OBS9

XDP_OBS7

XDP_OBS8

XDP_OBS10

XDP_OBS14XDP_OBS4

XDP_OBS3

XDP_BPM#43

XDP_OBS13

XDP_OBS15

XDP_OBS17

XDP_BPM#03

XDP_BPM#53

XDP_OBS035

XDP_OBS235

XDP_OBS135

XDP_OBS20 CLK_XDP# 35

L_CTRL_CLK7,17

CLK_XDP 35

CLK_PCIE_XDP_3GPLL35CLK_PCIE_XDP_3GPLL#35

H_PWRGD_XDP3

XDP_TDO 3

H_CPURST# 3,6

XDP_TRST# 3

XDP_TMS 3XDP_TDI 3

XDP_TCK3

XDP_DBRESET# 3

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

XDP

A

20 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

XDP

A

20 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

XDP

A

20 58Tuesday, August 28, 2007

XDP

CAD NOTE:

Layout note: R2U5 shouldconnect to H_CPURST# withno stub.

Place the XDP connector on theprimary side of the CRB and placeall components near theconnector.

GND38

GND514

GND01

OBSFN_A03

GND12

GND27

OBSFN_A15

OBSDATA_A09

OBSDATA_A111

OBSDATA_A215

OBSDATA_A317

GND413

GND619

GND825

GND1031

OBSDATA_B233

OBSDATA_B335

OBSDATA_B027

OBSDATA_B129

OBSFN_B021

OBSFN_B123

HOOK347

GND1237

PWRGOOD/HOOK039

HOOK141

VCC_OBS_AB43

HOOK245

GND1449

SDA51

SCL53

TCK155

TCK057

GND1659

GND720

GND926

GND1338

GND1550

GND1760

GND1132

OBSFN_C04

OBSFN_C16

OBSFN_D022

OBSFN_D124

OBSDATA_C010

OBSDATA_C112

OBSDATA_C216

OBSDATA_C318

OBSDATA_D028

OBSDATA_D130

OBSDATA_D234

OBSDATA_D336

ITPCLK/HOOK440

ITPCLK#/HOOK542

VCC_OBS_CD44

RESET#/HOOK646

DBR#/HOOK748

TDO52

TRSTN54

TDI56

TMS58

J1F1

CONN60_ITP-XDP

J1F1

CONN60_ITP-XDP

R2U5100

.

5%R2U5

100

.

5%C1T30.1uF

.10%

C1T30.1uF

.10%

R1U10

NO_STUFF

R1U10

NO_STUFF

R1U20

.

R1U20

.

R1T454.91%

R1T454.91%

R1T51K

.5%

R1T51K

.5%C1T40.1uF

.10%

C1T40.1uF

.10%

R1T154.91%

R1T154.91%

www.laptop-schematics

.com

Page 21: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BAT

BAT_D

LED_R

ICH_INTVRMEN

RTC_RST#

RTC_X2

H_DPSLP#_R

SATA_RBIAS_PN

SATA_TXN1_C

SM_INTRUDER#

SATA_RXN0_C

SATA_RXP1_C

GLAN_COMP

H_THERMTRIP_R

H_SMI#_R

H_DPRSTP#_R

SATA_TXP0_C

HDA_SDOUT

SATA_TXP1_C

ICH_INTVRMEN

SATA_TXN0_C

RTC_X1

SATA_RXN1_C

SATA_RXP0_C

ICH_SATA_LED#

H_RCIN#

SATA_RXN4_CSATA_RXP4_CSATA_TXN4_C

SATA_RXN5_CSATA_RXP5_CSATA_TXN5_CSATA_TXP5_C

SATA_TXN5_C

SATA_RXN5_C

SATA_TXP4_C

SRTC_RST#

ICH_SATA_LED#

ICH_GPIO56

H_FERR#_R

SATA_RXP5_C

SATA_TXP5_C

ICH_GPIO56

ICH_TP3 23

ICH_TP8

LPC_AD0 38,40,43LPC_AD1 38,40,43LPC_AD2 38,40,43LPC_AD3 38,40,43

+V3.3S_1.5S_HDA_IO24,27,28

+V3.3A_RTC24

+V1.5S_PCIE_ICH22,24

+V3.3A_RTC24+V3.3A

+V3.3S

+V1.05S_ICH_IO24

+V1.05S_ICH_IO24

+V1.05S_ICH_IO24

+V3.3S5,7,10,12,13,16,17,18,19,20,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

GLAN_CLK33

LAN_RXD133LAN_RXD033

LAN_RXD233

H_RCIN# 40,43

H_A20GATE 40,43

H_FERR# 3

PM_THRMTRIP# 3,7

RTC_RST# 41

ICH_DRQ#0 38

SATA_RXN4_DOCK 44SATA_RXP4_DOCK 44

SATA_RXN4 31SATA_RXP4 31

SATA_RXN5 30SATA_RXP5 30

CLK_PCIE_SATA# 35CLK_PCIE_SATA 35

HDA_SDIN37,27

HDA_SDIN027

HDA_SDIN227HDA_SDIN127

SATA_RXN030SATA_RXP030

SATA_RXN131SATA_RXP131

ICH_DRQ#1 38

LAN_TXD233

LAN_TXD033

HDA_DOCK_RST#27,44HDA_DOCK_EN#27,41

LAN_RSTSYNC33

LAN_TXD133

H_STPCLK# 3,43

H_DPRSTP# 3,7,43

H_PWRGD 3,43

H_NMI 3,43

H_A20M# 3

H_INTR 3

H_IGNNE# 3

H_DPSLP# 3,43

H_SMI# 3,43

H_INIT# 3

SATA_TXP4_DOCK 44SATA_TXN4_DOCK 44

SATA_TXN4 31SATA_TXP4 31

SATA_TXN5 30SATA_TXP5 30

SATA_LED#56

HDA_SDOUT7,27

HDA_RST#7,27

HDA_BIT_CLK7,27HDA_SYNC7,27

SATA_TXP131SATA_TXN131

SATA_TXN030SATA_TXP030

LPC_FRAME# 38,40,43

+V3.3A19,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (1 of 4)

A

21 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (1 of 4)

A

21 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (1 of 4)

A

21 58Tuesday, August 28, 2007

RSVD0

XOR Chain Entrance Strap - to be updated

Set PCIE port config bit 110

HDA_SDOUT

1 Enter XOR Chain0

Normal Operation (Default)

ICH_TP3

1

Description

01

Layout Note: Short pins AJ7, AH7 and placeR7G1 within 500 mils from them.

Cap values depend on Xtal

RTC Circuitry

Distance between the ICH9-M andcap on the "P" signal should beidentical distance between theICH9-M and cap on the "N"signal for same pair.

Layout note: R6V7 needs toplaced within 2" of ICH9-M,R6V8 must be placed within 2"of R6V7 w/o stub.

TPM Settings J5G1Clear ME RTC registersKeep ME RTC registers

ShuntOpen

CMOS Settings J5H2Clear CMOSKeep CMOS

ShuntOpen

Internal VRM enabled for VccSus1_05, VccSus1_5, VccCL1_5, VccLAN1_05 and VccCL1_05

R6V756R6V756

41

Y7F132.7680KHZ

Y7F132.7680KHZ

C7V17 0.01uF.

C7V17 0.01uF.

12

J5H2J5H2

C7F110pFC7F110pF

R7V1856

NO

_S

TU

FF

R7V1856

NO

_S

TU

FF

R7H181KNO_STUFF

R7H181KNO_STUFF

C7H2 0.01uF.

C7H2 0.01uF.

12

J5G1J5G1

C7W2 0.01uF NO_STUFFC7W2 0.01uF NO_STUFF

R7U410MR7U410M

C7H10 0.01uFC7H10 0.01uF

R7H7330R7H7330

C7V16 0.01uF.

C7V16 0.01uF.

R7V1556R7V1556

R7V9 56R7V9 56

R5W4 20KR5W4 20K

C7G8 0.01uFC7G8 0.01uF

C7V13 0.01uF NO_STUFFC7V13 0.01uF NO_STUFF

C5G61uFC5G61uF

C7H12 0.01uF.

C7H12 0.01uF.

R7G824.9

.1%

R7G824.9

.1%

R6F1024.9

.1%

R6F1024.9

.1%

R7U8332K1%

R7U8332K1%

C7V18 0.01uF.

C7V18 0.01uF.

C7H1 0.01uF.

C7H1 0.01uF.

R6V556

NO

_S

TU

FF

R6V556

NO

_S

TU

FF

C7H11 0.01uF.

C7H11 0.01uF.

C7V21 0.01uF.

C7V21 0.01uF.

RTCX1C23

RTCX2C24

INTVRMENB22

INTRUDER#C22

GLAN_CLKE25

LAN_RSTSYNCC13

LAN_RXD0F14

LAN_RXD1G13

LAN_RXD2D14

LAN_TXD0D13

LAN_TXD1D12

LAN_TXD2E13

HDA_BIT_CLKAF6

HDA_SYNCAH4

HDA_RST#AE7

HDA_SDIN0AF4

HDA_SDIN1AG4

HDA_SDIN2AH3

HDA_SDOUTAG5

SATALED#AG8

SATA0RXNAJ16

SATA0RXPAH16

SATA0TXNAF17

SATA0TXPAG17

SATA1RXNAH13

SATA1RXPAJ13

SATA1TXNAG14

SATA1TXPAF14

SATA_CLKNAH18

SATA_CLKPAJ18

SATARBIAS#AJ7

SATARBIASAH7

FWH0/LAD0K5

FWH1/LAD1K4

FWH2/LAD2L6

FWH3/LAD3K2

LDRQ0#J3

LDRQ1#/GPIO23J1

FWH4/LFRAME#K3

A20GATEN7

A20M#AJ27

DPRSTP#AJ25

DPSLP#AE23

FERR#AJ26

CPUPWRGDAD22

IGNNE#AF25

INIT#AE22

INTRAG25

RCIN#L3

SMI#AF24

NMIAF23

STPCLK#AH27

THRMTRIP#AG26

RTCRST#A25

GPIO56B10

GLAN_COMPOB27

GLAN_COMPIB28

HDA_SDIN3AE5

SATA4TXNAG12

SATA4RXNAH11

SATA4TXPAF12

SATA4RXPAJ11

TP12AG27

HDA_DOCK_EN#/GPIO33AG7

HDA_DOCK_RST#/GPIO34AE8

LAN100_SLPA22

SATA5RXNAH9

SATA5RXPAJ9

SATA5TXNAE10

SATA5TXPAF10

SRTCRST#F20

RTC

LAN / GLAN

IHDA

SATA

LPC

CPU

U7F1A

ICH9M REV 1.0

RTC

LAN / GLAN

IHDA

SATA

LPC

CPU

U7F1A

ICH9M REV 1.0

R7H1410K

.

R7H1410K

.

C7H30.1uF

.10%

SMC0402C7H30.1uF

.10%

SMC0402

C7G9 0.01uF.

C7G9 0.01uF.

C7F210pFC7F210pF

R6V6 0

.

R6V6 0

.

R5G10 20KR5G10 20K

R8U6 10KR8U6 10K

C7V20 0.01uFC7V20 0.01uF

12

CR7H1GREENCR7H1GREEN

R7V10 0

.

R7V10 0

.

R6V90

.

R6V90

.

C7V22 0.01uF.

C7V22 0.01uF.

C5W21uF80%

C5W21uF80%

R8U110K5%

.R8U110K5%

.

1 3

CR5H2

BAT54

CR5H2

BAT54

1 3

CR5H1

BAT54

CR5H1

BAT54

1

24

53

U7H1

74AHC1G08

.

U7H1

74AHC1G08

.

C5H31uFC5H31uF

R5W51KR5W51K

C7V19 0.01uF.

C7V19 0.01uF.

R7H80

NO_STUFF R7H80

NO_STUFF

R7G131KNO_STUFF

R7G131KNO_STUFF

C7V15 0.01uFC7V15 0.01uF

R5W31MR5W31M

13

2

BT5H1Battery_HolderBT5H1Battery_Holder

C7W3 0.01uF NO_STUFFC7W3 0.01uF NO_STUFF

R6V8 54.9

.

1%R6V8 54.9

.

1%

C7V14 0.01uF NO_STUFFC7V14 0.01uF NO_STUFF

C7H13 0.01uF.

C7H13 0.01uF.

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Page 22: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_GNT#0

SPI_CS#1

PCIE_TXN3_C

PCIE_TXN4_C

PCIE_TXP3_C

PCIE_TXP6_CPCIE_TXN6_C

PCIE_TXP5_CPCIE_TXN5_C

PCIE_TXP4_C

PCI_GNT#3

PCI_STOP#PCI_TRDY#

INT_PIRQH#INT_PIRQG#

PCI_SERR#

PCI_REQ#3

PCI_FRAME#

INT_PIRQE#

ICH_GPIO52

PCI_DEVSEL#

INT_PIRQF#

PCI_REQ#0

INT_PIRQC#

PCI_REQ#1

INT_PIRQD#

PCI_LOCK#

INT_PIRQA#INT_PIRQB#

PCI_PERR#

PCI_IRDY#

PLT_RST#

PCI_GNT#0_R

PCIE_RXP2_RPCIE_RXN2_R

PCIE_TXP1_CPCIE_TXN1_CPCIE_RXP1_RPCIE_RXN1_R

USB_PN9USB_PP9

DMI_IRCOMP_R

PCI_AD0

PCI_AD6

PCI_AD25

PCI_AD23

PCI_AD15

PCI_AD22

PCI_AD24

PCI_AD1

PCI_AD11

PCI_AD26

PCI_AD8

PCI_AD5

PCI_AD27

PCI_AD12

PCI_AD7

PCI_AD17PCI_AD16

INT_PIRQB#

PCI_AD28

PCI_AD20

INT_PIRQA#

PCI_AD30PCI_AD31

INT_PIRQD#

PCI_AD4

PCI_AD29

PCI_AD14

PCI_AD19

PCI_AD9

PCI_AD2

PCI_AD10

PCI_AD13

PCI_AD18

PCI_AD21

PCI_AD3

SPI_CLK_RSPI_CS#0_R

PCIE_RXN5_SLOT5_RPCIE_RXP5_SLOT5_R

GLAN_RXN_RGLAN_RXP_R

SPI_CS#1_R

USBRBIAS_PN

DMI_RXN0_RDMI_RXP0_RDMI_TXN0_RDMI_TXP0_R

DMI_RXN1_RDMI_RXP1_RDMI_TXN1_RDMI_TXP1_R

DMI_RXN2_RDMI_RXP2_RDMI_TXN2_RDMI_TXP2_R

DMI_RXN3_RDMI_RXP3_RDMI_TXN3_RDMI_TXP3_R

PCIE_TXP2_C

SPI_MOSI_R

PCIE_TXN2_C

SPI_MOSI_R_3.2V

SPI_CLK34

SPI_CS#134

SPI_SI34SPI_SO34

USB_PN2 29USB_PP2 29

USB_PN6 29

USB_PP4 29

USB_PP1 29

USB_PN8 29

USB_PP5 29

USB_PP8 29

USB_PN1 29

USB_PP3 29

USB_PP0 29

USB_PN3 29

USB_PN0 29

USB_PN4 29

USB_PN7 29USB_PP7 29

USB_PN5 29

USB_PP6 29

SPI_CS#034

PCI_IRDY# 32

PCI_TRDY# 32

PCI_CBE#3 32

PCI_PERR# 32

PCI_STOP# 32

PCI_PAR 32

PCI_CBE#1 32

PCI_LOCK# 32

PCI_CBE#2 32

PCI_DEVSEL# 32

PCI_CBE#0 32

PCI_AD[31:0]32

PCI_SERR# 32

PCI_PME# 32,43

PCI_FRAME# 32

+V3.3S

+V3.3S

+V1.5S_PCIE_ICH 21,24

USB_PN10 29USB_PP10 29

USB_PP11 29USB_PN11 29

USB_PP9_R 44USB_PN9_R 44

USB_PN9_R_FPIO 29

USB_PP9_R_FPIO 29

INT_PIRQC#32

INT_PIRQE# 32

PCIE_RXN3_SLOT326

PCIE_RXP5_SLOT526

GLAN_RXN33

PCIE_RXN2_SLOT225PCIE_RXP2_SLOT225

PCIE_RXN5_SLOT526

PCIE_RXP4_SLOT426PCIE_RXN4_SLOT426

PCIE_RXP3_SLOT326

GLAN_RXP33

PCIE_RXP2_DOCK44PCIE_RXN2_DOCK44

CLK_PCIE_ICH 35CLK_PCIE_ICH# 35

USB_OC#329

USB_OC#4_R

USB_OC#029

USB_OC#6_R

USB_OC#529

USB_OC#5_R

USB_OC#129

USB_OC#7_R

USB_OC#1_RUSB_OC#0_R

USB_OC#2_RUSB_OC#3_R

USB_OC#229

USB_OC#429

USB_OC#629USB_OC#729USB_OC#829USB_OC#929

PCIE_RXN1_SLOT125PCIE_RXP1_SLOT125

PCIE_RXN1_DOCK44PCIE_RXP1_DOCK44

PCI_REQ#0 32

CLK_PCIF_ICH 36

PCI_REQ#1 32

PCI_REQ#3 32

USB_OC#8_RUSB_OC#9_R

USB_OC#1029USB_OC#1129

BUF_PLT_RST#40,43

PCIE_TXN3_SLOT326

PCIE_TXN5_SLOT526

PCIE_TXN1_SLOT125

PCIE_TXN2_SLOT225

PCIE_TXN4_SLOT426

GLAN_TXN33

PCIE_TXP4_SLOT426

PCIE_TXP1_SLOT125

PCIE_TXP3_SLOT326

GLAN_TXP33

PCIE_TXP5_SLOT526

PCIE_TXP2_SLOT225

PCIE_TXP1_DOCK44

PCIE_TXP2_DOCK44

PCIE_TXN1_DOCK44

PCIE_TXN2_DOCK44

PCI_GNT#0 32

PCI_GNT#3 32

PCI_GNT#1 32

PCI_RST# 32,41

PLT_RST# 7,19,25,26,38,41,57

ICH_GPIO53

+V3.3M_WOL24,33,34,44,48,55,57

DMI_TXN1 7

DMI_TXP3 7DMI_TXN3 7

DMI_TXP1 7

DMI_TXP2 7

DMI_TXP0 7

DMI_TXN2 7

DMI_TXN0 7

DMI_RXP3 7

DMI_RXP2 7DMI_RXN2 7

DMI_RXN3 7

DMI_RXP0 7

DMI_RXN1 7DMI_RXP1 7

DMI_RXN0 7

INT_PIRQF# 32INT_PIRQG# 32INT_PIRQH# 32

ICH_GPIO52

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (2 of 4)

A

22 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (2 of 4)

A

22 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (2 of 4)

A

22 58Tuesday, August 28, 2007

SPI_CS#1

11

SPI(Default)0Boot BIOS LocationPCI_GNT#0

LPC PCI

10

GNT#0 and SPI_CS#1have a weakinternal pull up

1

Boot BIOS Strap

Default : 1-2

PCI_GNT#3 Low = A16 swap override/Top-BlockSwap Override enabledHigh = Default (Jumper 1-X)

A16 swap override Strap/Top-Block Swap Override jumper

ICH9M Pullups

Buffer to reduce loading on

PLT_RST#.

Layout Note:R7U11,R7F7,R7F8,R7F9 to be placed within 600mils of U7F1

GLAN_TXP&TXN towardsGLAN Device

PCI_E_SLOT6_TXN_C&TXPC(from ICH)

PCI_E_SLOT5_TXN_C&TXPC(towards PCIe slot5)

PCI_E_SLOT5_TXN_C&TXPC(from ICH)

PCIe LANE 6 SELECTION

Lane 6 can be connected to LAN or Slot 5 depending on the stuffing option described below.Placed the components such that CAP1 (0603)Pad2 &CAP2 Pad1 are next to each other as shown above. The Placement is such that a 0603 Capacitor can be placed there . Similar placement followed for CAP3 and CAP4.This approach is same for RX Path also.

R8G40

.

R8G40

.

4 5RP9B2D 8.2KRP9B2D 8.2K

C6F2 0.1uF

.

C6F2 0.1uF

.

R7H6 0R7H6 0

R6F19 0

.

R6F19 0

.

2 7RP9B1B 8.2KRP9B1B 8.2K

R6F2 0

.

R6F2 0

.

C7T40.1uF20%.

C7T40.1uF20%.

R8G60

.

R8G60

.

3 6RP9C1C 8.2KRP9C1C 8.2K

R9D9 1K

.

R9D9 1K

.

C6F11 0.1uFC6F11 0.1uF

R8V30

NO_STUFF

R8V30

NO_STUFF

R6F16 0

.

R6F16 0

.

C6F10 0.1uFC6F10 0.1uF

R6U5 0

.

R6U5 0

.

12

J8G7J8G7

R8G1 0R8G1 0

R7U11 15R7U11 15

R8U9 0R8U9 0

12

J9

D2

J9

D2

C6F4 0.1uF

.

C6F4 0.1uF

.

R6F4 0

.

R6F4 0

.

1 8RP9C1A 8.2KRP9C1A 8.2K

R6U21 0R6U21 0

4 5RP9C1D 8.2KRP9C1D 8.2K

PERN1N29

PERP1N28

PETN1P27

PETP1P26

PERN2L29

PERP2L28

PETN2M27

PETP2M26

PERN3J29

PERP3J28

PETN3K27

PETP3K26

PERN4G29

PERP4G28

PETN4H27

PETP4H26

PERN5E29

PERP5E28

PETN5F27

PETP5F26

PERN6/GLAN_RXNC29

PERP6/GLAN_RXPC28

PETN6/GLAN_TXND27

PETP6/GLAN_TXPD26

DMI0RXNV27

DMI0RXPV26

DMI0TXNU29

DMI0TXPU28

DMI1RXNY27

DMI1RXPY26

DMI1TXNW29

DMI1TXPW28

DMI2RXNAB27

DMI2RXPAB26

DMI2TXNAA29

DMI2TXPAA28

DMI3RXNAD27

DMI3RXPAD26

DMI3TXNAC29

DMI3TXPAC28

DMI_CLKNT26

DMI_CLKPT25

DMI_ZCOMPAF29

DMI_IRCOMPAF28

OC0#/GPIO59N4

OC1#/GPIO40N5

OC2#/GPIO41N6

OC3#/GPIO42P6

OC4#/GPIO43M1

OC5#/GPIO29N2

OC6#/GPIO30M4

OC7#/GPIO31M3

USBP0NAC5

USBP0PAC4

USBP1NAD3

USBP1PAD2

USBP2NAC1

USBP2PAC2

USBP3NAA5

USBP3PAA4

USBP4NAB2

USBP4PAB3

USBP5NAA1

USBP5PAA2

USBP6NW5

USBP6PW4

USBP7NY3

USBP7PY2

USBRBIAS#AG1

USBRBIASAG2

SPI_CLKD23

SPI_CS0#D24

SPI_CS1#/GPIO58/CLGPIO6F23

SPI_MOSID25

SPI_MISOE23

OC8#/GPIO44N3

OC9#/GPIO45N1

USBP8PW2

USBP8NW1

USBP9NV2

USBP9PV3

USBP10NU5

USBP11NU1

USBP10PU4

USBP11PU2

OC10#/GPIO46P5

OC11#/GPIO47P3

PCI-Express

Direct Media Interface

USB

SPI

U7F1D

ICH9M REV 1.0

PCI-Express

Direct Media Interface

USB

SPI

U7F1D

ICH9M REV 1.0

C6U3 0.1uFC6U3 0.1uF

R8F18 0R8F18 0

R6F17 0

.

R6F17 0

.

C6U4 0.1uFC6U4 0.1uF

4 5RP9B1D 8.2KRP9B1D 8.2K

4 5RP8C1D 8.2KRP8C1D 8.2K

1 8RP9B1A 8.2KRP9B1A 8.2K

R8F17 0R8F17 0

2 7RP9C1B 8.2KRP9C1B 8.2K

R8U7 0R8U7 0

R8F12 0R8F12 0

R7F8 15R7F8 15

R6U4 0

.

R6U4 0

.

1 8RP8C1A 8.2KRP8C1A 8.2K

R8G2 0R8G2 0

R8F10 1K5%

R8F10 1K5%

R6F3 0

.

R6F3 0

.

R6F14 0

.

R6F14 0

.

3 6RP9B2C 8.2KRP9B2C 8.2K

R6G524.9

.1%

R6G524.9

.1%

2 7RP9B2B 8.2KRP9B2B 8.2K

R6U2 0

.

R6U2 0

.

C6F1 0.1uF

.

C6F1 0.1uF

.

R7F7 15R7F7 15

R6F12 0

.

R6F12 0

.

R6F11 0

.

R6F11 0

.

C6F3 0.1uF

.

C6F3 0.1uF

.

R6U3 0

.

R6U3 0

.

R6F1 0

.

R6F1 0

.

1 8RP9D1A 8.2KRP9D1A 8.2K

3 6RP9B1C 8.2KRP9B1C 8.2K

R6F18 0

.

R6F18 0

.

R6U6 0

.

R6U6 0

.

2 7RP8C1B 8.2KRP8C1B 8.2K

C6U5 0.1uFC6U5 0.1uF

R8F16 0R8F16 0

R8F19 0R8F19 0

2 7RP9D1B 8.2KRP9D1B 8.2K

R6U1 0

.

R6U1 0

.

R6U8 0

.

R6U8 0

.

4 5RP9D1D 8.2KRP9D1D 8.2K

R6F5 0

.

R6F5 0

.

C6U6 0.1uFC6U6 0.1uF

C6U11 0.1uF

.

C6U11 0.1uF

.

R6U7 0

.

R6U7 0

.

12

J8H1J8H1

C6F8 0.1uF

.

C6F8 0.1uF

.

R7G522.61%

R7G522.61%

R7F9 15R7F9 15

R6F6 0

.

R6F6 0

.

R6U22 0R6U22 0

R8V40

NO_STUFF

R8V40

NO_STUFF

1

24

53

U8E2

74AHC1G08

.

U8E2

74AHC1G08

.

R6F13 0

.

R6F13 0

.

C6U12 0.1uF

.

C6U12 0.1uF

.

1 8RP9B2A 8.2KRP9B2A 8.2K

C6U7 0.1uFC6U7 0.1uF

R7F31K

NO_STUFF

R7F31K

NO_STUFF

R6F8 0

.

R6F8 0

.

3 6RP8C1C 8.2KRP8C1C 8.2K

R6F7 0

.

R6F7 0

.

R6U29 0NO_STUFF

R6U29 0NO_STUFF

C6U8 0.1uFC6U8 0.1uF

R8T6100KR8T6100K

R6U27 0R6U27 0

3 6RP9D1C 8.2KRP9D1C 8.2K

AD0D11

AD1C8

AD2D9

AD3E12

AD4E9

AD5C9

AD6E10

AD7B7

AD8C7

AD9C5

AD10G11

AD11F8

AD12F11

AD13E7

AD14A3

AD15D2

AD16F10

AD17D5

AD18D10

AD19B3

AD20F7

AD21C3

AD22F3

AD23F4

AD24C1

AD25G7

AD26H7

AD27D1

AD28G5

AD29H6

AD30G1

AD31H3

REQ0#F1

GNT0#G4

REQ1#/GPIO50B6

GNT1#/GPIO51A7

REQ2#/GPIO52F13

GNT2#/GPIO53F12

REQ3#/GPIO54E6

GNT3#/GPIO55F6

C/BE0#D8

C/BE1#B4

C/BE2#D6

C/BE3#A5

IRDY#D3

PARE3

PCIRST#R1

DEVSEL#C6

PERR#E4

PLOCK#C2

SERR#J4

STOP#A4

TRDY#F5

FRAME#D7

PLTRST#C14

PCICLKD4

PME#R2

PIRQA#J5

PIRQB#E1

PIRQC#J6

PIRQD#C4

PIRQH#/GPIO5G2

PIRQG#/GPIO4F2

PIRQF#/GPIO3K6

PIRQE#/GPIO2H4

PCI

Interrupt I/F

U7F1B

ICH9M REV 1.0

PCI

Interrupt I/F

U7F1B

ICH9M REV 1.0

C6F9 0.1uFC6F9 0.1uF

www.laptop-schematics

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Page 23: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SMB_DATA_ME

PM_THRM#

CLK_SATA_OE#

SMB_CLK_ME

PM_CLKRUN#

PM_RI#

INT_SERIRQ

PM_RSMRST#

SMB_ALERT#

SMB_DATA

PCIE_WAKE#

SMB_CLK

ALL_SYS_PWRGD

PM_BATLOW#_R

HDA_SPKR

I2C_EN3

SMB_DATA_M2

DA2

CL1

SMB_DATA_M3

SMB_DATA_S4

SMB_DATA_A1

I2C_EN1

SMB_CLK

SMB_CLK_M3

I2C_EN2

SMB_CLK_A1

SMB_CLK_S4

SMB_CLK_M2

DA1CL2

I2C_EN4

SMB_DATA

PM_ICH_PWROK

SLP_S4#_R

SMC_WAKE_SCI#_R

VR_PWRGD_CLKEN

PM_RSMRST#_R

PM_S4_STATE#_R

PM_STPCPU_ICH#

SMB_ALERT#

PM_STPPCI_ICH#

PM_DPRSLPVR_R

PM_ICH_PWROK

PM_SLP_S5#_R

CL_VREF1_ICH_R

PM_BATLOW#_R

SLP_S3#_R

SATA_PWR_EN#0_RSATA_PWR_EN#1_R

SATA_PWR_EN#1_R

ICH_GPIO12

ICH_GPIO6

ICH_GPIO12_R

SMC_WAKE_SCI#_R

SATA_PWR_EN#0_R

CL_VREF0_ICH_R

DMI_TERM_SEL

DMI_TERM_SEL

ICH_GPIO38

ICH_GPIO36

ICH_GPIO57

ICH_GPIO57_J

TP_ICH_PWM0TP_ICH_PWM1TP_ICH_PWM2

ICH_GPIO38

TXT_STATUS

TXT_STATUS_R

ICH_GPIO13

ICH_GPIO12_R

ICH_GPIO37_R

PM_SLP_M#_R

SMB_CLK_M2 13,14,15SMB_DATA_M2 13,14,15

SMB_CLK_A1 25,26,32,44

SMB_CLK_M3 35,36

SMB_CLK_S4 19,43SMB_DATA_S4 19,43

SMB_DATA_M3 35,36

SMB_DATA_A1 25,26,32,44

CL_CLK1 26

CL_DATA0 7CL_DATA1 26

CL_CLK0 7SV_SET_UP

ICH_GPIO37_R

ICH_GPIO19_R

CL_RST#0 7

ICH_GPIO20

SMC_WAKE_SCI#_R

SATA_PWR_EN#0_RSATA_PWR_EN#1_R

SMB_DATA

INT_SERIRQ38,40,43

ICH_TP321

SMB_CLK

PM_CLKRUN#32,38,40,43

+V3.3S

+V3.3A

+V3.3S 5,7,10,12,13,16,17,18,19,20,21,22,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3A

+V3.3S

+V3.3A

+V3.3S

+V3.3M 13,14,15,35,55,57

+V3.3M13,14,15,35,55,57

+V3.3A19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3S

+V3.3M13,14,15,35,55,57

+V3.3A 19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3M13,14,15,35,55,57

+V3.3A 19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

SMB_CLK_ME40,43SMB_DATA_ME40,43

CL_RST#1 26

SMC_RUNTIME_SCI#40,43

+V3.3A

ALL_SYS_PWRGD 40,43,47

DELAY_VR_PWRGOOD 7

CLK_USB48 35

PM_PWRBTN# 40,43

CLK_REF_ICH 35

PM_LAN_ENABLE 33,40,43

PM_THRM#5,12,40,43

PM_BATLOW# 40,43

PM_RSMRST# 40,43,56

MCH_ICH_SYNC#7

VR_PWRGD_CLKEN#

MPWROK 7,46

SATA_DET#1 31

EV_V3.3_ICH_CLVREF0

CRB_SV_DET_R

SMC_WAKE_SCI# 40,43

BIOS_REC 41

PCIE_WAKE#19,25,26,44

PM_RI#38,43

PM_SYSRST#56

AC_PRESENT 40,43,56

PM_STPCPU#35,43

PM_SLP_S3# 11,40,43,44,46,47,49,55,57

PM_DPRSLPVR 7,43,52

CLK_PWRGD 35,36

PM_SUS_STAT#38,40,43

CLK_SATA_OE#35

PM_SLP_S4# 46,55

SUS_CLK 43

HDA_SPKR27,44

PM_STPPCI#35,43

PM_SLP_M# 40,43,44,47,55,57

SATA_PWR_EN#0 30SATA_PWR_EN#1 31

ICH_GPIO36

LAN_WOL_EN 40,43,55,57

SUS_PWR_ACK 40,43

CL_VREF0_ICH

MFG_MODE

MCH_ICH_SYNC_R#

ICH_TP7

EV_V3.3_ICH_CLVREF1

CL_VREF1_ICH

ICH_GPIO18

SATA_DET#0 30

+V3.3A

SMC_EXTSMI#38,40,43,44

PM_SLP_S5# 57

PM_S4_STATE# 32,40,43,44,55,57

PM_SYNC#7

+V3.3A

+V3.3S

ICH_GPIO13

ICH_GPIO6034

ICH_GPIO24 34

BIOS_REC41

ICH_GPIO6

ICH_GPIO12_RICH_GPIO12 57ICH_GPIO37

+V3.3S_PEG19

+V3.3S

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (3 of 4)

A

23 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (3 of 4)

A

23 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (3 of 4)

A

23 58Tuesday, August 28, 2007

ICH9M Pullups

J8F2 Default is 1-Xfor BIOSrecovery 1-2

HDA_SPKR

No Reboot Strap

Low = DefaultHigh = No Reboot

NO_STUFF

GPIO49 has a weak internal pull-up

R7V16 is used for testingpurposes only

TPM PHYSICAL PRESENCEJ7H2 1-X default

TXT Status LED

ICH_GPIO38 is used for TXT status indication

R6H110K

NO_STUFF

R6H110K

NO_STUFF

R9A5 10KR9A5 10K

R7H13100K5%

R7H13100K5%

R6C50

.

R6C50

.

R8D1 10KR8D1 10K

12

J7H2J7H2

C7U30.1uF

.10%

C7U30.1uF

.10%

R9G17 10KR9G17 10K

R9A4 10KR9A4 10K

R7U17 0

NO_STUFF

R7U17 0

NO_STUFF

R7D11 2.2KR7D11 2.2K

R7R5 10KR7R5 10K

R7U150

.

R7U150

.

R7G150

.

R7G150

.

R7U19 0

.

R7U19 0

.

R6U110

NO_STUFF

R6U110

NO_STUFF

R7R3 10KR7R3 10K

R7V12 10KR7V12 10K

R7R7 10KR7R7 10K

R8G5 10KR8G5 10K

12

R7U18453_1%R7U18453_1%

R8F13 0

.

R8F13 0

.

R8F40

.

R8F40

.

SATA0GP/GPIO21AH23

SATA1GP/GPIO19AF19

SATA4GP/GPIO36AE21

SATA5GP/GPIO37AD20

SMBCLKG16

SMBDATAA13

LINKALERT#/GPIO60/CLGPIO4E17

SMLINK0C17

SMLINK1B18

SUS_STAT#/LPCPD#R4

SYS_RESET#G19

PMSYNC#/GPIO0M6

GPIO1AG19

GPIO6AH21

GPIO7AG21

GPIO8A21

GPIO12C12

SMBALERT#/GPIO11A17

GPIO17AE18

GPIO18K1

SCLOCK/GPIO22AJ22

SATACLKREQ#/GPIO35L1

STP_PCI#A14

STP_CPU#E19

SLOAD/GPIO38AE19

SDATAOUT0/GPIO39AG22

CLKRUN#L4

SDATAOUT1/GPIO48AF21

WAKE#E20

SERIRQM5

THRM#AJ23

VRMPWRGDD21

CLK14H1

CLK48AF3

SUSCLKP1

SLP_S3#C16

SLP_S4#E16

SLP_S5#G17

PWROKG20

DPRSLPVR/GPIO16M2

BATLOW#B13

PWRBTN#R3

LAN_RST#D20

RSMRST#D22

RI#F19

S4_STATE#/GPIO26C10

GPIO27A9

GPIO28D19

TP11A20

CK_PWRGDR5

CLPWROKR6

SLP_M#B16

GPIO20AF8

CL_CLK0F24

CL_CLK1B19

CL_DATA0F22

CL_DATA1C19

CL_VREF0C25

CL_VREF1A19

CL_RST0#F21

GPIO10/SUS_PWR_ACKC18

WOL_EN/GPIO9C20

GPIO14/AC_PRESENTC11

MEM_LED/GPIO24A16

SPKRM7

TP3B21

CL_RST1#D18

GPIO49AH24

GPIO13C21

GPIO57/CLGPIO5A8

TP10AJ21

TP8AH20

MCH_SYNC#AJ24

TP9AJ20

SATA

SMB

SYS

GPIO

GPIO

GPIO

Clocks

Power MGT

Controller Link

MISC

U7F1C

ICH9M REV 1.0

SATA

SMB

SYS

GPIO

GPIO

GPIO

Clocks

Power MGT

Controller Link

MISC

U7F1C

ICH9M REV 1.0

C8C10.1uF

.10%

C8C10.1uF

.10%

R7U133.24K1%

R7U133.24K1%

R7T16 10KR7T16 10K

R8C5 10KR8C5 10K

EXPSCL11

EXPSCL22

EXPSDA118

EXPSDA219

SCL03

SDA04

EN17

EN211

EN314

EN417

VSS10

VCC20

SCL15

SDA16

SCL28

SDA29

SCL312

SDA313

SCL415

SDA416

U7D1

EXP. 5-CH-I2C HUB

U7D1

EXP. 5-CH-I2C HUB

C7R20.1uF20%.

C7R20.1uF20%.

R7T2210K

.

5%R7T22

10K

.

5%

R7R2 10KR7R2 10K

R7V1 0R7V1 0

R416 10K

NO_STUFF

R416 10K

NO_STUFF

R6H410K

NO_STUFF

R6H410K

NO_STUFF

R7U250

.

R7U250

.

R8F200

.

R8F200

.

R7U23 0R7U23 0

R7R4 10KR7R4 10K

R8H90

.

R8H90

.

R8F9 8.2KR8F9 8.2K

R7U24 0R7U24 0

R8V1010K

.5%

R8V1010K

.5%

R7G7 8.2KR7G7 8.2K

R8W60

.

R8W60

.

R7R11 10KR7R11 10K

R7U27 0. 5%R7U27 0. 5%

R7D3 10KR7D3 10K

R7V200

.

R7V200

.

R8C410K5%

R8C410K5%

C7W10.1uF

.10%

C7W10.1uF

.10%

R8U2 0

.

R8U2 0

.

2 4

5

3

U6H1

INVERTER

U6H1

INVERTER

R6C310K

.

R6C310K

.

R7V22 10K

NO_STUFF

R7V22 10K

NO_STUFF

12

J8F2J8F2

3

1

2

Q8G1BSS138

.

Q8G1BSS138

.R7R9 10KR7R9 10K

R7U9 10KR7U9 10K

R8W30

.

R8W30

.

R7U22

10K

R7U22

10K

R7F10 10KR7F10 10K

1

24

53

U8C2

74AHC1G08

.

U8C2

74AHC1G08

.

R7R8 10KR7R8 10K

R8U4 8.2KR8U4 8.2K

R8F810KR8F810K

R7T20 10KR7T20 10K

12

CR8G1GREEN

.

CR8G1GREEN

.

R7H1210KR7H1210K

R7G6 10KR7G6 10K

R7U63.24K1%

R7U63.24K1%

R7D1 10KR7D1 10K

R7U12 10KR7U12 10K

R8F141KNO_STUFF

R8F141KNO_STUFF

12

R7U20453_1%R7U20453_1%

R8G11240R8G11240

R7U21 10KR7U21 10K

R7R12 10KR7R12 10K

R7V16

1K

NO_STUFFR7V16

1K

NO_STUFF

R7U14 10K

.

R7U14 10K

.

R7H4100K5%

R7H4100K5%

R7D10 2.2KR7D10 2.2K

R3J30

NO_STUFF

R3J30

NO_STUFF

R7R10 10KR7R10 10K

R7P32K1%

R7P32K1%

R8F5 10KR8F5 10K

C7U20.1uF

.10%

C7U20.1uF

.10%

R6U12 0

NO_STUFF

R6U12 0

NO_STUFF

R7U1 1KR7U1 1K

www.laptop-schematics

.com

Page 24: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V1.05S_ICH_DMI

+V1.5S_PCIE_R

TP_VCCSUS1_05_ICH_1

+V1.5S_ICH_GLANPLL_R

+V1.5S_ICH_VCCDMIPLL_R

+V1.5S_APLL_ICH

+V1.5S_ICH_GLANPLL_R_L

+V3.3S_1.5S_HDA_IO_ICH

+V3.3S_PCI_ICH

TP_VCCSUS1_05_ICH_2

TP_VCCSUS1_5_ICH_1

VCCSUS1_5_INT_ICH

+V5S_ICH_VCC5REF

+V5A_ICH_V5REF_SUS

+V3.3S_GLAN_ICH

+V3.3M_VCCPAUX VCCLAN1_05_INT_ICH

+V1.5S_ICH_VCCDMIPLL

+V3.3S_SATA_ICH

+V3.3S_VCCPCORE_ICH

+V3.3A_USB_ICH

+V3.3A_ICH

VCCCL1_05_INT_ICH

VCCCL1_5_INT_ICH

+V3.3M_ICH

+V1.5S 4,10,11,28,47,55,57

+V1.05S_ICH41

+V3.3S

+V1.5S 4,10,11,28,47,55,57

+V1.05S4,9,10,47,55

+V3.3S_DMI_ICH

+V1.5S_PCIE_ICH21,22

+V3.3A

+V1.5S 4,10,11,28,47,55,57

+V1.05S4,9,10,47,55

+V1.5S4,10,11,28,47,55,57

+V5A

+V3.3A

+V3.3S_1.5S_HDA_IO21,27,28

+V1.5S_PCIE_ICH21,22+V3.3S

+V1.05S_ICH_IO21

+V1.5S_USB_ICH

+V1.5S_SATA_ICH

+V5S 5,11,12,16,17,18,28,30,31,32,39,48,49,52,55,56,57

+V3.3S

+V3.3A_1.5A_HDA_IO27,28,44

+V3.3A_RTC21

+V3.3M_WOL22,33,34,44,48,55,57

+V1.5S_SATA_ICH

+V1.05S_ICH41

+V3.3M_WOL22,33,34,44,48,55,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (4 of 4)

A

24 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (4 of 4)

A

24 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

ICH9M (4 of 4)

A

24 58Tuesday, August 28, 2007

R7G16 0.002R7G16 0.002

C6F130.01uF10%.402

C6F130.01uF10%.402

C7U40.1uF

.10%SMC0402

C7U40.1uF

.10%SMC0402

1

3

CR8V1BAT54CR8V1BAT54

C6F74.7uF

.10%

C6F74.7uF

.10%

C7G51.0uF

.402

C7G51.0uF

.402

C7V60.1uF

.10%SMC0402

C7V60.1uF

.10%SMC0402

C7V10.022uF10%.402

C7V10.022uF10%.402

C6G322uF

.

C6G322uF

.

R7U7 0.002R7U7 0.002C7F310uF

.20%

C7F310uF

.20%

R6G6 0.002R6G6 0.002

L7G1

10uH

L7G1

10uH

C7G10.022uF10%.402

C7G10.022uF10%.402

R6V10 0.002R6V10 0.002

C6F1210uF

.20%

C6F1210uF

.20%

R7G1 0.002R7G1 0.002

C7U141UF

NO_STUFF

C7U141UF

NO_STUFF

R6G20

.

R6G20

.

V5REFA6

V5REF_SUSAE1

VCC1_5_B[1]AA24

VCC1_5_B[2]AA25

VCC1_5_B[3]AB24

VCC1_5_B[4]AB25

VCC1_5_B[5]AC24

VCC1_5_B[6]AC25

VCC1_5_B[7]AD24

VCC1_5_B[8]AD25

VCC1_5_B[9]AE25

VCC1_5_B[10]AE26

VCC1_5_B[11]AE27

VCC1_5_B[12]AE28

VCC1_5_B[13]AE29

VCC1_5_B[14]F25

VCC1_5_B[15]G25

VCC1_5_B[16]H24

VCC1_5_B[17]H25

VCC1_5_B[18]J24

VCC1_5_B[19]J25

VCC1_5_B[20]K24

VCC1_5_B[21]K25

VCC1_5_B[22]L23

VCC1_5_B[23]L24

VCC1_5_B[24]L25

VCC1_5_B[25]M24

VCC1_5_B[26]M25

VCC1_5_B[27]N23

VCC1_5_B[28]N24

VCC1_5_B[29]N25

VCC1_5_B[30]P24

VCC1_5_B[31]P25

VCC1_5_B[32]R24

VCC1_5_B[33]R25

VCC1_5_B[34]R26

VCC1_5_B[35]R27

VCC1_5_B[36]T24

VCC1_5_B[37]T27

VCC1_5_B[38]T28

VCC1_5_B[39]T29

VCC1_5_B[40]U24

VCC3_3[1]AG29

VCCDMIPLLR29

VCC1_5_A[1]AC16

VCC1_5_A[2]AD15

VCC1_5_A[3]AD16

VCC1_5_A[4]AE15

VCC1_5_A[5]AF15

VCCSATAPLLAJ19

VCC3_3[2]AJ6

VCC1_5_A[9]AC11

VCC1_5_A[10]AD11

VCCUSBPLLAJ5

VCCLAN1_05[1]A10

VCCLAN1_05[2]A11

VCC1_05[1]A15

VCC1_05[2]B15

VCC1_05[3]C15

VCC1_05[4]D15

VCC1_05[5]E15

VCC1_05[6]F15

VCC1_05[7]L11

VCC1_05[8]L12

VCC1_05[9]L14

VCC1_05[10]L16

VCC1_05[11]L17

VCC1_05[12]L18

VCC1_05[13]M11

VCC1_05[14]M18

VCC1_05[15]P11

VCC1_05[16]P18

VCC1_05[17]T11

VCC1_05[18]T18

VCC1_05[19]U11

VCC1_05[20]U18

VCCLAN3_3[1]A12

VCCLAN3_3[2]B12

VCCHDAAJ4

VCCSUSHDAAJ3

V_CPU_IO[1]AB23

V_CPU_IO[2]AC23

VCC3_3[9]F9

VCC3_3[10]G3

VCC3_3[11]G6

VCC3_3[12]J2

VCC3_3[13]J7

VCC3_3[14]K7

VCCRTCA23

VCCSUS3_3[1]A18

VCCSUS3_3[2]D16

VCCSUS3_3[3]D17

VCCSUS3_3[4]E22

VCCSUS3_3[6]T1

VCCSUS3_3[7]T2

VCCSUS3_3[8]T3

VCCSUS3_3[9]T4

VCCSUS3_3[10]T5

VCCSUS3_3[11]T6

VCCSUS3_3[12]U6

VCCSUS3_3[13]U7

VCCSUS3_3[14]V6

VCCSUS3_3[15]V7

VCCSUS3_3[16]W6

VCCSUS3_3[17]W7

VCC1_5_A[13]AG10

VCCSUS1_05[1]AC8

VCCSUS1_05[2]F17

VCC1_5_A[22]G9

VCC1_5_A[23]AC12

VCC1_5_A[24]AC13

VCC1_5_A[25]AC14

VCC1_5_A[26]AA7

VCCSUS3_3[5]AF1

VCC3_3[8]B9

VCC1_5_A[27]AB6

VCC1_05[22]V12

VCC1_05[25]V17

VCC1_05[23]V14

VCC1_05[21]V11

VCC1_05[26]V18

VCC1_05[24]V16

VCCGLAN1_5[4]E27

VCCGLAN1_5[2]D29

VCCGLAN1_5[3]E26

VCCGLAN1_5[1]D28

VCCGLAN3_3A26

VCCGLANPLLA27

VCC3_3[3]AD19

VCCSUS3_3[18]Y6

VCCSUS1_5[1]AD8

VCCSUS1_5[2]F18

VCC_DMI[2]Y23

VCC_DMI[1]W23

VCCCL1_05G22

VCCCL3_3[2]B24

VCCCL3_3[1]A24

VCCCL1_5G23

VCC1_5_B[45]W24

VCC1_5_B[43]V25

VCC1_5_B[41]U25

VCC1_5_B[46]W25

VCC1_5_B[44]U23

VCC1_5_B[42]V24

VCC1_5_B[47]K23

VCC1_5_B[48]Y24

VCC1_5_B[49]Y25

VCC1_5_A[6]AG15

VCC1_5_A[7]AH15

VCC1_5_A[8]AJ15

VCC1_5_A[11]AE11

VCC1_5_A[12]AF11

VCCSUS3_3[19]Y7

VCC3_3[4]AF20

VCC3_3[5]AG24

VCC3_3[6]AC20

VCC3_3[7]AC10

VCC1_5_A[20]AC21

VCC1_5_A[21]G10

VCC1_5_A[19]AC19

VCC1_5_A[18]AC18

VCC1_5_A[17]AC9

VCC1_5_A[16]AJ10

VCC1_5_A[15]AH10

VCC1_5_A[14]AG11

VCC1_5_A[28]AB7

VCC1_5_A[29]AC6

VCC1_5_A[30]AC7

VCCSUS3_3[20]T7

CORE

VCCA3GP

ATX

ARX

USB CORE

PCI

GLAN POWER

VCCP_CORE

VCCPSUS

VCCPUSB

U7F1F

ICH9M REV 1.0

CORE

VCCA3GP

ATX

ARX

USB CORE

PCI

GLAN POWER

VCCP_CORE

VCCPSUS

VCCPUSB

U7F1F

ICH9M REV 1.0

C7V80.1uF

.10%SMC0402

C7V80.1uF

.10%SMC0402

R7G14 0.002R7G14 0.002

C7V70.1uF

.10%SMC0402

C7V70.1uF

.10%SMC0402

R7H1 0.002R7H1 0.002

C7V50.1uF

.10%SMC0402

C7V50.1uF

.10%SMC0402

C7U50.1uF

.10%

SMC0402

C7U50.1uF

.10%

SMC0402

FB6G1

330ohm@100MHz

FB6G1

330ohm@100MHz

C7F42.2uF

.SMC0603

C7F42.2uF

.SMC0603

C7G31.0uF

.402

C7G31.0uF

.402

R7F10

.

R7F10

.

C7U60.1uF

.10%SMC0402

C7U60.1uF

.10%SMC0402

R6G3 0.002R6G3 0.002

C7U100.1uF

NO_STUFF10%

SMC0402

C7U100.1uF

NO_STUFF10%

SMC0402

C7V120.1uF

.10%SMC0402

C7V120.1uF

.10%SMC0402

C7V44.7uF

.10%

C7V44.7uF

.10%

C6G2220uFC6G2220uF

C7V100.1uF

.10%SMC0402

C7V100.1uF

.10%SMC0402

R7U16105%

R7U16105%

1 2

L7F1

1uH

L7F1

1uH

R6U9 0.002R6U9 0.002

C7V90.1uF

.10%SMC0402

C7V90.1uF

.10%SMC0402

R8V5105%

R8V5105%

R6F9 0.002R6F9 0.002

R7F4 0.002R7F4 0.002

R7V17 0.022R7V17 0.022

C7U70.1uF

NO_STUFF10%

SMC0402

C7U70.1uF

NO_STUFF10%

SMC0402

C6V50.1uF

.10%SMC0402

C6V50.1uF

.10%SMC0402

C6G122uF

.

C6G122uF

.

1

3

CR7U1BAT54CR7U1BAT54

C7U160.1uF

.10%SMC0402

C7U160.1uF

.10%SMC0402

C7V110.1uF

.10% SMC0402

C7V110.1uF

.10% SMC0402

R7F2 0.002R7F2 0.002

C7G40.1uF

.10%SMC0402

C7G40.1uF

.10%SMC0402

VSS[1]AA26

VSS[2]AA27

VSS[3]AA3

VSS[4]AA6

VSS[5]AB1

VSS[6]AA23

VSS[7]AB28

VSS[8]AB29

VSS[9]AB4

VSS[10]AB5

VSS[11]AC17

VSS[12]AC26

VSS[13]AC27

VSS[14]AC3

VSS[15]AD1

VSS[16]AD10

VSS[17]AD12

VSS[18]AD13

VSS[19]AD14

VSS[20]AD17

VSS[21]AD18

VSS[22]AD21

VSS[23]AD28

VSS[24]AD29

VSS[25]AD4

VSS[26]AD5

VSS[27]AD6

VSS[28]AD7

VSS[29]AD9

VSS[30]AE12

VSS[31]AE13

VSS[32]AE14

VSS[33]AE16

VSS[34]AE17

VSS[35]AE2

VSS[36]AE20

VSS[37]AE24

VSS[38]AE3

VSS[39]AE4

VSS[40]AE6

VSS[41]AE9

VSS[42]AF13

VSS[43]AF16

VSS[44]AF18

VSS[45]AF22

VSS[46]AH26

VSS[47]AF26

VSS[48]AF27

VSS[49]AF5

VSS[50]AF7

VSS[51]AF9

VSS[52]AG13

VSS[53]AG16

VSS[54]AG18

VSS[55]AG20

VSS[56]AG23

VSS[57]AG3

VSS[58]AG6

VSS[59]AG9

VSS[60]AH12

VSS[61]AH14

VSS[62]AH17

VSS[63]AH19

VSS[64]AH2

VSS[65]AH22

VSS[66]AH25

VSS[67]AH28

VSS[68]AH5

VSS[69]AH8

VSS[70]AJ12

VSS[71]AJ14

VSS[72]AJ17

VSS[73]AJ8

VSS[74]B11

VSS[75]B14

VSS[76]B17

VSS[77]B2

VSS[78]B20

VSS[79]B23

VSS[80]B5

VSS[81]B8

VSS[82]C26

VSS[83]C27

VSS[84]E11

VSS[85]E14

VSS[86]E18

VSS[87]E2

VSS[88]E21

VSS[89]E24

VSS[90]E5

VSS[91]E8

VSS[92]F16

VSS[93]F28

VSS[94]F29

VSS[95]G12

VSS[96]G14

VSS[97]G18

VSS[99]G24

VSS[100]G26

VSS[101]G27

VSS[102]G8

VSS[103]H2

VSS[104]H23

VSS[105]H28

VSS[106]H29

VSS[107]H5

VSS[108]J23

VSS[109]J26

VSS[110]J27

VSS[111]AC22

VSS[112]K28

VSS[113]K29

VSS[114]L13

VSS[115]L15

VSS[116]L2

VSS[117]L26

VSS[118]L27

VSS[119]L5

VSS[120]L7

VSS[121]M12

VSS[122]M13

VSS[123]M14

VSS[124]M15

VSS[125]M16

VSS[126]M17

VSS[127]M23

VSS[128]M28

VSS[129]M29

VSS[130]N11

VSS[131]N12

VSS[132]N13

VSS[133]N14

VSS[134]N15

VSS[135]N16

VSS[136]N17

VSS[137]N18

VSS[138]N26

VSS[139]N27

VSS[140]P12

VSS[141]P13

VSS[142]P14

VSS[143]P15

VSS[144]P16

VSS[145]P17

VSS[146]P2

VSS[147]P23

VSS[148]P28

VSS[149]P29

VSS[150]P4

VSS[151]P7

VSS[152]R11

VSS[153]R12

VSS[154]R13

VSS[155]R14

VSS[156]R15

VSS[157]R16

VSS[158]R17

VSS[159]R18

VSS[160]R28

VSS[161]T12

VSS[162]T13

VSS[163]T14

VSS[164]T15

VSS[165]T16

VSS[166]T17

VSS[167]T23

VSS[169]U12

VSS[170]U13

VSS[171]U14

VSS[172]U15

VSS[173]U16

VSS[174]U17

VSS[175]AD23

VSS[176]U26

VSS[177]U27

VSS[178]U3

VSS_NCTF[1]A1

VSS_NCTF[2]A2

VSS_NCTF[3]A28

VSS_NCTF[4]A29

VSS_NCTF[5]AH1

VSS_NCTF[6]AH29

VSS_NCTF[7]AJ1

VSS_NCTF[8]AJ2

VSS_NCTF[9]AJ28

VSS_NCTF[10]AJ29

VSS_NCTF[11]B1

VSS_NCTF[12]B29

VSS[179]V1

VSS[180]V13

VSS[181]V15

VSS[182]V23

VSS[183]V28

VSS[98]G21

VSS[184]V29

VSS[185]V4

VSS[186]V5

VSS[187]W26

VSS[188]W27

VSS[189]W3

VSS[190]Y1

VSS[191]Y28

VSS[192]Y29

VSS[193]Y4

VSS[194]Y5

VSS[195]AG28

VSS[196]AH6

VSS[197]AF2

VSS[168]B26

VSS[198]B25

U7F1E

ICH9M REV 1.0

U7F1E

ICH9M REV 1.0

C7U130.1uF

NO_STUFF10%

SMC0402

C7U130.1uF

NO_STUFF10%

SMC0402C7U90.1uF

.10%SMC0402

C7U90.1uF

.10%SMC0402

C7U120.1uF

.10%SMC0402

C7U120.1uF

.10%SMC0402

C7U80.1uF

.10%SMC0402

C7U80.1uF

.10%SMC0402

FB7V1

5ohm@100MHz

FB7V1

5ohm@100MHz

C7U172.2uF

.SMC0603

C7U172.2uF

.SMC0603

C7U150.1uF

.10%SMC0402

C7U150.1uF

.10%SMC0402

R7G9 0.002R7G9 0.002

R7F5 0.002R7F5 0.002

C7V20.1uF

.10%SMC0402

C7V20.1uF

.10%SMC0402

C7G61.0uF

.402

C7G61.0uF

.402

C7V34.7uF

.10%

C7V34.7uF

.10%

C7G20.1uF

.10%SMC0402

C7G20.1uF

.10%SMC0402

C7G710uF

.20%SMC0805

C7G710uF

.20%SMC0805

1 2

L6G1

1uH

L6G1

1uH

C7U110.1uF

.10% SMC0402

C7U110.1uF

.10% SMC0402

www.laptop-schematics

.com

Page 25: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCIESLOT1_PRSNT#1

SMB_CLK_A1

PCIESLOT2_PRSNT#1

PCIE_WAKE# PLT_RST#

SMB_DATA_A1

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V12S26,30,31,32,43,55,57

+V12S_PCIESLOT2

+V3.3S_PCIESLOT1

+V12S26,30,31,32,43,55,57

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3S_PCIESLOT1

+V12S_PCIESLOT1

+V12S_PCIESLOT1

+V3.3S_PCIESLOT1

+V12S_PCIESLOT2+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S_PCIESLOT2

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3S_PCIESLOT1

+V12S_PCIESLOT2

+V3.3S_PCIESLOT2

+V12S_PCIESLOT1

+V3.3S_PCIESLOT2+V3.3S_PCIESLOT2

SMB_CLK_A123,26,32,44SMB_DATA_A123,26,32,44

CLK_PCIE_SLOT2# 36

PLT_RST# 7,19,22,26,38,41,57

CLK_PCIE_SLOT1 36CLK_PCIE_SLOT1# 36

CLK_PCIE_SLOT2 36

PCIE_TXP1_SLOT122PCIE_TXN1_SLOT122

PCIE_TXP2_SLOT222PCIE_TXN2_SLOT222

PCIE_RXP1_SLOT1 22PCIE_RXN1_SLOT1 22

PCIE_RXP2_SLOT2 22PCIE_RXN2_SLOT2 22

PCIE_WAKE#19,23,26,44

CLK_SLOT1_OE#36

CLK_SLOT2_OE#36

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCI-E Slots (1 & 2)

25 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCI-E Slots (1 & 2)

25 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCI-E Slots (1 & 2)

25 58Tuesday, August 28, 2007

SLOT 2

NOTE: SLOTS 1 AND 2ARE PHYSICALY IN-LINE

SLOT 1

C7B100.1uF

.10%

C7B100.1uF

.10%

R7R10.002

.

1%

R7R10.002

.

1%

R7D1410K

.

5%

R7D1410K

.

5%

C6D30.1uF

.10%

C6D30.1uF

.10%

C6C120.1uF10%.

C6C120.1uF10%.

R7N50.002

.

1%

R7N50.002

.

1%C6B130.1uF

.10%

C6B130.1uF

.10%

C7D20.1uF

.10%

C7D20.1uF

.10%

+12V1B1

+12V2B2

RSVD1B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

+3.3V1B8

JTAGB9

3.3VAUXB10

WAKE#B11

RSVD2B12

GND3B13

HSOP_0B14

HSON_0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

+12V3A2

+12V4A3

GND6A4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PWRGDA11

GND7A12

REFCLK+A13

REFCLK-A14

GND8A15

HSLP_0A16

HSLN_0A17

GND9A18

Key

J6D1

PCIE_X1

Key

J6D1

PCIE_X1

C7D30.1uF

.10%

C7D30.1uF

.10%

C7B140.1uF

.10%

C7B140.1uF

.10%

R7C200.002

.

1%

R7C200.002

.

1%

C7B60.1uF10%.

C7B60.1uF10%.

+12V1B1

+12V2B2

RSVD1B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

+3.3V1B8

JTAGB9

3.3VAUXB10

WAKE#B11

RSVD2B12

GND3B13

HSOP_0B14

HSON_0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

+12V3A2

+12V4A3

GND6A4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PWRGDA11

GND7A12

REFCLK+A13

REFCLK-A14

GND8A15

HSLP_0A16

HSLN_0A17

GND9A18

Key

J6B1

PCIE_X1

Key

J6B1

PCIE_X1

R7R60

.

R7R60

.

C7D122uFC7D122uF

R6B20

.

R6B20

.

C6B40.1uF10%.

C6B40.1uF10%.

R7C310K

.

5%

R7C310K

.

5%

C6B1022uFC6B1022uF

C7B1622uFC7B1622uF

C7C122uFC7C122uF

C7D422uFC7D422uF

R7N60.002

.

1%

R7N60.002

.

1%C7B822uFC7B822uF

C7C30.1uF10%.

C7C30.1uF10%.

www.laptop-schematics

.com

Page 26: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCIESLOT3_PRSNT1#

PCIESLOT5_PRSNT1#

PCIESLOT4_A6PCIESLOT4_A8PCIESLOT4_A5

SMB_DATA_A1

PLT_RST#

SMB_CLK_A1 PCIESLOT4_A5

PCIESLOT4_PRSNT1#

PCIE_WAKE#

SMB_DATA_A1

PLT_RST#

SMB_CLK_A1

PCIE_WAKE#

PCIESLOT4_A6

PCIESLOT4_A8

VAUX4_OK#

VAUX4_G_SWITCH

VAUX3_OK#

VAUX3_G_SWITCH

+V12S_PCIESLOT3

+V12S_PCIESLOT4

+V12S_PCIESLOT3

+V3.3_PCIESLOT3

+V12S_PCIESLOT4

+V3.3_PCIESLOT3

+V3.3_PCIESLOT3

+V3.3_PCIESLOT3

+V3.3_PCIESLOT4

+V3.3S

+V12S_PCIESLOT3

+V12S25,30,31,32,43,55,57

+V3.3S

+V12S25,30,31,32,43,55,57

+V12S_PCIESLOT4

+V3.3S_PCIESLOT5

+V3.3A

+V12S25,30,31,32,43,55,57

+V3.3S_PCIESLOT5

+V3.3S_PCIESLOT5

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S_PCIESLOT5

+V12S_PCIESLOT5+V12S_PCIESLOT5

+V12S_PCIESLOT5

+V3.3_PCIE_VAUX_SLOT4

+V3.3_PCIE_VAUX_SLOT4

+V3.3A19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+VBATA45,46,47,56,57

+V3.3A19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3_PCIE_VAUX_SLOT4

+V3.3_PCIE_VAUX_SLOT3

+V3.3_PCIE_VAUX_SLOT3

+V3.3A

+VBATA45,46,47,56,57

+V3.3A

+V3.3_PCIESLOT4

+V3.3_PCIESLOT4

+V3.3_PCIESLOT4

+V3.3_PCIE_VAUX_SLOT3

CL_CLK1 23CL_DATA1 23CL_RST#1 23

SMB_CLK_A123,25,32,44SMB_DATA_A123,25,32,44

CLK_PCIE_SLOT4 36PCIE_TXP4_SLOT422

PCIE_TXN4_SLOT422

CLK_PCIE_SLOT3# 36CLK_PCIE_SLOT3 36

CLK_PCIE_SLOT4# 36

PCIE_TXP3_SLOT322PCIE_TXN3_SLOT322

PLT_RST# 7,19,22,25,38,41,57

PCIE_TXN5_SLOT522

PCIE_TXP5_SLOT522CLK_PCIE_SLOT5 36CLK_PCIE_SLOT5# 36

EC_PCIE_SLOT4_VAUX_ON40

EC_PCIE_SLOT3_VAUX_ON41

PCIE_WAKE#19,23,25,44

PCIE_RXP4_SLOT4 22

CLK_SLOT3_OE#36

CLK_SLOT4_OE#36

PCIE_RXP3_SLOT3 22PCIE_RXN3_SLOT3 22

CLK_SLOT5_OE#36 PCIE_RXN5_SLOT5 22PCIE_RXP5_SLOT5 22

PCIE_RXN4_SLOT4 22

PCIE_RSVD_1#

PCIE_RSVD_2#

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCI-E Slots (3,4 & 5)

26 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCI-E Slots (3,4 & 5)

26 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PCI-E Slots (3,4 & 5)

26 58Tuesday, August 28, 2007

SLOT 4

NOTE: SLOTS 3 AND 4ARE PHYSICALY IN-LINE SLOT 3

SLOT 5

PCIe Slot3 VAUX Control

PCIe Slot4 VAUX Control

Upham 4 Support: STUFF R8B5 and NO_STUFF R7C1Upham 3 and Conventional PCIe card support(Default): STUFF R7C1 and NO_STUFF R8B5

NOTE: Remove Resistors in case a JTAG-capable PCIE card is to be inserted in Slot 4

Upham 4 Support: STUFF R8D3 and NO_STUFF R8D2Upham 3 and Conventional PCIe card support(Default): STUFF R8D2 and NO_STUFF R8D3

C8B70.1uF

.10%

C8B70.1uF

.10%

C8B422uFC8B422uF

C7B90.1uF

.10%

C7B90.1uF

.10%

R7P5100KR7P5100K

R8B8100KR8B8100K

+12V1B1

+12V2B2

RSVD1B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

+3.3V1B8

JTAGB9

3.3VAUXB10

WAKE#B11

RSVD2B12

GND3B13

HSOP_0B14

HSON_0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

+12V3A2

+12V4A3

GND6A4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PWRGDA11

GND7A12

REFCLK+A13

REFCLK-A14

GND8A15

HSLP_0A16

HSLN_0A17

GND9A18

Key

J8B3

PCIE_X1

Key

J8B3

PCIE_X1

R7N40.002

.

1%

R7N40.002

.

1%

C8B80.01UF.

10%

C8B80.01UF.

10%

R8D510K

.

5%

R8D510K

.

5%

R7P6100KR7P6100K

R7N30

.

R7N30

.

C8B90.1uF

.10%

C8B90.1uF

.10%

4

5678

3

12

Q7R1IRF7822

.

Q7R1IRF7822

.

R7P130

.

R7P130

.

R7P4100KR7P4100K

C8B60.1uF

.10%

C8B60.1uF

.10%

R8B20.002

.

1%

R8B20.002

.

1%

R7D120

.

R7D120

.

R8B7100KR8B7100K

3

1

2

Q8N2BSS138

.

Q8N2BSS138

.

R8B6100KR8B6100K

R7C10.002

.

1%

R7C10.002

.

1%

R8B50.002

NO_STUFF

1%

R8B50.002

NO_STUFF

1%R8B40

.

R8B40

.

C8C40.1uF10%.

C8C40.1uF10%.

4

5678

3

12

Q8B1IRF7822

.

Q8B1IRF7822

.

R7D200

.

R7D200

.

R8D20.002

.

1%

R8D20.002

.

1%

C8C30.1uF10%.

C8C30.1uF10%.

C8D30.1uF

.10%

C8D30.1uF

.10%

C7B1522uFC7B1522uF

R7C210K

.

5%

R7C210K

.

5%

C8B30.1uF10%.

C8B30.1uF10%.

+12V1B1

+12V2B2

RSVD1B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

+3.3V1B8

JTAGB9

3.3VAUXB10

WAKE#B11

RSVD2B12

GND3B13

HSOP_0B14

HSON_0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

+12V3A2

+12V4A3

GND6A4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PWRGDA11

GND7A12

REFCLK+A13

REFCLK-A14

GND8A15

HSLP_0A16

HSLN_0A17

GND9A18

Key

J8D1

PCIE_X1

Key

J8D1

PCIE_X1

3

1

2

Q7P1BSS138

.

Q7P1BSS138

.

C7B120.1uF

.10%

C7B120.1uF

.10%

R7N20.002

.

1%

R7N20.002

.

1%

C8D122uFC8D122uF

C7B1322uFC7B1322uF

C8D40.1uF

.10%

C8D40.1uF

.10%

C7B422uFC7B422uF

+12V1B1

+12V2B2

RSVD1B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

+3.3V1B8

JTAGB9

3.3VAUXB10

WAKE#B11

RSVD2B12

GND3B13

HSOP_0B14

HSON_0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

+12V3A2

+12V4A3

GND6A4

JTAG2A5

JTAG3A6

JTAG4A7

JTAG5A8

+3.3V2A9

+3.3V3A10

PWRGDA11

GND7A12

REFCLK+A13

REFCLK-A14

GND8A15

HSLP_0A16

HSLN_0A17

GND9A18

Key

J7B1

PCIE_X1

Key

J7B1

PCIE_X1

C8C222uFC8C222uF

C7R10.01UF.

10%

C7R10.01UF.

10%

3

1

2

Q8N1BSS138

.

Q8N1BSS138

.

C7B1722uFC7B1722uF

C7B50.1uF10%.

C7B50.1uF10%.

C8D20.1uF

.10%

C8D20.1uF

.10%

R8C30.002

.

1%

R8C30.002

.

1%

R8C110K

.

5%

R8C110K

.

5%

R7D130

.

R7D130

.

3

1

2

Q7P2BSS138

.

Q7P2BSS138

.

C8N422uFC8N422uF

C7B70.1uF10%.

C7B70.1uF10%.

C7B110.1uF

.10%

C7B110.1uF

.10%

C8B50.1uF10%.

C8B50.1uF10%.

R8D30.002

NO_STUFF

1%

R8D30.002

NO_STUFF

1%C8D522uFC8D522uF

www.laptop-schematics

.com

Page 27: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VBATS_HDA_R1

HDA_CODEC_0_1_2_CLK HDA_MDC_BITCLK

HDA_MDC_SYNCHDA_MDC_SDOHDA_CODEC_0_1_2_SDATAOUT

HDA_MDC_RST#HDA_CODEC_0_1_2_RST#

HDA_CODEC_3_RST#

HDA_CODEC_0_1_2_SYNC

HDA_CODEC_3_SYNC

HDA_CODEC_0_1_2_RST#

HDA_CODEC_0_1_2_SYNC

HDA_MDC_SDATAIN1

HDA_MDC_SDATAIN2

HDA_AUDIO_PWRDN_NET

HDA_MDC_SDATAIN3

HDA_SDIN2

HDA_CODEC_3_SDATAOUT

HDA_CODEC_0_1_2_SDATAOUT

HDA_CODEC_3_CLK

HDA_CODEC_0_1_2_CLK

HDA_DOCK_SDATAIN

HDA_CODEC_3_SDATAOUT

HDA_CODEC_3_CLKHDA_CODEC_3_RST#

+VBATS_HDA_R2

HDA_CODEC_3_SYNC

HDA_SDIN3_R2

HDA_SDIN3_R1HDA_SDIN3

HDA_SDIN2_RHDA_SDIN2

HDA_CODEC_0_1_2_CLK

HDA_DOCK_EN#

HDA_DOCK_EN#

HDA_DOCK_SDATAIN

HDA_DOCK_EN#_J

HDA_BCLK_R

HDA_SDO_RHDA_SYNC_R

HDA_CODEC_0_1_2_SYNC HDA_CODEC_0_1_2_SDATAOUT

HDA_SPKR_R

+V3.3A19,21,23,24,25,26,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V5 32,42,43,48,52,55,56,57

+VBATS16,19,30,31,55,57

+V3.3A_1.5A_HDA_IO24,28,44

+V3.319,32,39,41,42,43,55,57

+VBATS16,19,30,31,55,57

+V5 32,42,43,48,52,55,56,57

+V3.319,32,39,41,42,43,55,57

+V3.3A_1.5A_HDA_IO24,28,44

+V3.3S_1.5S_HDA_IO21,24,28

+V3.3S_1.5S_HDA_IO21,24,28 +V3.3S_1.5S_HDA_IO21,24,28

HDA_SPKR 23,44

HDA_DOCK_EN# 21,41HDA_DOCK_RST#21,44

HDA_RST#7,21

HDA_SYNC7,21

HDA_SDOUT7,21

HDA_BIT_CLK7,21

HDA_SDATAIN_DOCK 44

HDA_SDIN121

HDA_SDIN221

HDA_SDIN021

HDA_SDIN37,21

HDA_BCLK_DOCK 44

HDA_SDO_DOCK 44HDA_SYNC_DOCK 44

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

High Definition Audio

A

27 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

High Definition Audio

A

27 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

High Definition Audio

A

27 58Tuesday, August 28, 2007

Layout Note:Place both headers in-line andexactly 200 mils from each other,pin-to-pin. Draw one silkscreenbox around both parts.

HDA Header for MDC Interposer

HDA Docking Circuit

HDA Header for External HDMI Support

ICH

13x2 HeaderDocking Connector

8x2 Header

GMCH

**

*

**

**Note: Place the resistors "*" as

Marked in the Diagram

***

Layout Toplogy for HDA Clk,Sync,RST,SDout,Enable

These Resistors need to be Mountedappropriately when SDIN2 & SDIN3 need to gettested using the MDC.

To use iHDMI,Must STUFF: R7V23, R7V8, R7V3, R7V4, R5F9.Must NO_STUFF: R7G3, R7G2, R7V7, R7G11, R9E13, R9E10, R9E14, R9E12, R9E8,

To use eHDMI (on SDIN3)Must NO_STUFF: R7V23, R7V8, R7V3, R7V4, R5F9, R9E14, R9E12, R9E8, Must STUFF: R7G3, R7G2, R7V7, R7G11, ONE of R9E13 OR R9E10 depending on the add-in-card.

R9D7 33R9D7 33

R9E1610K

.

5%

R9E1610K

.

5%

R7G11 33R7G11 33

2468

13

79111315

10121416

J9E22X8_HDR_KEY12

J9E22X8_HDR_KEY12

R7G2 33R7G2 33

OE#1

A2

GND3

Y4

NC5

VCC6

U9D1

NC7SV125L

U9D1

NC7SV125L

R9D620KR9D620K

R9E80NO_STUFF

R9E80NO_STUFF

R7G3 33R7G3 33

R9E170

.

R9E170

.

R6C20

.

R6C20

.

R9E110

.

R9E110

.

R9E6 33R9E6 33

R7G40

.

R7G40

.

R9E130NO_STUFF

R9E130NO_STUFF

OE#1

A2

GND3

Y4

NC5

VCC6

U9D2

NC7SV125L

U9D2

NC7SV125L

C9D40.1uF20%

C9D40.1uF20%

OE#1

A2

GND3

Y4

NC5

VCC6

U9E1

NC7SV125L

U9E1

NC7SV125L

R9E3 33R9E3 33

R9E100NO_STUFF

R9E100NO_STUFF

R9N320KR9N320K

R9D8 33R9D8 33

R9D3 33R9D3 33

R9E140NO_STUFF

R9E140NO_STUFF

R9E90

.

R9E90

.

R7V20

.

R7V20

.

C9D30.1uF20%

C9D30.1uF20%

OE1#1

1A2

1B3

GND4

2A5

2B6

OE2#7

VCC8

U9B2

74CBT3306

U9B2

74CBT3306

R9E120

.

R9E120

.

R7V7 33R7V7 33

2468

13

79111315

10121416

J6C2

2X8_HDR_KEY12

J6C2

2X8_HDR_KEY12

R7V60

.

R7V60

.

R9E150

.

R9E150

.

R9E2 33R9E2 33

C9B30.1uF20%

C9B30.1uF20%

R7G100

.

R7G100

.

R9E70

.

R9E70

.

C9E10.1uF20%

C9E10.1uF20%

1 23 45 67 8

J9E48Pin HDR

J9E48Pin HDR

R9E120KR9E120K

R9N20

NO_STUFF

R9N20

NO_STUFF

R9D4 33R9D4 33

R9E420KR9E420K

www.laptop-schematics

.com

Page 28: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDA_IO_ADJ

SC

1563_S

HD

N

+V3.3A19,21,23,24,25,26,27,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A +V1.5A_HDA_IO+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S_1.5S_HDA_IO21,24,27

+V1.5A_HDA_IO

+V3.3A_1.5A_HDA_IO24,27,44

+V3.3A19,21,23,24,25,26,27,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V1.5S4,10,11,24,47,55,57

VR_ALW_ENABLE45,56

+V5S

+V1.5S_LDO_QDAC10

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

HDA Power Supply

A

28 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

HDA Power Supply

A

28 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

HDA Power Supply

A

28 58Tuesday, August 28, 2007

Layout Notes:Place the Two Resistors Nextto each Other

Layout Notes:Place the Two Resistors Nextto each Other

Selection of I/O Voltage for the High Definition Audio

Power Supply for High Definiton Audio

R8T210K

.

5%

R8T210K

.

5%

3

1

2

Q8T1BSS138Q8T1BSS138

R8T410K1%

R8T410K1%

R7H2 0.002

NO_STUFF

1%R7H2 0.002

NO_STUFF

1%

3

46521

Q8D1SI3442BDV

Q8D1SI3442BDV

C8T222uFC8T222uF

R8T5100R8T5100

SHDN1

IN5

OUT4

GND

2

ADJ

3

U8E1 SC1563U8E1 SC1563

R8E8 0.002

NO_STUFF

1%R8E8 0.002

NO_STUFF

1%

C8E10.1uF

.10%

C8E10.1uF

.10%

R7H3 0.0021%

R7H3 0.0021%

C8T11.0uF10%

C8T11.0uF10%

C8D60.01UF.

10%

C8D60.01UF.

10%

R8T12.55K

.1%

R8T12.55K

.1%

R8E7 0.0021%

R8E7 0.0021%

www.laptop-schematics

.com

Page 29: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USBE+USBE-

+V5A_USBPWR_PN8

EN2_EEN1_E +V5A_USBPWR_PN10

USBA-

EN1_B

+V5A_USBPWR_PN0

USBC-

EN1_A+V5A_USBPWR_IN3

+V5A_USBPWR_PN4

EN2_A

EN2_B

+V5A_USBPWR_PN2

+V5A_USBPWR_IN3

+V5A_USBPWR_IN3

+V5A_USBPWR_IN2EN1_DEN2_D

+V5A_USBPWR_PN5_PN7 +V5A_L_USBPWR_PN5_PN7

+V5A_USBPWR_IN1 +V5A_USBPWR_PN1_PN3 +V5A_L_USBPWR_PN1_PN3

EN2_CEN1_C

+V5A_L_USBPWR_PN10

+V5A_L_USBPWR_PN0

USBA+

USBB-USBB+

USBC+

USBD-USBD+

+V5A_L_USBPWR_PN5_PN7

+V5A_L_USBPWR_PN2

+V5A_L_USBPWR_PN8

+V5A_L_USBPWR_PN6

+V5A_L_USBPWR_PN4+V5A_USBPWR_PN6

USBF+USBF-

+V5A_L_USBPWR_PN1_PN3

+V5A_L_USBPWR_PN9_PN11

+V5A_USBPWR_IN4EN1_FEN2_F

+V5A_L_USBPWR_PN9_PN11+V5A_USBPWR_PN9_PN11USB_OC#9_R_2052

+V3.3A19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V5A 24,34,38,44,46,47,50,51,56,57

+V5A 24,34,38,44,46,47,50,51,56,57

+V5A 24,34,38,44,46,47,50,51,56,57

+V3.3A19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A

+V3.3A

USB_PN022

USB_PP022

USB_PN7 22USB_PP7 22

+V3.3A+V3.3A

+V5A 24,34,38,44,46,47,50,51,56,57

USB_PN9_R_FPIO22

USB_PP9_R_FPIO22

+V3.3A

USB_PN222

USB_PP222

USB_PN422

USB_PP422

USB_PP622

USB_PN622

USB_PN822

USB_PP822

USB_PN1022

USB_PP1022

USB_PN122USB_PP122

USB_PN3 22USB_PP3 22

USB_PN522USB_PP522

USB_PN11 22USB_PP11 22

USB_OC#10 22

USB_OC#8 22

USB_OC#4 22

USB_OC#0 22

USB_OC#2 22

USB_OC#5 22

USB_OC#7 22

USB_OC#3 22

USB_OC#1 22

USB_OC#622USB_OC#9 22

USB_OC#11 22

+V5A24,34,38,44,46,47,50,51,56,57

+V5A24,34,38,44,46,47,50,51,56,57

+V5A24,34,38,44,46,47,50,51,56,57

+V5A24,34,38,44,46,47,50,51,56,57

+V5A24,34,38,44,46,47,50,51,56,57

+V5A24,34,38,44,46,47,50,51,56,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

USB 1.1/2.0

29 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

USB 1.1/2.0

29 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

USB 1.1/2.0

29 58Tuesday, August 28, 2007

Back of ChassisFPIO/DuckbayBack of ChassisFPIO/DuckbayBack of ChassisFPIO/DuckbayBack of ChassisFPIO/DuckbayBack of ChassisDocking/FPIO/DuckbayBack of ChassisFPIO/Duckbay

USB Port LocationUSB Port Routing Locations

USB Port 0USB Port 1 USB Port 2 USB Port 3 USB Port 4USB Port 5 USB Port 6 USB Port 7USB Port 8USB Port 9USB Port 10USB Port 11

RJ45 1000 with Dual

USB Connector

Layout Note:Place ESD diodes asclose to the connectoras possible.

Need to have minimum of 150mil clearance step down stencil definition around the ESD diodes CM1230 in layout too. Step down stencil area can accomodate other components. If needed, area for step down stencil definition can even be extended to cover other nearby components to avoid step down area covering the components half way, meaning, if extended step down area should cover other nearby coponents fullly.

LAYOUT NOTE FOR ESD DIODE: CM1230

Header-1: FPIO - Port 1, 3

Header-2: FPIO - Port 5, 7

Header-1

Header-2

USB Header USB Port PCIESlotHeader-1 Port 1 & Port 3 Slot 1 & Slot 2Header-2 Port 5 & Port 7 Slot 3 & Slot 4

USB FPIO Header to PCIe connector mapping

Quadraple USB

Connector

Header-3 Port 9 & Port 11

Header-3

Header-3: FPIO - Port 9, 11

Ports 0,2,4,6

Ports 8,10

EHCI

0

1

FB6H2

50OHM

FB6H2

50OHM

ESD_CH1A2

V+B2

V-A1

ESD_CH2B1

U3A2

CM1230_02

U3A2

CM1230_02

VCC11

P0#2

P03

GND14

VCC25

P1#6

P17

GND28

J5A1B

RJ45 1000 WITH DUAL USB

J5A1B

RJ45 1000 WITH DUAL USB

R7W410K5%

R7W410K5%

2 3

1 4

L5B1

90@100MHz

L5B1

90@100MHz

C5W90.1uF10%.

C5W90.1uF10%.

R5W181K

.

R5W181K

.

R3B101K

.

R3B101K

.

ESD_CH1A2

V+B2

V-A1

ESD_CH2B1

U5A1

CM1230_02

U5A1

CM1230_02

2 3

1 4

L3B1

90@100MHz

L3B1

90@100MHz

27

RP3B1B10KRP3B1B10K

27

RP5W1B10KRP5W1B10K

C6H3470PFC6H3470PF

R6W21K

.

R6W21K

.

GND1

IN2

EN13

EN24

OC2#5

OUT26

OUT17

OC1#8

U7H2

TPS2052B

U7H2

TPS2052B

2 3

1 4

L5B2

90@100MHz

L5B2

90@100MHz

2 3

1 4

L3B4

90@100MHz

L3B4

90@100MHz

ESD_CH1A2

V+B2

V-A1

ESD_CH2B1

U5B1

CM1230_02

U5B1

CM1230_02

FB7H1

50OHM

FB7H1

50OHM

13 4

2

57

1086

J6J1

USB_2X5-Header

J6J1

USB_2X5-Header

+ C4A3220uF20%.

+ C4A3220uF20%.

+ C6H1220uF20%.

+ C6H1220uF20%.

+ C3A3220uF20%.

+ C3A3220uF20%.

FB6H1

50OHM

FB6H1

50OHM

C3B40.1uF20%

C3B40.1uF20%

GND1

IN2

EN13

EN24

OC2#5

OUT26

OUT17

OC1#8

U3N1

TPS2052B

U3N1

TPS2052B

GND1

IN2

EN13

EN24

OC2#5

OUT26

OUT17

OC1#8

U5H4

TPS2052B

U5H4

TPS2052B

GND1

IN2

EN13

EN24

OC2#5

OUT26

OUT17

OC1#8

U4A2

TPS2052B

U4A2

TPS2052B

C3M2

470PF

C3M2

470PF

13 4

2

57

1086

J6H4

USB_2X5-Header

J6H4

USB_2X5-Header

R4M51K

.

R4M51K

.

+ C3A1220uF20%.

+ C3A1220uF20%.

C6W7470PFC6W7470PF

FB4M1

50OHM

FB4M1

50OHM

R7H50.0021%

R7H50.0021%

C7H50.1uF10%.

C7H50.1uF10%.

2 3

1 4

L3B2

90@100MHz

L3B2

90@100MHz

FB3M1 50OHMFB3M1 50OHM

FB3N1

50OHM

FB3N1

50OHM

+ C7J1220uF20%.

+ C7J1220uF20%.

R5W150.0021%

R5W150.0021%

+ C3B2220uF20%.

+ C3B2220uF20%.

+ C3A2220uF20%.

+ C3A2220uF20%.

C3M1

470PF

C3M1

470PF

R7H150.0021%

R7H150.0021%

R4A310K5%

R4A310K5%

45

RP5W1D10KRP5W1D10K

ESD_CH1A2

V+B2

V-A1

ESD_CH2B1

U3A3

CM1230_02

U3A3

CM1230_02

C4M3470PFC4M3470PF

C3M6470PFC3M6470PF

R4M61K

.

R4M61K

.

C4M7470PFC4M7470PF

C4M50.1uF20%

C4M50.1uF20%

R7W61K

.

R7W61K

.

R3B30.0021%

R3B30.0021%

18

RP5W1A10KRP5W1A10K

FB4M2

50OHM

FB4M2

50OHM

C3N1470PFC3N1470PF

R7W10

NO_STUFF

5%

R7W10

NO_STUFF

5%

FB3N2

50OHM

FB3N2

50OHM

R3B71K

.

R3B71K

.

ESD_CH1A2

V+B2

V-A1

ESD_CH2B1

U3A4

CM1230_02

U3A4

CM1230_02

ESD_CH1A2

V+B2

V-A1

ESD_CH2B1

U3A1

CM1230_02

U3A1

CM1230_02

R3B81K

.

R3B81K

.

C6J1470PFC6J1470PF

36

RP3B1C10KRP3B1C10K

VCC141

P#042

P043

GND144

VCC231

P#132

P133

GND234

VCC321

P#222

P223

GND324

GND51

GND62

GND73

VCC411

P#312

P313

GND414

GND84

GND95

GND106

TOPPORT

UPPERMIDDLEPORT

LOWERMIDDLEPORT

BOTTOMPORT

J3A1

QUAD_stack_USB

TOPPORT

UPPERMIDDLEPORT

LOWERMIDDLEPORT

BOTTOMPORT

J3A1

QUAD_stack_USB

+ C4A6220uF20%.

+ C4A6220uF20%.

GND1

IN2

EN13

EN24

OC2#5

OUT26

OUT17

OC1#8

U6H2

TPS2052B

U6H2

TPS2052B

FB3N3 50OHMFB3N3 50OHM

R7W210K5%

R7W210K5%

2 3

1 4

L3B3

90@100MHz

L3B3

90@100MHz

C3B30.1uF20%

C3B30.1uF20%

R6W31K

.

R6W31K

.

R3B91K

.

R3B91K

.

18

RP3B1A10KRP3B1A10K

13 4

2

57

1086

J6H2

USB_2X5-Header

J6H2

USB_2X5-Header

45

RP3B1D

10K

RP3B1D

10K

R7W51K

.

R7W51K

.

C7H90.1uF10%.

C7H90.1uF10%.

R4A210K5%

R4A210K5%

R5W191K

.

R5W191K

.

+ C6H2220uF20%.

+ C6H2220uF20%.

GND1

IN2

EN13

EN24

OC2#5

OUT26

OUT17

OC1#8

U3N2

TPS2052B

U3N2

TPS2052B

36

RP5W1C10KRP5W1C10K

www.laptop-schematics

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Page 30: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TP_SATA_RESEV

+V5S_SATA_P0

SATA_5V_EN0_1 SATA_5V_EN0_2

V_3.3_3_PC

V_5.0_7_PC

V_12_13_PC

+V5_SATA_EN0_3

+V3.3S_SATA_P0

+V12_SATA_EN0_3 +V12S_SATA_P0

SATA_PWR_EN#0_5V

SATA_PWR_EN#0_5V

SATA_12V_EN0_2SATA_12V_EN0_1

SATA_3.3_EN0

+V

3.3

_S

AT

A_E

N0_4

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,12,16,17,18,24,28,31,32,39,48,49,52,55,56,57

+VBATS16,19,27,31,55,57

+V12S25,26,31,32,43,55,57

SATA_TXN021SATA_TXP021

SATA_PWR_EN#023

SATA_TXP521SATA_TXN521

SATA_RXN021SATA_RXP021

SATA_RXN521SATA_RXP521

SATA_DET#023

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

SATA (1 of 3)

30 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

SATA (1 of 3)

30 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

SATA (1 of 3)

30 58Tuesday, August 28, 2007

Layout Note: Place this connectoron the edge of CRB

SATA Port 0,

Direct Connect

+V12S is only for desktop type SATA devices

SATA Port-0,Direct Connect

SATA Port-5, eSATA

Presence Shunt (Default)Removed No Shunt

SATA Device Status J7H1

Interlock Switch to SATA port 0

This jumper simulates the drive status. For proper functionof the hot plug, this jumper must be "No Shunt" when driveis removed and "Shunt" after the drive is plugged in.

C9Y11000pF10%

C9Y11000pF10%

3

4

5 6

Q8H4BSI4925BDYQ8H4BSI4925BDY

R8Y2 1R8Y2 1

C9J30.1uF20%

C9J30.1uF20%

C9H51000pF10%

C9H51000pF10%

R8W12

1M

.

R8W12

1M

.

C8W41000pF10%

C8W41000pF10%

C8J40.1uF

.10%

C8J40.1uF

.10%

3

1

2

Q8J1BSS138Q8J1BSS138

C8Y122uFC8Y122uF

R8H131MR8H131M

C8J222uFC8J222uF

R8H12 0.0021%

R8H12 0.0021%

12

+

C8J1100uF

+

C8J1100uF

TP9H1NO_STUFF

TP9H1NO_STUFF

R8Y1 0.0021%

R8Y1 0.0021%

TX2

TX#3

RX#5

RX6

GND11

GND44

GND77

J7J1

eSATA_Signal_Plug

J7J1

eSATA_Signal_Plug

3

1

2

Q7H2BSS138Q7H2BSS138

1

2

7 8

Q8H4ASI4925BDYQ8H4ASI4925BDY

1

32

SI2307DS

Q9H3SI2307DS

Q9H3

4

1 2 38765

Q9Y1

IRF7835

Q9Y1

IRF7835

R8W14 0.0021%

R8W14 0.0021% C9J2

0.1uF20%

C9J20.1uF20%

R9Y15.1R9Y15.1

R8H10

1M

.

R8H10

1M

.

R8J2 4.3R8J2 4.3

+ C9J115uF20%

+ C9J115uF20%

12

J7H1J7H1

C8J50.1uF

.10%

C8J50.1uF

.10%

TX2

TX#3

RX#5

RX6

V_3.3_18

V_3.3_29

V_3.3_3_PC10

V_5.0_815

V_5.0_916

V_5.0_7_PC14

P_RESERVE_1118

V_12_1421

V_12_1522

V_12_13_PC20

GND_2M_P_1017

GND_1M_P_1219

GND_2M_S_11

GND_2M_S_44

GND_2M_S_77

GND_2M_P_512

GND_2M_P_613

GND_1M_P_411

J8J1

Serial ATA Recepticle

J8J1

Serial ATA Recepticle

R8H11 1MR8H11 1M

3

1

2

Q9H22N7002Q9H22N7002

R9H201MR9H201M

R8J110K1%

R8J110K1%

R7H943KR7H943K

R8W11

1M

.

R8W11

1M

.

C8J30.1uF

.10%

C8J30.1uF

.10%

www.laptop-schematics

.com

Page 31: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V12S_SATA_P1

+V5S_SATA_P1+V5_SATA_EN1_3

+V3.3S_SATA_P1

SATA_PWR_EN#1_5V

SATA_PWR_EN#1_5V

SATA_12V_EN1_1

SATA_PWR_EN#1_J

SATA_12V_EN1_2

SATA_5V_EN1_2

+V3.3_SATA_EN1_3

+V12_SATA_EN1_3

SATA_3.3V_EN1_1

SATA_5V_EN1_1

+V12S25,26,30,32,43,55,57

+V5S5,11,12,16,17,18,24,28,30,32,39,48,49,52,55,56,57

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+VBATS16,19,27,30,55,57

+V3.3S

SATA_TXN121SATA_TXP121

SATA_PWR_EN#123

SATA_TXN421SATA_TXP421

SATA_RXP121SATA_RXN121

SATA_DET#123

SATA_RXN421SATA_RXP421

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

SATA (2 and 3 of 3)

31 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

SATA (2 and 3 of 3)

31 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

SATA (2 and 3 of 3)

31 58Tuesday, August 28, 2007

SATA Port-1 and Port-2, Cable Connect

This jumper simulates the drive status. For proper functionof the hot plug, this jumper must be "No Shunt" when driveis removed and "Shunt" after the drive is plugged in.

Interlock Switch to SATA port 1

SATA Power Connector

Notes:-- Both SATA Port-1 and SATA Port-2 share the same power connector, J5J1-- Use Y-Cable available with Kit to feed the power from J5J1 to SATA device on port-1 and SATA device on Port-2.-- Connect Power cable first before connecting SATA signal cable.

SATA Port-4

SATA Port-2 SATA Port-1 Jumper (J4J2)Device notconnectedthru cable

Hotplug/removalsupported

Shunt (Default)

Deviceconnectedthru cable

Hotplug/removal not supported

No Shunt

SATA Port-1

SATA Signal Connectors

SATA Device Status J9H2Presence Shunt (Default)Removed No Shunt

R4Y3 0.0021%

R4Y3 0.0021%

R6J3 0.0021%

R6J3 0.0021%

C5J30.1uF20%

C5J30.1uF20%

R6J11MR6J11M

+ C5J715uF20%

+ C5J715uF20%

3

1

2

Q4J22N7002Q4J22N7002

12

+

C5J8100uF

+

C5J8100uF

C5J60.1uF

.10%

C5J60.1uF

.10%

4

1 2 38765

Q4J4

SI4835BDY

Q4J4

SI4835BDY

C4Y41000pF10%

C4Y41000pF10%

C6J21000pF10%

C6J21000pF10%

TX2

TX#3

RX#5

RX6

GND11

GND44

GND77

J6J3

SATA_Signal_Plug

J6J3

SATA_Signal_Plug

C4Y31000pF10%

C4Y31000pF10%

12

J4J2J4J2

R9H1543KR9H1543K

R4J210K1%

R4J210K1%

C5J40.1uF

.10%

C5J40.1uF

.10%

3

1

2

Q4J5BSS138Q4J5BSS138

R4J31MR4J31M

12

J9H2J9H2

R4Y4 0.0021%

R4Y4 0.0021%

R4J41MR4J41M

TX2

TX#3

RX#5

RX6

GND11

GND44

GND77

J6J2

SATA_Signal_Plug

J6J2

SATA_Signal_Plug

V_3.3_11

V_3.3_22

V_5_13

V_5_24

V_12_15

GND_16

GND_27

GND_38

GND_49

GND_510

J5J1

SATA_POWER_CONNECTOR

J5J1

SATA_POWER_CONNECTOR

3

1

2

Q4J3BSS138Q4J3BSS138

4

5 6 7 831 2

Q6Y1IRF7822

.

Q6Y1IRF7822

.

R4J61M

.

5%R4J61M

.

5%

R4J51M

.5%

R4J51M

.5%

C5J20.1uF20%

C5J20.1uF20%

C6J322uFC6J322uF

C5J122uFC5J122uF

R6J21MR6J21M

4

1 2 38765

Q4Y1

SI4835BDY

Q4Y1

SI4835BDY

C5J50.1uF

.10%

C5J50.1uF

.10%

www.laptop-schematics

.com

Page 32: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCI_GNT3

PM_SLP_S4#_R

PCI_RST#_R

LV

L_P

CIR

ST

#

PCI_AD22 22PCI_AD20 22

PCI_AD18 22PCI_AD16 22

PCI_AD6 22

PCI_CBE#0 22

PCI_AD9 22

PCI_AD2 22

PCI_AD11 22PCI_AD13 22

SMB_DATA_A1 23,25,26,44

PCI_AD15 22PCI_PAR 22

SMB_CLK_A1 23,25,26,44

PCI_STOP# 22

PCI_TRDY# 22

PCI_AD4 22

PCI_AD0 22

PCI_AD30 22

PCI_AD26 22PCI_AD28 22

PCI_AD24 22

PCI_FRAME# 22

INT_PIRQC# 22INT_PIRQG# 22

PM_CLKRUN# 23,38,40,43

INT_PIRQH# 22

PCI_AD2322

PCI_IRDY#22

INT_PIRQF#22

PCI_CBE#322

PCI_PERR#22PCI_LOCK#22

PCI_AD2122

PCI_AD122

PCI_AD2922

PCI_AD1722

PCI_AD1422

PCI_AD1922

PCI_AD322

PCI_AD2722

PCI_DEVSEL#22

PCI_SERR#22

PCI_AD3122

PCI_AD722

PCI_AD1022

PCI_AD2522

PCI_CBE#122

PCI_CBE#222

PCI_AD522

INT_PIRQE#22

PCI_AD1222

PCI_AD822

+V3.3S_PCI

+V5S_PCI

-V12S57

+V3.3A

+V5S_PCI

+V3.3S_PCI

+V5S5,11,12,16,17,18,24,28,30,31,39,48,49,52,55,56,57

+V5_PCI +V12S_PCI

+V5S_PCI

+V3.3S

+V3.3S_PCI

+V5S

+V5_PCI+V5 27,42,43,48,52,55,56,57

+V12S_PCI

+V12S25,26,30,31,43,55,57

PM_S4_STATE# 23,40,43,44,55,57

PCI_GNT#0 22

CLK_PCI_PCIGOLDF36

PCI_GNT#122

PCI_PME# 22,43

PCI_REQ#122

PCI_REQ#322

PCI_REQ#022

+V5

+V3.3 19,27,39,41,42,43,55,57

PCI_RST# 22,41

PCI_GATED_RST# 41

PCI_GNT#3 22

+V3.3S+V3.3S_PCI

+V3.3S

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

PCI Edge Connector (Goldfinger)

32 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

PCI Edge Connector (Goldfinger)

32 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

PCI Edge Connector (Goldfinger)

32 58Tuesday, August 28, 2007

(GOLDFINGER)

PCI - EDGE CONNECTOR

Default is to use pin A11 as a +V5S power pin (R9N2stuffed)

Stuff R9N3 and unstuff R9N2 if using ATX powersupply directly on extension board.

DO NOT STUFF BOTH R9N3 AND R9N2 AT THE SAME TIME

Place close to PCI EdgeConnector

Place close to PCI EdgeConnector

NO_STUFF

Place close to PCI EdgeConnector

-12VB1

GND(TCK)B2

GND1B3

REQ#0(TDO)B4

+5V_1B5

+5V_2B6

INTB#B7

INTD#B8

REQ#1(PRSNT1#)B9

RSV1B10

GNT#1(PRSNT2#)B11

+3.3V(RSV2)B14

GND4B15

CLKB16

GND5B17

REQ#5(REQ#)B18

+5V(+V_I/O1)B19

AD31B20

AD29B21

GND6B22

AD27B23

AD25B24

+3.3V_2B25

C/BE3#B26

AD23B27

GND7B28

AD21B29

AD19B30

+3.3V_3B31

AD17B32

C/BE2#B33

GND8B34

IRDY#B35

+3.3V_4B36

DEVSEL#B37

GND9B38

LOCK#B39

PERR#B40

+3.3V_5B41

SERR#B42

+3.3V_6B43

C/BE1#B44

AD14B45

GND10B46

AD12B47

AD10B48

GND11B49

AD08B52

AD07B53

+3.3V_7B54

AD05B55

AD03B56

GND12B57

AD01B58

+5V(+V_I/O2)B59

+5V(ACK64#)B60

+5V_3B61

+5V_4B62

C/BE0#A52

+3.3V_16A53

AD06A54

AD04A55

GND22A56

AD02A57

AD00A58

+5V(+V_I/O5)A59

+5V(REQ64#)A60

+5V (7)A61

+5V (8)A62

3.3VAUXA14

RST#A15

+5V(+V_I/O4)A16

GNT#5(GNT#)A17

GND15A18

PME#A19

AD30A20

+3.3V_11A21

AD28A22

AD26A23

GND16A24

AD24A25

+3.3V(IDSEL)A26

+3.3V_12A27

AD22A28

AD20A29

GND17A30

AD18A31

AD16A32

+3.3V_13A33

FRAME#A34

GND18A35

TRDY#A36

GND19A37

STOP#A38

+3.3V_14A39

SMBCLKA40

SMBDATA41

GND20A42

PARA43

AD15A44

+3.3V_15A45

AD13A46

AD11A47

GND21A48

AD09A49

GND(TRST#)A1

+12VA2

INT#(TMS)A3

GNT#0(TDI)A4

+5V_5A5

INTA#A6

INTC#A7

+5V_6A8

RSV3A9

+5V(+V_I/O3)A10

+5V(RSV4)A11

GND2B12

GND3B13

GND13A12

GND14A13

5V KEY

PCI_EXTENSION_GOLDFINGERS_5V

S9B1

NO_STUFF

5V KEY

PCI_EXTENSION_GOLDFINGERS_5V

S9B1

NO_STUFF

R8B1 0.0021%

R8B1 0.0021%

R9B20.0021%

R9B20.0021%

C9C40.1uF20%

C9C40.1uF20%

C9C30.1uF20%

C9C30.1uF20%

C9D20.1uF20%

C9D20.1uF20%

C9B10.1uF20%

C9B10.1uF20%

R9P10

.

R9P10

.

C8B210uFC8B210uF

C9C20.1uF20%

C9C20.1uF20%

TP9D2TP9D2

R9D50.0021%

NO

_S

TU

FF

R9D50.0021%

NO

_S

TU

FF

C9D522uFC9D522uF

TP8D1TP8D1

C9E222uFC9E222uF

R8P3

10K

.

R8P3

10K

.

R8B3 0.002

NO_STUFF1%

R8B3 0.002

NO_STUFF1%

C9B20.1uF20%

C9B20.1uF20%

TP9D1TP9D1

R9P20 NO_STUFFR9P20 NO_STUFF

TP8D2TP8D2

C9C10.1uF20%

C9C10.1uF20%

R9B10

.

R9B10

.

R9B30NO_STUFFR9B30NO_STUFF

1

3

2

Q8P12N3904Q8P12N3904

R9N10.0021%

NO

_S

TU

FF

R9N10.0021%

NO

_S

TU

FF

C9E30.1uF20%

C9E30.1uF20%

R8P2

1K

R8P2

1K

R9D20.0021%

R9D20.0021%

www.laptop-schematics

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Page 33: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

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5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CTRL_18

CTRL_18

CTRL_10

GLAN_CLK_R

+V1.0_LAN_M

+V1.8_LAN

LAN_XTAL2LAN_XTAL1

LAN_DIS

+V1.0_LAN_M_IN

LAN_TEST_EN

LAN_ATEST_NLAN_ATEST_P

LA

N_

JT

AG

_T

DO

LA

N_

JT

AG

_T

MS

LA

N_

JT

AG

_T

DI

RES_COMP

DIS_REG1P0

LA

N_

JT

AG

_T

RS

T

CTRL_10CTRL_10_R

+V1.0_LAN_M_IN

+V1.8_LAN_M

LA

N_

JT

AG

_T

CK

GLAN_RXN_CGLAN_RXP_C

+V3.3M_LAN

+V1.8_LAN_M34

+V1.0_LAN_M

+V1.8_LAN

+V3.3M_WOL22,24,34,44,48,55,57 +V3.3M_LAN +V1.8_LAN_M34+V1.8_LAN

+V3.3M_LAN

LAN_MDI0P34LAN_MDI0N34

LAN_MDI1P34LAN_MDI1N34

LAN_MDI2P34LAN_MDI2N34

LAN_MDI3P34LAN_MDI3N34

+V1.8_LAN_M34

+V1.0_LAN_M

+V3.3M_LAN+V3.3M_LAN

LAN_RSTSYNC21

LAN_TXD121LAN_TXD221

LAN_TXD021

PM_LAN_ENABLE 23,40,43

LAN_RXD121

GLAN_CLK21

LAN_RXD021

LAN_RXD221

LAN_LED_LNK#_ACT 34LAN_LED_1000# 34

LAN_LED_100# 34

+V3.3M_LAN

+V3.3M_LAN

GLAN_TXN22GLAN_TXP22

GLAN_RXN22GLAN_RXP22

+V3.3M_LAN

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LAN Boazman

A

33 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LAN Boazman

A

33 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LAN Boazman

A

33 58Tuesday, August 28, 2007

Place C8M14 close to PNP Collector (pin4)

Place C9M1 & C9M2 close to pin3

Place C8M6 close to PNP Collector (pin4)

Place C8A1, C8M5, C8M13 & C8M4close to LAN Controller(EU8A1)

Place GLAN_CLK series resistor close to LANController

Place C8M15 & C8M16 closeto LAN Controller

Place C8A5, C8M2, C8M12, C8M3, C8M9,C8M8 & C8M7 close to LAN Controller(EU8A1)

Place C9M3 & C9M4 close to pin3

Place crystal less than0.75 (~1.9 cm) inches fromLAN Controller

Layout Note:Keep this resistoron top side androute differentially

1V Source Stuff No_Stuff

IVRi

IVRd

R8M2

R8M2

R8M3, R8M1, Q9A1

R8M3, R8M1, Q9A1 (Default)

C9M30.1uF10%

C9M30.1uF10%

C8M90.1uF10%

C8M90.1uF10%

C8A24.7uF10%

C8A24.7uF10%

C8B127pF

5%

.

C8B127pF

5%

.

R9A8 5.1K

.5%

R9A8 5.1K

.5%

R8A12 4.99K

.

1%R8A12 4.99K

.

1%

R8A11KNO_STUFF

R8A11KNO_STUFF

C9M20.1uF10%

C9M20.1uF10%

1 2R7A2

0.002

R7A2

0.0021 2

R8A11

0.002

R8A11

0.002

R8M30

.5%

R8M30

.5%

R8A20

NO_STUFF

R8A20

NO_STUFF

R8A5200

NO_STUFF5%

R8A5200

NO_STUFF5%

41

Y8A1

25MHZ

Y8A1

25MHZ

C8M30.1uF10%

C8M30.1uF10%

TP9A1

NO

_S

TU

FF

TP9A1

NO

_S

TU

FF

C8M150.1uF10%.

C8M150.1uF10%.

C8A510uF80%

C8A510uF80%

R8M21KNO_STUFF

R8M21KNO_STUFF

C8M110.1uF10%

C8M110.1uF10%

C8A110uF80%

C8A110uF80%

1

3

2 4

Q9A2BCP69Q9A2BCP69

R8M100

NO_STUFF

R8M100

NO_STUFF

C8M130.1uF10%

C8M130.1uF10%

XTAL110

XTAL29

JKCLK45

JRSTSYNC50

JTXD244

JTXD143

JTXD042

JRXD047

JRXD148

JRXD249

GLAN_RXP55

GLAN_RXN56

GLAN_TXP52

GLAN_TXN53

IEEE_TEST_P12

IEEE_TEST_N13

LAN_DIS#37

LED04

LED12

LED21

MDI_PLUS[0]27

MDI_MINUS[0]26

MDI_PLUS[1]23

MDI_MINUS[1]22

MDI_PLUS[2]21

MDI_MINUS[2]20

MDI_PLUS[3]17

MDI_MINUS[3]16

JTAG_TCK40

JTAG_TDI7

JTAG_TDO6

JTAG_TMS39

TEST_EN36

NC51

VCC3P3[1]3

VCC3P3[3]28

VCC1P0[4]38

VCC1P0[1]5

VCC1P0[2]8

VCC1P0[3]33

VCC1P8[2]14

VCC1P8[3]18

VCC1P8[4]19

VSS57

CTRL1829

CTRL1031

RSET15

VCC1P8[5]24

VCC1P8[6]25

VCC1P8[7]30

VCC1P8[8]32

DIS_REG1P034

JTAG_TRST35

VCC3P3[2]46

VCC1P8[9]54

VCC1P8[1]11

VCC1P8[10]41

LCI

GLCI

MDI

JTAG

EU8A1

IC,BOAZ,56QFN,11-28-06,LAN,R0p7

LCI

GLCI

MDI

JTAG

EU8A1

IC,BOAZ,56QFN,11-28-06,LAN,R0p7

C8M80.1uF10%

C8M80.1uF10%

R9A2200

NO_STUFF5%

R9A2200

NO_STUFF5%

TP9A4

NO

_S

TU

FF

TP9A4

NO

_S

TU

FF

C8A827pF

5%

.

C8A827pF

5%

.

C9M410uF

.20%

C9M410uF

.20%

R8A610K

.5%

R8A610K

.5%

1

3

2 4

Q9A1

BCP69

Q9A1

BCP69

C8M16 0.1uF10%.

C8M16 0.1uF10%.

TP9A6

NO

_S

TU

FF

TP9A6

NO

_S

TU

FF

C8M40.1uF10%

C8M40.1uF10%

R9A1200

NO_STUFF5%

R9A1200

NO_STUFF5%

R8A410K

.5%

R8A410K

.5%

1 2R8A3

0.002

R8A3

0.002

C8M70.1uF10%

C8M70.1uF10%

C8M20.1uF10%

C8M20.1uF10%

C8M50.1uF10%

C8M50.1uF10%

TP9A3

NO

_S

TU

FF

TP9A3

NO

_S

TU

FF

R8M11KR8M11K

C8M120.1uF10%

C8M120.1uF10%

C8M610uF20%

C8M610uF20%

R8M6 33R8M6 33

TP9A5

NO

_S

TU

FF

TP9A5

NO

_S

TU

FF

C9M110uF

.20%

C9M110uF

.20%

C8M1410uF20%

C8M1410uF20%

R9A7 5.1K

.5%

R9A7 5.1K

.5%

www.laptop-schematics

.com

Page 34: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SPI0_SI_R

SPI0_HOLD#

SPI0_WP#

SPI_SO_SW

SPI_SI_SW

SPI0_SO_R

LAN_MDI1N_QLAN_MDI2P_Q

LAN_MDI3P_QLAN_MDI2N_Q

LAN_MDI3N_Q

LAN_MDI0N_Q

LAN_DOCK_EN#_R

LAN_LED_LNK#_ACT_QLAN_LED_1000#_QLAN_LED_100#_Q

LAN_LED_LNK#_ACT_Q

LAN_LED_100#_Q

SPI1_HOLD#

SPI1_SI_R

SPI1_WP# SPI1_CLK_R

SPI1_CLK_R

SPI0_CLK_RSPI_CS#0_CON

LAN_RJ45_VCT

SPI_CS#1_CON

SPI_SO_R

SPI1_SO_R

SPI_CS#0_CON

SPI0_SI_R

SPI0_WP#

SPI0_HOLD#

SPI0_CLK_R

SPI0_SO_R

LAN_DOCK_EN#_R

SPI_CLK_SW

LAN_MDI0P_QLAN_MDI0N_QLAN_MDI1P_QLAN_MDI1N_Q

LAN_MDI2P_QLAN_MDI2N_QLAN_MDI3P_QLAN_MDI3N_Q

SPI_CS#1_CON

SPI1_SI_R

SPI1_WP#

SPI1_HOLD#

SPI1_CLK_R

SPI1_SO_R

SPI1_SI_R

SPI0_SI_R

SPI0_SO_R

SPI0_CLK_R

SPI1_SO_R

OE#1

SPI_CS#SPI_SI_SWSPI_CLK_SW

SPI_SO_SW

OE#1

SPI_SI_SW

OE#1

OE#1OE#1

SPI_CLK_SW

SPI_CS#

SPI_SO_SW

LAN_LED_1000#_Q

OE#1OE#1

SPI_CS#0_CON

SPI_CS#1_CON

SPI_CS#0_CON

SPI_CS#1_CON

SPI_CS0#_PULLUP

SPI_CS1#_PULLUP

LAN_MDI0P_Q

LAN_MDI1P_Q

ICH_GPIO60_SPI ICH_GPIO24_SPI

LAN_MDI0P_Q_DOCK 44LAN_MDI0N_Q_DOCK 44LAN_MDI1P_Q_DOCK 44LAN_MDI1N_Q_DOCK 44LAN_MDI2P_Q_DOCK 44LAN_MDI2N_Q_DOCK 44LAN_MDI3P_Q_DOCK 44LAN_MDI3N_Q_DOCK 44

LAN_MDI0P33LAN_MDI0N33LAN_MDI1P33LAN_MDI1N33LAN_MDI2P33LAN_MDI2N33LAN_MDI3P33LAN_MDI3N33

+V3.3M_WOL22,24,33,44,48,55,57

+V3.3M_WOL22,24,33,44,48,55,57

+V3.3M_WOL22,24,33,44,48,55,57

+V5A24,29,38,44,46,47,50,51,56,57

+V3.3M_SPI_CON

+V1.8_LAN_M33

+V1.8_LAN_M33

+V3.3M_SPI_CON

+V1.8_VCT_LAN_DOCK44

+V3.3M_SPI_CON

+V3.3M_SPI_CON

+V3.3M_SPI_CON +V3.3M_SPI_CON

+V3.3M_SPI_CON

+V3.3M_SPI_CON

+V5A24,29,38,44,46,47,50,51,56,57

+V3.3M_SPI+V3.3M_SPI_CON

SPI_SI 22

SPI_CLK 22

LAN_LED_LNK#_ACT33LAN_LED_1000#33LAN_LED_100#33

DOCK_LAN_EN#41

LAN_LED_LINK#_DOCK 44LAN_LED_1000#_DOCK 44LAN_LED_100#_DOCK 44

SPI_SO22

+V5A24,29,38,44,46,47,50,51,56,57

SPI_CS#022

SPI_CS#1 22

+V5A24,29,38,44,46,47,50,51,56,57

+V3.3M_SPI

+V3.3M_WOL22,24,33,44,48,55,57

ICH_GPIO24 23ICH_GPIO6023

+V3.3M_WOL22,24,33,44,48,55,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LAN Docking and SPI

A

34 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LAN Docking and SPI

A

34 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LAN Docking and SPI

A

34 58Tuesday, August 28, 2007

Layout Note:This is thermal PAD ofIC (at bottom) and tobe shorted to GND

ACTIVITY LEDGreen = LINK UPBLINKING = TX/RX ACTIVITY

SPEED LEDOff = Link 10 MbpsGreen = Link 100 MbpsOrange = Link 1000 Mbps

Place C9C5 & C9C6 close to docking connector

Place C5A1 & C5N1 close to RJ45

LAYOUT NOTE:

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

U8C1/U8C4

U8B2/U8C3

At any time either U8B2/U8C3 or U8C1/U8C3 can bestuffed.

1 2 3 4

5678

HOLD#

VCC

NC

NC

NC

NC NC

NC

NC

NC

CS#

DO WP#

VSS

DI

CLK

SPI InterfaceVCCCSMISO

SPI ISP Conn pinout

GNDCLKMOSI

Mode J9D1 J8C1 J9C1

NormalOperation

Programing SPI0

Programing SPI1

1-X 1-XAllOpen

1-2 1-21-23-X

1-X2-3

1-2 1-2

DO8

WP#9

HOLD#1

NC13

NC24

NC35

NC46

NC511

NC612

NC713

NC814

DI15

CS#7

GND10

CLK16

VCC2

U8B2

32Mb SPI FLASH

NO_STUFF

U8B2

32Mb SPI FLASH

NO_STUFF

R8P43.3K

R8P43.3K

C5A10.01uF10%.402

C5A10.01uF10%.402

R8P53.3K

R8P53.3K

C5N10.01uF10%.402

C5N10.01uF10%.402

C9P10.1uF

.10%

C9P10.1uF

.10%

C8R20.1uF

.10%

C8R20.1uF

.10%

R7F11

0NO_STUFF5%

R7F11

0NO_STUFF5%

0+10

0-11

1+12

1-13

2+14

2-15

3+16

3-17

LED_1000#22

VCC09

GND018

LED_LINK#19

LED_ACT20

LED_100#21

J5A1A

RJ45 1000 WITH DUAL USB

J5A1A

RJ45 1000 WITH DUAL USB

DO8

WP#9

HOLD#1

NC13

NC24

NC35

NC46

NC511

NC612

NC713

NC814

DI15

CS#7

GND10

CLK16

VCC2

U8C3

32Mb SPI FLASH

NO_STUFF

U8C3

32Mb SPI FLASH

NO_STUFF

1 23 45 67 8

J8D2

8Pin HDR

J8D2

8Pin HDR

R8N3 47R8N3 47

1OE#1

1A2

1B3

2OE#4

2A5

2B6

GND7

VCC14

4OE#13

4A12

4B11

3OE#10

3A9

3B8

U8D1

74

CB

T3

12

5

U8D1

74

CB

T3

12

5

R8N2 47R8N2 47

C9C50.01uF10%.402

C9C50.01uF10%.402

32

1

CON3_HDR

J8C1

CON3_HDR

J8C1R8R2100

.

R8R2100

.

C8R10.1uF

.10%

C8R10.1uF

.10%

R8N8 15 1%R8N8 15 1%

R7A310K

NO

_S

TU

FF

5%

R7A310K

NO

_S

TU

FF

5%

CE#1

SO2

WP#3

VSS4

SI5

SCK6

HOLD#7

VDD8

U8C1

SST SPI FLASH

.

U8C1

SST SPI FLASH

.

R9C40

.

R9C40

.

R7T21

0NO_STUFF5%

R7T21

0NO_STUFF5%

R7M81K5%

NO

_S

TU

FF

R7M81K5%

NO

_S

TU

FF

R5B10

.

R5B10

.

R7A40

.

R7A40

.

CE#1

SO2

WP#3

VSS4

SI5

SCK6

HOLD#7

VDD8

U8C4

SST SPI FLASH

U8C4

SST SPI FLASH

1 2R8R1

0.002

R8R1

0.002

R8N6 47R8N6 47

A02

A13

A27

A38

NC

5

A411

A512

A614

A715

SEL17

7B229

6B230

7B131

6B132

5B234

4B235

5B136

4B137

3B240

2B241

3B142

2B143

1B245

0B246

1B147

0B148

GN

D0

1

GN

D1

6

GN

D2

9

GN

D3

13

GN

D4

16

GN

D5

21

GN

D6

24

GN

D7

28

GN

D8

33

GN

D9

39

GN

D1

04

4

GN

D1

14

9

GN

D1

25

3

GN

D1

35

5

VD

D4

38

VD

D3

27

VD

D2

18

VD

D1

10

VD

D0

4

LED019

LED120

0LED122

1LED226

VD

D5

50

VD

D6

56

2LED251

1LED123

0LED225

2LED152

LED254

THRM57

EU7A1

PI3L500 LAN Switch

EU7A1

PI3L500 LAN Switch

R8P13.3K

R8P13.3K

R8N73.3K

R8N73.3K

C8N30.1uF

.10%

C8N30.1uF

.10%

1 2

J9C1.J9C1.

R8P73.3K

R8P73.3K

C8N20.1uF

.10%

C8N20.1uF

.10%

R8P60

.5%

R8P60

.5%

C9C60.01uF10%.402

C9C60.01uF10%.402

R8N5 47R8N5 47

C7M10.1uF

.10%

C7M10.1uF

.10%

R8N43.3K

R8N43.3K

C7M40.1uF

.10%

C7M40.1uF

.10%

I/O11

I/O22

I/O33

I/O810

I/O79

I/O67

I/O56

I/O44

VN

5V

P8

U5M1

ESD DIODE ARRAY

NO_STUFF

U5M1

ESD DIODE ARRAY

NO_STUFF

1OE#1

1A2

1B3

GND4

VCC8

2OE#7

2B6

2A5

U8R1

SN74CBTD3306

U8R1

SN74CBTD3306

R8P8 15 1%R8P8 15 1%

C8P10.1uF

.10%

C8P10.1uF

.10%

1 2

J9D1

.

J9D1

.

www.laptop-schematics

.com

Page 35: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PCIF5_ITP_EN

CLK_SRC8_ITPCLK_SRC#8_ITP#

CLK_CPU0CLK_CPU#0

CLK_DOT96CLK_DOT96#

CLK_SRC6

CLK_SS_CLKCLK_SS_CLK#

XTAL_IN_D XTAL_IN

XTAL_OUT

BS

EL0_P

ULLU

P

VDD_CK505

XTAL_INXTAL_OUT

FSCCLK_BSEL2

PCI4_SRC5_EN

CLK_CPU#1CLK_CPU1

CLK_SRC#10

CLK_SRC#9CLK_SRC9

CLK_SRC2CLK_SRC2#

CLK_SRC4CLK_SRC#4

CLK_SRC3CLK_SRC#3

CLK_SRC#6

CLK_SRC10

CLK_BSEL0

CLK_BSEL1

FSACLK_SRC7CLK_SRC#7

PCI0_OE#_R

CLK_MCH_R_OE#PCI1_R

+V1.05M9,10,15,47,55

MCH_BSEL0 7

MCH_BSEL2 7

MCH_BSEL1 7

+V1.05S_CPU3,4,20,39,43,52,54

+V1.05S_CPU3,4,20,39,43,52,54

+VDDIO_CLK

+V3.3M 13,14,15,23,55,57

+V3.3S

+VDDIO_CLK

SMB_DATA_M323,36

PM_STPPCI# 23,43PM_STPCPU# 23,43

CPU_BSEL23

XDP_BPM#2 3

CPU_BSEL03

CPU_BSEL13

XDP_BPM#3 3

XDP_BPM#1 3

SMB_CLK_M323,36

CLK_XDP 20CLK_XDP# 20

CLK_CPU_BCLK# 3CLK_CPU_BCLK 3

DREFCLK 7DREFCLK# 7

DREFSSCLK 7DREFSSCLK# 7

XDP_OBS020

XDP_OBS120

XDP_OBS220

CLK_PCIF36

CLK_USB4823

CLK_REF_SIO38

CLK_REF_ICH23

CLK_REF_LPC43

CLK_PCI36

CLK_MCH_BCLK 6CLK_MCH_BCLK# 6

CLK_PCIE_XDP_3GPLL 20CLK_PCIE_XDP_3GPLL# 20

CLK_PWRGD 23,36

CLK_BSEL1

CLK_PWRGD_R

CLK_BSEL0

CLK_BSEL2

CLK_PCIE_3GPLL# 7CLK_PCIE_3GPLL 7

CLK_PCIE_SATA# 21CLK_PCIE_SATA 21

CLK_SRC_DB800 36CLK_SRC_DB800# 36

CLK_SATA_OE# 23

CLK_PCIE_DMI_LAICLK_PCIE_DMI_LAI#

CLK_PCIE_PEG# 19CLK_PCIE_PEG 19

CLK_PCIE_ICH 22CLK_PCIE_ICH# 22CLK_MCH_OE#7

PCI1

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CK505

Custom

35 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CK505

Custom

35 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

CK505

Custom

35 58Tuesday, August 28, 2007

1

1

1

0

FSB

1

0

1

100

266

1

0

BSEL1BSEL2

0

0

0

FSA

0 133

3330

1

400

0

166

Reserved

0

FSC

1

1

0

Host Clock frequency MHz

200

1

0

1

BSEL0

1

CPU,MCH and XDP BCLK FREQUENCYSELECTION TABLE

Place each 0.1uF cap as close aspossible to each VDD_IO pin. Placethe 10uF cap on the VDD_IO plane.

1067

J1G5 -> OpenJ1G3 -> OpenJ1G1 -> 2-3

(Default

Setting)

J1G5 -> 2-3J1G3 -> OpenJ1G1 -> 2-3

FSB Speed (MT/s)

FSB Frequency Select:

800

667

CPUDriven

J1G5 -> OpenJ1G3 -> 2-3J1G1 -> 2-3

J1G5 -> 1-2J1G3 -> 1-2J1G1 -> 1-2

SPARE

CK505D

QFN-64

R5V12 0.0021%

R5V12 0.0021%

R6H7 0

.

R6H7 0

.

C6W60.1uF

.10%

C6W60.1uF

.10%

R5G8 2.2KR5G8 2.2K

R6G17 0

.

R6G17 0

.

32

1

CON3_HDR

J1G5

CON3_HDR

J1G5

R6H8 0

.

R6H8 0

.

R6G7 0

.

R6G7 0

.

R5G11 22R5G11 22

32

1

CON3_HDR

J1G3

CON3_HDR

J1G3

C6W50.1uF

.10%

C6W50.1uF

.10%

R5H210K

.

R5H210K

.

C5V610uF

.20%

C5V610uF

.20%

36RP1F1C0NO_STUFF

RP1F1C0NO_STUFF

R6G8 0

.

R6G8 0

.

R6H13 0

.

R6H13 0

.

C6V130.1uF

.10%

C6V130.1uF

.10%

R6H3 0

.

R6H3 0

.

R6G10 0

.

R6G10 0

.

R6H9 0

.

R6H9 0

.

R6G11 0

.

R6G11 0

.

R5G13 22R5G13 22

R6H5 0

.

R6H5 0

.

R6H14 475R6H14 475

R6G14 0

.

R6G14 0

.

R5W20

NO_STUFF

R5W20

NO_STUFF

18RP1F1A0NO_STUFF

RP1F1A0NO_STUFF

36RP1U1C0

RP1U1C0

R5H4 33R5H4 33

27RP1F1B0NO_STUFF

RP1F1B0NO_STUFF

C6V90.1uF

.10%

C6V90.1uF

.10%

45RP1U1D0

RP1U1D0

C6V60.1uF

.10%

C6V60.1uF

.10%

354

1

2

J5H1

5Pin_JACK

NO_STUFFJ5H1

5Pin_JACK

NO_STUFF

R5G1210K5%

R5G1210K5%

C5H10.1uF

.10%

C5H10.1uF

.10%

R1G3 1KR1G3 1K

R1G11KR1G11K

PCI312

PCI4/SEL_LCDCLK#13

PCIF5/ITP_EN14

REF/FSC/TEST_SEL5

FSB/TEST_MODE64

VDD_I/O19

VSS_PCI15

VSS_PLL326

VDD_SRC1_I/O43

USB/FS_A17

SRC0/DOT_9620

SRC0#/DOT_96#21

VDD_SRC46

LCDCLK#/27M_SS25

LCDCLK/27M24

SRC228

SRC2#29

VSS_I/O22

SRC3/CLKREQ_C#31

SRC3#/CLKREQ_D#32

SRC434

SRC4#35

VDD_PCI9

SRC11#/CLKREQ_G#39

SRC11/CLKREQ_H#40

SRC7#/CLKREQ_E#50

SRC7/CLKREQ_F#51

VSS_4818

VDD_4816

CPU0#60

CPU061

CPU1_MCH#57

CPU1_MCH58

VSS_CPU59

CPU_STOP#44

PCI_STOP#45

XTAL_IN3

SCL7

SDA6

VSS_REF1

XTAL_OUT2

VDD_PLL323

PCI0/CLKREQ_A#8

PCI1/CLKREQ_B#10

PCI211

VDD_PLL3_I/O27

VDD_CPU_I/O56

NC55

SRC8/CPU_ITP54

SRC8#/CPU_ITP#53

VSS_SRC136

VDD_SRC0_I/O33

VSS_SRC030

VDD_CPU62

CKPWRGD/PD#63

VSS_SRC249

SRC9#38

SRC937

SRC10#42

SRC1041

SRC6#47

SRC648

VDD_SRC2_I/O52

VDD_REF4

THERM65

EU6H1

SLG8SP533

EU6H1

SLG8SP533

R5H3 33R5H3 33

R6W1 0

.

R6W1 0

.

C6V70.1uF

.10%

C6V70.1uF

.10%

C6V80.1uF

.10%

C6V80.1uF

.10%

R5G9 33R5G9 33

R1G456R1G456

C6W30.1uF

.10%

C6W30.1uF

.10%

C6V1210uF

.20%

C6V1210uF

.20%

R6G9 0

.

R6G9 0

.

C5W14.7uF

.10%

C5W14.7uF

.10%

R5V8 0.0021%

R5V8 0.0021%

27RP1U1B0

RP1U1B0

R6H2 0

.

R6H2 0

.

R5G14475

R5G14475

R6H10 0

.

R6H10 0

.

R6G18 0

.

R6G18 0

.

R6H6 0

.

R6H6 0

.

R5W9 33R5W9 33

R6G16 0

.

R6G16 0

.

R5W60

NO_STUFF

R5W60

NO_STUFF

32

1

CON3_HDR

J1G1

CON3_HDR

J1G1

C5V510uF

.20%

C5V510uF

.20%

R6G13 0

.

R6G13 0

.

C5W333pF

.5%

C5W333pF

.5%

C6W210uF

.20%

C6W210uF

.20%

R6H12 0

.

R6H12 0

.

C6V100.1uF

.10%

C6V100.1uF

.10%

C6V114.7uF

.10%

C6V114.7uF

.10%

R6G19 0

.

R6G19 0

.

C6W40.1uF

.10%

C6W40.1uF

.10%

2 1

Y5H1

14.318MHZ

Y5H1

14.318MHZ

R6H11 0

.

R6H11 0

.

R6G12 0

.

R6G12 0

.

R1F21KR1F21K

45RP1F1D0NO_STUFF

RP1F1D0NO_STUFF

R5W849.91%

NO_STUFF

R5W849.91%

NO_STUFF

R1G5 1KR1G5 1K

18RP1U1A0

RP1U1A0

C6W10.1uF

.10%

C6W10.1uF

.10%

R5G15475 .1%

R5G15475 .1%

R6G15 0

.

R6G15 0

.

C5V70.1uF

.10%

C5V70.1uF

.10%

R1F1 1KR1F1 1K

R5V910K5%

R5V910K5%

C5W433pF

.5%

C5W433pF

.5%

R1G61KR1G61K

www.laptop-schematics

.com

Page 36: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_PCIE_SLOT2CLK_PCIE_SLOT1#CLK_PCIE_SLOT1

CLK_PCIE_SLOT3#CLK_PCIE_SLOT3CLK_PCIE_SLOT2#

DIF2

DIF1

DIF0

DIF#1+V3.3S_DB800_VDDA

DB800_IREF

DIF#0

DIF#2

DB800_BYPASS#_PLL

DB800_HIGH_BW#DB800_SRC_DIV#

DB800_SRC_STOP

DB800_OEINV

DIF7#DIF7

DIF#3

DIF4

DIF3

DIF#4

CLK_PCIE_SLOT5CLK_PCIE_SLOT4#

CLK_PCIE_SLOT5#

CLK_PCIE_SLOT4

CLK_PCIE_DOCKCLK_PCIE_DOCK#

DB800_PD

DB800_OE5#

DB800_OE6#

PCIF_QA7

PCI_QB1

PCI_QB6

PCI_QB4

PCI_QB5

PCI_QB7

PCI_QB3

PCI_QB2

TP_OE

AGND_DB800

AGND_DB800SMB_DATA_M323,35

+V3.3S +V3.3S_DB800

+V3.3S_DB800

+V3.3S_DB800

CLK_REQ#_DOCK 44

CLK_SLOT1_OE# 25

CLK_SLOT2_OE# 25

CLK_SLOT3_OE# 26SMB_CLK_M323,35

CLK_SRC_DB80035CLK_SRC_DB800#35

CLK_SLOT5_OE# 26

CLK_SLOT4_OE# 26CLK_PWRGD23,35

CLK_PCIE_SLOT1 25

CLK_PCIE_SLOT2# 25CLK_PCIE_SLOT2 25

CLK_PCIE_SLOT1# 25

CLK_PCIE_SLOT3 26CLK_PCIE_SLOT3# 26

CLK_PCIE_DOCK# 44CLK_PCIE_DOCK 44

CLK_PCIE_SLOT5# 26

CLK_PCIE_SLOT4 26

CLK_PCIE_SLOT5 26

CLK_PCIE_SLOT4# 26

CLK_PCIF_ICH 22

CLK_PCI_KBC 40

CLK_PCI_LPC 43

CLK_PCI_SIO 38

CLK_PCI_XDP

CLK_PCI_SIODOCK 38

CLK_PCI_PCIGOLDF 32

CLK_PCI_TPM 43

CLK_PCIF_2Y2

CLK_PCI35

CLK_PCIF35

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,38,39,40,41,43,48,49,52,55,56,57

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,38,39,40,41,43,48,49,52,55,56,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DB800 & Buffers

A

36 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DB800 & Buffers

A

36 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DB800 & Buffers

A

36 58Tuesday, August 28, 2007

Layout Note: Series termination resistors should be placed as close to the device as possible. Place the 0.01uF decoupling capacitors closest.

C7T120.01UF.

C7T120.01UF.

R7P1010K

NO_STUFF

5%

R7P1010K

NO_STUFF

5%

DIF08

DIF112

DIF216

DIF320

DIF430

DIF534

DIF638

DIF742

DIF#09

DIF#113

DIF#217

DIF#321

DIF#429

DIF#533

DIF#637

DIF#741

OE0#6

OE1#14

OE2#15

OE3#7

OE4#43

OE5#35

OE6#36

OE7#44

VDD12

VDD211

VDD319

VDD431

VDD539

GND13

GND210

GND318

GND425

GND532

OE_INV40

VDDA48

GNDA47

SRC_DIV#1

SRC_IN4

SRC_IN#5

BYPASS#/PLL22

SCLK23

SDATA24

PWRDWN26

SRC_STOP27

HIGH_BW#28

LOCK45

IREF46

U7C2

DB800

U7C2

DB800

R7T11 33

.

R7T11 33

.

R7D9 49.9R7D9 49.9

C7C222uFC7C222uF

R7P1110K

.

5%

R7P1110K

.

5%

2 4

5

3

U7C1

INVERTER

U7C1

INVERTER

R7C22 33R7C22 33

R7C111R7C111

R7C10 49.9R7C10 49.9

R7D7 49.9R7D7 49.9C7P70.1uF

.10%

C7P70.1uF

.10%

R7D4 49.9R7D4 49.9

R7C16 33R7C16 33

R7T6 33

.

R7T6 33

.

R7C6 49.9R7C6 49.9C7P50.1uF

.10%

C7P50.1uF

.10%

R7P70

.

R7P70

.

R7C13 10KR7C13 10K

R7C17 33R7C17 33

R7T10 33

.

R7T10 33

.

R7C8 49.9R7C8 49.9

R7C19 33R7C19 33

R7T7 33

.

R7T7 33

.

R7C7 49.9R7C7 49.9

R7C26 33R7C26 33

C7T160.01UF.

C7T160.01UF.

R7P2 33R7P2 33

R7C23 33R7C23 33C7P40.1uF

.10%

C7P40.1uF

.10%

R7C12475R7C12475

R7D210K

.

5%

R7D210K

.

5%

R7D6 49.9R7D6 49.9

R7C1510K

.

5%

R7C1510K

.

5%

R7C5 49.9R7C5 49.9

C7T130.01UF.

C7T130.01UF.

R7P1 33R7P1 33

R7P810K

.

5%

R7P810K

.

5%

C7P20.1uF

.10%

C7P20.1uF

.10%

R7C25 33R7C25 33

R7C4 49.9R7C4 49.9

R7P1410K

NO_STUFF

5%

R7P1410K

NO_STUFF

5%

R7C18 33R7C18 33

R7C21 33R7C21 33

INA1

QA02

QA13

QA24

VDDA15

VDDA26

QA37

QA48

GND19

GND210

QA511

QA612

QA713

OE14

VDD15

QB716

QB617

QB518

GND319

GND420

QB421

QB322

VDDB123

VDDB224

QB225

QB126

QB027

INB28

U7E4

MK74CB218B

U7E4

MK74CB218B

C7P30.1uF

.10%

C7P30.1uF

.10%

C7P10.1uF

.10%

C7P10.1uF

.10%

R7T15 33

.

R7T15 33

.

R7D5 49.9R7D5 49.9

R7C24 33R7C24 33

R7T19 33

.

R7T19 33

.

C7P60.1uF

.10%

C7P60.1uF

.10%

R7T9 15

.

R7T9 15

.

R7T18 33

.

R7T18 33

.

R7D8 49.9R7D8 49.9

R7C90.002

.

1%

R7C90.002

.

1%

R7C14 10KR7C14 10K

R7P1210K

.

5%

R7P1210K

.

5%

R7P910K

NO_STUFF

5%

R7P910K

NO_STUFF

5%

www.laptop-schematics

.com

Page 37: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BOARD_ID0BOARD_ID1

BOARD_ID3BOARD_ID2

REV_FAB_ID3

REV_FAB_ID0

REV_FAB_ID2REV_FAB_ID1

REV_FAB_ID0

BOARD_ID1

A1_RA0_R

BOARD_ID3

A2_R

BOARD_ID2

REV_FAB_ID3

PCA9557_RST#

REV_FAB_ID1REV_FAB_ID2

BOARD_ID0

SMB_BS_DATA40,43,51,52SMB_BS_CLK40,43,51,52

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

I/O Port Expander

A

37 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

I/O Port Expander

A

37 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

I/O Port Expander

A

37 58Tuesday, August 28, 2007

BOARD REVISION

FAB REVISION

1

0

14

0

1

1

0

00

0

15

0

0

1

2

1

1

0

0

0

1

0

1

13

1

0

1

1

1

0

1

0

0

0

0

1

0

0

1

1

0

1

0

0

1

FAB_REV

0

0

1

FAB ID Strapping Table

0 4

1

1

0

1

3

0

0

BOARD ID

0

1

BOARD REVISION Strapping Table

0

0 0

1

0

0

5

1

6

0

1

0

1

1

0

11

1

0

1

1

1

BOARD FAB

1

3

0

0

0 0

0

0

0

1

1

7

2

1

1

1

3

BOARD REVISION

1

0

1

8

0

1

1

1

1

0

0

12

1

1

1

1

1

1

0

10

0

1

1

1

1

1

0

11

1

1

0

0

0

1

0

1

1

9

0

STHI CPV-MCH DDR3

1

00

1

0

0

0

0

1

16

2

1

0

1

0

STHI CPV-ICH DDR2STHI PPV-PGA DDR2Sundial

TBDTBDTBDTBD

TBD

TBDTBD

TBD

8-bit I/O Port Expander

fixed

0 0 1 1 A2 A1 A0 R/W

PCA9557 Address

programmable

slave address

Pillar RockSilver CascadeFern HillSTHI CPV-MCH DDR2

R9G810K

.

5%

R9G810K

.

5%

R9G1410K

NO_STUFF

5%

R9G1410K

NO_STUFF

5%

R9V410K

NO_STUFF

R9V410K

NO_STUFF

R9G910K

NO_STUFF

5%

R9G910K

NO_STUFF

5%

R9G1210K

NO_STUFF

5%

R9G1210K

NO_STUFF

5%

R9G1510K

.

5%

R9G1510K

.

5%

R9G1810K

.

R9G1810K

.

R9V510K

NO_STUFF

R9V510K

NO_STUFF

R9V610K

.

R9V610K

.

R9G2010K

.

5%

R9G2010K

.

5%

R9G1910K

.

R9G1910K

.

R9G2110K

NO_STUFF

R9G2110K

NO_STUFF

R9V80

.

R9V80

.

R9V100

.

R9V100

.

R9G2210K

NO_STUFF

R9G2210K

NO_STUFF

R9V90

.

R9V90

.

R9V710K

.

R9V710K

.

R9G710K

NO_STUFF

5%

R9G710K

NO_STUFF

5%

R9G1310K

.

5%

R9G1310K

.

5%

VDD16

VSS8

SCLK1

SDATA2

I/O06

A03

A25

A14

I/O17

I/O29

I/O310

I/O411

I/O512

I/O613

I/O714

RESET#15

U9G1

PCA9557PW

U9G1

PCA9557PW

C9G20.1uF20%

C9G20.1uF20%

R9G41K

.5%

R9G41K

.5%

www.laptop-schematics

.com

Page 38: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SIO_RST#RST_PD

SER_DTRA#

AND_DRQ#0

SER_RTSA#

D_LDRQ1

LPCD_PWRGD

LPCD_RST#

LPCD_PD#

D_CLK_33

LPCD_SMC_EXTSMI#

LPCD_PCI_PME#

D_LAD_1

D_SER_IRQ

LPCD_OPNREQ#

D_CLK_14

D_LFRAME#

D_CLKRUN

D_LAD_0 D_LAD_2D_LAD_3

LPCD_PWREN#

D_LDRQ1D_LFRAME#

D_LAD_2

TP_GPIO32

TP_SIO_GPIO13

D_CLK_14

SIO_DRQ#1

LPCD_OPNREQ_OUT#

D_CLKRUN

D_LAD_1

LPCD_PWREN#

D_LAD_0

LPCD_LPCPD#

D_SER_IRQ

SIO_DRQ#0

LPCD_PWRGD

D_LAD_3

SIO_RST#

TP_GPIO33D_CLK_33

LPCD_LPCRST#

LPCD_RI#

SER_DTRA#

LPCD_OPNREQ_OUT#LPCD_OPNREQ#

SER_RTSA#

PM_SUS_STAT#

LPCD_LPCPD#LPCD_PD#

PLT_RST#

LPCD_LPCRST#LPCD_RST#

PM_RI_SIO

LPCD_PCI_PME#LPCD_RI# SMC_EXTSMI#

LPCD_SMC_EXTSMI#

LPCD_QSEN#

LPCD_PWRGD

LPC_AD0 21,40,43LPC_AD1 21,40,43LPC_AD2 21,40,43LPC_AD3 21,40,43

INT_SERIRQ 23,40,43

IR_MODE39

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57

+V3.3A

+V3.3A19,21,23,24,25,26,27,28,29,32,37,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3S

+V3.3S

+V3.3S

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57

+V3.3S_SIO

+V3.3S_SIO

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57+V3.3S_SIO

+V3.3S

+V3.3S

+V3.3A19,21,23,24,25,26,27,28,29,32,37,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V5A24,29,34,44,46,47,50,51,56,57

LPC_FRAME# 21,40,43

CLK_REF_SIO 35CLK_PCI_SIODOCK 36

PM_SUS_STAT# 23,40,43

PLT_RST#7,19,22,25,26,41,57

IR_RXD39

RS232_RI#39LPCS_PME#43

SER_SINA 39

CLK_PCI_SIO 36

LPC_DRQ#143

SER_RIA# 39

LPC_DRQ#043

SER_DCDA# 39

SER_DTRA# 39SER_RTSA# 39

TPM_DRQ#043

PM_RI# 23,43

PM_CLKRUN# 23,32,40,43

IR_TXD39

SMC_EXTSMI#23,40,43,44

RS232_EN39

L_BKLTSEL1#17

ICH_DRQ#1 21

SER_CTSA# 39SER_DSRA# 39

ICH_DRQ#0 21

SER_SOUTA 39

KSC_LPC_DOCK#40

IRDA_CIR_SLT39

L_BKLTSEL0#17

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

SIO

A

38 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

SIO

A

38 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

SIO

A

38 58Tuesday, August 28, 2007

LPC HOT DOCKING

Default:1 - 2

SMSC PORT-SWITCH

11= 0x164E

Base Address:00 = 0x002E01 = 0x004E10 = 0x162E11 = 0x164E

Default:

LPC DOCKING

R7T13100K5%

R7T13100K5%

R8T810K5%

R8T810K5%

R7T30

NO_STUFF

R7T30

NO_STUFF

C7T122UFC7T122UF

1

24

53

U7E2

74AHC1G08

U7E2

74AHC1G08

1

24

53

U7E1

74AHC1G08

U7E1

74AHC1G08

R8E610K5%

R8E610K5%

R7E410K

.

R7E410K

.

C9F1 0.1uFC9F1 0.1uF

C7T110.1uF20%

C7T110.1uF20%

R9F11100K5%

R9F11100K5%

R7T1710K5%

R7T1710K5%

R9F8100K5%

R9F8100K5%

C7T170.1uF20%

C7T170.1uF20%

C7T70.1uF20%

C7T70.1uF20%

R7E110K

NO_STUFF

R7E110K

NO_STUFF

R7E210K

NO_STUFF

R7E210K

NO_STUFF

R7T2 0.0021%

R7T2 0.0021%

1

24

53

U8E4

74AHC1G08

U8E4

74AHC1G08

32

1

CON3_HDR

J7E1

CON3_HDR

J7E1

C7T60.1uF20%

C7T60.1uF20%

C7T80.1uF20%

C7T80.1uF20%

C7T50.1uF20%

C7T50.1uF20%

C7T140.1uF20%

C7T140.1uF20%

C7T20.1uF20%

C7T20.1uF20%

R8E910K

.

5%

R8E910K

.

5%

1

24

53

U8E5

74AHC1G08

U8E5

74AHC1G08

R8T710K5%

R8T710K5%

R7T80

.

R7T80

.

VCC4

OUT3

GND1

IN2

U9F1

MAX6816

U9F1

MAX6816

C7T100.1uF20%

C7T100.1uF20%

R7E310K

.

R7E310K

.

R7T148.2KR7T148.2K

3

1

2

Q8E5BSS138Q8E5BSS138

C7T30.1uF20%

C7T30.1uF20%

1

24

53

U8E3

74AHC1G08

U8E3

74AHC1G08

VCC15

VCC217

VCC331

VCC442

VCC560

VSS18

VSS220

VSS329

VSS437

VSS545

VSS662

VTR48

GPIO1027

GPIO1128

GPIO12/IO_SMI#30

GPIO13/IRQIN132

GPIO14/IRQIN233

GPIO1534

GPIO1635

GPIO1736

GPIO3038

GPIO3139

GPIO3240

GPIO3341

GPIO3443

GPIO3544

GPIO3646

GPIO3761

IRTX249

IRRX250

IRMODE/IRRX351

LAD064

LAD12

LAD24

LAD37

LFRAME14

LDRQ024

LDRQ112

PCI_RESET22

LPCPD25

CLKRUN16

PCI_CLK21

SER_IRQ19

IO_PME47

LPC_CLK_3310

SIO_14M23

DLAD(0)63

DLAD(1)1

DLAD(2)3

DLAD(3)6

DLFRAME13

DLDRQ111

DCLKRUN15

DLPC_CLK_339

DSER_IRQ18

DSIO_14M26

TXD153

RTS1#/SYSOPT055

DTR1#/SYSOPT157

CTS156

RXD152

DSR154

DCD159

RI158

GENERAL PURPOSE I/O

UART2

IRPOWER & GROUND

LPC INTERFACE

DOCKING LPC INTERFACE

UART1

U7E3

SIO1007-JV

GENERAL PURPOSE I/O

UART2

IRPOWER & GROUND

LPC INTERFACE

DOCKING LPC INTERFACE

UART1

U7E3

SIO1007-JV

OE1#1

1A2

1B3

GND4

2A5

2B6

OE2#7

VCC8

U7E5

74CBT3306

U7E5

74CBT3306

13 4

2

579

86

1011131517192123 24

222018161412

J9E3

2X12-HDR_SHRD

J9E3

2X12-HDR_SHRD

C7T150.1uF20%

C7T150.1uF20%

R8E510K5%

R8E510K5%

C7T180.1uF20%

C7T180.1uF20%

R7E510K5%

R7E510K5%

www.laptop-schematics

.com

Page 39: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SERBUF_DTRA

VID_COMP

SERBUF_RTSA

SERBUF_SINA#

SERBUF_C2-

VID_COMP

SERBUF_V-

SERBUF_V+

SERBUF_C2+

SERBUF_CTSA

SERBUF_SOUTA#

SERBUF_DCDA

VID_COMP

SERBUF_DSRA

SERBUF_RIA

VID_COMP

LE

D_

VID

0

LE

D_

VID

1

LE

D_

VID

2

LE

D_

VID

3

LE

D_

VID

4

SER_ON

SER_RIA

IRDA_TXD

TX_OUT

SERBUF_SINA#RX_IN

TX_OUT

SERBUF_DTRASERBUF_RIA

SERBUF_DSRA

SERBUF_CTSA

RX_IN

SERBUF_DCDA

SERBUF_RTSASERPRT_RX_IN

SERPRT_TX_OUTSERPRT_CTSA

SERPRT_RIASERPRT_DTRA

SERPRT_DCDASERPRT_DSRA

SERPRT_RTSA

SERBUF_C1+

SERBUF_C1-

C2+4

C1-3

V_C_6

SER_TX_OUT

C2-5

V_C_2

C1+1

VID_0_D

VID_COMP

VID_COMP

VID_COMP

LE

D_

VID

5

LE

D_

VID

6

SIO_VID6

VID_1_D

VID_2_D

VID_3_D

VID_4_D

VID_5_D

VID_6_D

VID_COMP

SIO_VID4

SIO_VID0

SIO_VID3

CIR_TXD

SIO_VID5

SIO_VID2

SIO_VID5

U1C1D_SPARE

SIO_VID0

SIO_VID2SIO_VID4

SIO_VID1

SIO_VID3

SIO_VID6

SIO_VID1

SER_TX_OUT

SER_KBCPROG_RX_IN SER_KBCPROG_RX_IN

LED_A

VCC_HSDL

SER_EC_SCIF_TXD

SER_EC_SCIF_RXD

SERBUF_SOUTA#

IR_MODE38

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V1.05S_CPU3,4,20,35,43,52,54

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V3.3 19,27,32,41,42,43,55,57

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V3.319,27,32,41,42,43,55,57

+V5S 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V3.3A

+V3.3A

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

+V3.3S_IR

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,40,41,43,48,49,52,55,56,57

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,40,41,43,48,49,52,55,56,57

+V3.3A

VR_VID052

SER_SOUTA38

IR_TXD38

RS232_EN38

IRDA_CIR_SLT38

KBC_PROG_TX#40

VR_VID152

VR_VID252

VR_VID352

VR_VID452

VR_VID552

VR_VID652

SER_DSRA#38

SER_CTSA#38

EC_SCIF_TXD_TRANSC40

RS232_RI#38

SER_SINA38

SER_DCDA#38

SER_RIA#38

IR_RXD38

KBC_PROG_RX#40

SER_RTSA#38

SER_DTRA#38

EC_SCIF_RXD_TRANSC40

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

Legacy Support

A

39 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

Legacy Support

A

39 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

Legacy Support

A

39 58Tuesday, August 28, 2007

RS-232 TRANSCEIVER

SERIAL PORT CONNECTOR

SIO VID VOLTAGE TRANSLATION

IR

CAD NOTE:Place nearU1B1 &U1B3

Spare

IRDA_CIR_SLT =0, then Y0=A, IRDA_CIR_SLT=1,then Y1=A.

C4A2,C4A5 Should benear U4A1.

In Ckt H8 Programming J7A1 and J8B2Disable 1-2 (Default)Enable 2-3 (In Ckt Programming)

R1N22330R1N22330

R1P110K

.

R1P110K

.

C7B1 0.1uF

.10%C7B1 0.1uF

.10%

S1

GND2

A3

Y14

VCC5

Y06

U4M1

NON-INV DMUX

U4M1

NON-INV DMUX

+ C4A46.8uF10%

+ C4A46.8uF10%

R1N18 1KR1N18 1K

C6M40.1uF

.10%

C6M40.1uF

.10%

C7M70.1uF20%

C7M70.1uF20%

C4A20.1uF

.10%

C4A20.1uF

.10%

2 7FB2A5B 60OHM-100MHZFB2A5B 60OHM-100MHZ

R1

N2

31

0K

R1

N2

31

0K

7

61

3

12

+

-

U1B1B

LM339

+

-

U1B1B

LM339

C7M60.1uF20%

C7M60.1uF20%

R1P3 1KR1P3 1K

C7M50.1uF

.10%

C7M50.1uF

.10%

12

CR1B4GREENCR1B4GREEN

R1N32330R1N32330

R1

N4

41

0K

R1

N4

41

0K

C7B3 0.1uF

.10%C7B3 0.1uF

.10%

R1

N2

91

0K

R1

N2

91

0K

2 7FB2A3B 60OHM-100MHZFB2A3B 60OHM-100MHZ

12

CR1B5GREENCR1B5GREEN

R4M110KR4M110K

1 8FB2A5A 60OHM-100MHZFB2A5A 60OHM-100MHZ

7

61

3

12

+

-

U1B3B

LM339

+

-

U1B3B

LM339

11

1013

3

12

+

-

U1B1D

LM339

+

-

U1B1D

LM339

+ C4A56.8uF10%

+ C4A56.8uF10%

R7M910K

.

5%

R7M910K

.

5%

R1N411K

.1%

R1N411K

.1%

C7N222UFC7N222UF

R1

N3

31

0K

R1

N3

31

0K

R7M1010K

.5%

R7M1010K

.5%

4 5FB2A3D 60OHM-100MHZFB2A3D 60OHM-100MHZ

C4A10.1uF

.10%

C4A10.1uF

.10%

R1N28330R1N28330

VCC16

C1+1

C1-3

C2+4

C2-5

V+2

V-6

T1IN11

R1OUT12

T1OUT14

R1IN13

GND15

T2IN10

T2OUT7

R2OUT9

R2IN8

U7B1

MAX3232_RS232_TRNCVR

U7B1

MAX3232_RS232_TRNCVR

R1N36330R1N36330

C1N50.1uF20%

C1N50.1uF20%

R1N26 1KR1N26 1K

9

814

3

12

+

-

U1B1C

LM339

+

-

U1B1C

LM339

C4M20.1uF

.10%

C4M20.1uF

.10%

VC

C2

6

C1+28

C1-24

C2+1

C2-2

V+27

V-3

T1IN14

T2IN13

T3IN12

R2OUTB20

R2OUT18

R3OUT17

R4OUT16

R5OUT15

R1OUT19

T1OUT9

T2OUT10

T3OUT11

R1IN4

R2IN5

R3IN6

R4IN7

R5IN8

FORCEON23

FORCEOFF#22

INVALID#21

GND25

U6A1

MAX3243

U6A1

MAX3243

12

CR1B6GREENCR1B6GREEN

9

814

3

12

+

-

U1B3C

LM339

+

-

U1B3C

LM339

R7M1110K

.5%

R7M1110K

.5%

R4M210KR4M210K

R7M121K

5%

R7M121K

5%

5

42

3

12

+

-

U1B3A

LM339

+

-

U1B3A

LM339

5

42

3

12

+

-

U1B1A

LM339

+

-

U1B1A

LM339

C7N1 0.1uF

.10%C7N1 0.1uF

.10%

R1P21K

.1%

R1P21K

.1%

R7M61K

5%

R7M61K

5%

TXD_RC7

GND8

VCC6

SD5

RXD4

TXD_IR3

IO_VCC2

LED_A1

SHLD9

U4A1

HSDL-3021_021

U4A1

HSDL-3021_021

32

1

CON3_HDR

J8B2

CON3_HDR

J8B2

3 6FB2A5C 60OHM-100MHZFB2A5C 60OHM-100MHZ

12

CR1B7GREENCR1B7GREENR

1N

13

10

KR

1N

13

10

K

11

1013

3

12

+

-

U1B3D

LM339

+

-

U1B3D

LM339

3 6FB2A3C 60OHM-100MHZFB2A3C 60OHM-100MHZ

12

CR1B1GREENCR1B1GREEN

32

1

CON3_HDR

J7A2

CON3_HDR

J7A2

C1N80.1uF20%

C1N80.1uF20%

12

CR1B2GREENCR1B2GREEN

C1N20.1uF20%

C1N20.1uF20%

C7B2 0.1uF

.10%C7B2 0.1uF

.10%

R4A1 4.7R4A1 4.7

R1N17 1KR1N17 1K

31

2

Q7M1BSS138

Q7M1BSS138

R4M4 3.9R4M4 3.9

R1P4 1KR1P4 1K

C6A222UFC6A222UF

R1N21 1KR1N21 1K

R1N12330R1N12330

4 5FB2A5D 60OHM-100MHZFB2A5D 60OHM-100MHZ

R1N43330R1N43330

R7A510K

.

5%

R7A510K

.

5%

32

1

CON3_HDR

J7A1

CON3_HDR

J7A1

R1

N1

61

0K

R1

N1

61

0K

R1

N3

71

0K

R1

N3

71

0K

R1N38 1KR1N38 1K

C6M30.1uF

.10%

C6M30.1uF

.10%

12

CR1B3GREENCR1B3GREEN

C4M10.1uF

.10%

C4M10.1uF

.10%

C6M80.1uF

.10%

C6M80.1uF

.10%

R1N15330R1N15330

R4M30.0021%

R4M30.0021%

594837261

GNDRIDTRCTSTXDRTSRXDDSRDCD

J2A2A

2IN1

GNDRIDTRCTSTXDRTSRXDDSRDCD

J2A2A

2IN1

1 8FB2A3A 60OHM-100MHZFB2A3A 60OHM-100MHZ

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Page 40: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SMB_BS_CLK

NMI_GATE

SMC_WAKE_SCI#

SMC_RUNTIME_SCI#

KBC_SCANOUT4

KBC_NUMLOCK

KBC_SCANOUT5

KBC_SCANOUT14

PLT_RST_R

KBC_SCANOUT2

KBC_SCANOUT0

KBC_SCANOUT6

KBC_SCANOUT8KBC_SCANOUT9

KBC_SCANOUT11

KBC_SCANOUT15

KBC_SCANOUT10

KBC_SCANOUT13

MD1

KBC_SCANOUT3

KBC_SCANOUT7

KBC_SCANOUT1

KBC_SCANOUT12

KBC_SCROLLOCKKBC_CAPSLOCK

DOCK_SYS_PWRGD#

SMB_BS_DATA

KBC_SCANIN1

KBC_SCANIN6KBC_SCANIN7

KBC_SCANIN0

KBC_SCANIN4KBC_SCANIN5

KBC_SCANIN3KBC_SCANIN2

AC_PRESENT

H8_P91_IRQ1#

LE

D_

NU

M

LE

DD

1

LE

D_

SC

RO

LL

LE

DD

3

LE

D_

CA

PS

LE

DD

2

PM_LAN_ENABLE

PBATT_R

ALS_CLKALS_DATA

EC_THERM_STRAP

SMC_EXTSMI#

PM_LAN_ENABLE_H8

H8_P91_IRQ1#

PBATT_R

PM_LAN_ENABLE_H8

PM_THERM#_R

EC_BRK_CURRENT_R

EC_THERM_STRAP

IMVP_VR_ON_R

H_A20GATE_R

KBC_PE5KBC_PE4KBC_PE3KBC_PE2KBC_PE1

KBC_DISABLE#

KBC_PE0

KBC_FWE

ALL_SYS_PWRGD_R

ALS_INTR#

MD1 MD2

MD2

SMC_RES#

NMI_R

SMC_EXTALSMC_XTAL

+V3.3A_KBC 41,42

+V3.3S

+V3.3A_KBC41,42

INT_SERIRQ 23,38,43PM_CLKRUN# 23,32,38,43

LPC_AD1 21,38,43

LPC_FRAME# 21,38,43LPC_AD3 21,38,43LPC_AD2 21,38,43

LPC_AD0 21,38,43

KBC_MOUSE_DATA 42

KBC_GP_CLK 42

KBC_KB_CLK 42

KBC_MOUSE_CLK 42

KBC_KB_DATA 42

KBC_GP_DATA 42

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57

SMB_BS_CLK37,43,51,52

SMB_BS_DATA37,43,51,52

+V3.3S

SMB_THRM_CLK5,12,43SMB_THRM_DATA5,12,43

ALS_CLK17ALS_DATA17

H8S_I2C_DATA41H8S_I2C_CLK41

SMB_DATA_ME 23,43SMB_CLK_ME 23,43

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57+V3.3A_KBC41,42

+V3.3A_KBC41,42

BUF_PLT_RST# 22,43CLK_PCI_KBC 36

KBC_SCANIN[7:0] 42

PM_SUS_STAT# 23,38,43

KBC_PROG_RX# 39

KSC_LPC_DOCK# 38

DOCK_EXP_CPPE# 44

ALL_SYS_PWRGD 23,43,47

EC_SCIF_RXD_TRANSC39

SMC_ONOFF#43,56

SMB_BS_ALRT#43,51BC_ACOK43,50

PM_S4_STATE#23,32,43,44,55,57

ATX_DETECT#43,56VBRK_MON41

CPU_VCC_R_EC41

EC_BRK_CURRENT51

PSYS50

PBATT50

CPU_TACHO_FAN5,43

MCH_TACHO_FAN12,43

CPU_ICC_R_EC41

PM_SLP_S3#11,23,43,44,46,47,49,55,57

PE_OPNREQ#44DOCK_SYS_PWRGD#44

NETDETECT#43,56

DOCK_PE_DET#44

SUS_PWR_ACK23,43

RSMRST#_PWRGD41,43

KBC_SCANOUT[15:0] 42

CPU_PWM_FAN5,43

BS_DISB# 43,51

BS_CHGB# 43,51BS_CHGA# 43,51BS_CLR_LTCH# 43,51

BC_SHDN 50

SMC_SHUTDOWN 43,56

PM_LAN_ENABLE 23,33,43

PM_PWRBTN# 23,43

EC_SCIF_TXD_TRANSC39

PM_RSMRST#23,43,56

IMVP_VR_ON43

PM_THRM#5,12,23,43

MCH_PWM_FAN12,43

SMC_WAKE_SCI#23,43

SMC_RUNTIME_SCI#23,43

H_A20GATE21,43

SMC_RSTGATE#41,43H_RCIN#21,43

SMC_EXTSMI#23,38,43,44

PM_BATLOW#23,43BS_DISA#43,51

ICHRM50

VCHRM50

KBC_PROG_TX#39

EC_PCIE_SLOT4_VAUX_ON26

AC_PRESENT23,43,56

LIBP_BAT_SEL43,51

LIBP_CHG_EN_A43,51+V3.3A

+V3.3A_KBC41,42

NMI_GATE 42

SMC_LID 41,43VIRTUAL_BATTERY 41ME_G3_TO_M1# 56

SMC_RST#42

PM_EXTTS#0_DIMM0_113,15

SMC_INITCLK42ALS_INTR#17

LAN_WOL_EN 23,43,55,57

GFX_PWRMN_EC41

PM_SLP_M#23,43,44,47,55,57PM_EXTTS#0_EC7

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

Embedded Controller 1 of 2

A

40 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

Embedded Controller 1 of 2

A

40 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

Embedded Controller 1 of 2

A

40 58Tuesday, August 28, 2007

Boot Mode Programming StrapsP90-P92 needs to be at VCC for boot mode programming. They arealready pulled up in the design. MD0, MD1 needs to be at Vss.System needs to supply +V3.3A to flash connector.

Shunt J8G5 as default and as external programming

MD2

1OPEN1 STUFFED

MD1

00 X

Mode Type

01

0

Run Mode STUFFED

STUFFED X1

NMI

1

J8G5 J8G3

Program Boot BlockProgram Flash

CPU Thermal Monitor Strap

Pullup = DisablePull down = Enable

EnableDisable

J8B11-2 (Default)2-3

PM_LAN_ENABLE

Normal Operation

KBCEnableDisable 1-2

J8G61-X (Default)

1-X1-2Advanced Single Chip Mode

NOTE: Stuff R9F9 forwrite protect

J8G3MD2

EnableJ9F11-2 (Default)

Disable 2-3

SMC/KSC

R9G28 4.7K 5%R9G28 4.7K 5%

TP9G1NO_STUFF

TP9G1NO_STUFF

12

CR9G1GREENCR9G1GREEN

3

1

2

Q9G2BSS138Q9G2BSS138

R8M8 10KR8M8 10K

R9V14 4.7KR9V14 4.7K

C9G318PFC9G318PF

R9V110

.

R9V110

.

R9H5

10K

.

R9H5

10K

.

R9W6 10KR9W6 10K

12

J8

G5

J8

G5

R9H28.2KR9H28.2K

R9W3 10KR9W3 10K

R9G23

100K

R9G23

100K

12

J8G6J8G6

R9G29 4.7K 5%R9G29 4.7K 5%

R9H70

NO_STUFFR9H70

NO_STUFF

R9G110

.

R9G110

.

12

J8G3J8G3

R9H10

.

R9H10

.

R9V12 8.2KR9V12 8.2K

R9F12

4.7K

R9F12

4.7K

R9G26

100KNO_STUFF

R9G26

100KNO_STUFF

R9F90

NO_STUFF

R9F90

NO_STUFF

32

1

CON3_HDR

J9F1

CON3_HDR

J9F1

32

1

CON3_HDR

J8B1

CON3_HDR

J8B1

C9G418PFC9G418PF

3

1

2

Q9G3BSS138Q9G3BSS138

R9V16 10KR9V16 10K

R9G5240R9G5240

12

CR9G3GREENCR9G3GREEN

3

1

2

Q9G1BSS138Q9G1BSS138

R9F7 4.7KR9F7 4.7K

R9G10

.

R9G10

.

R9F5 4.7KR9F5 4.7K

R9H110

.

R9H110

.

R9H12 10K

.

R9H12 10K

.

R9G6240R9G6240

R9G24 10K

.

R9G24 10K

.

R9W1 10KR9W1 10K

R9G2510K R9G2510K

R9G16 100R9G16 100

R9G3240R9G3240

R9F2 4.7KR9F2 4.7KR9F3 4.7KR9F3 4.7K

R9H130

NO_STUFFR9H130

NO_STUFF

R8H110K

.

R8H110K

.

R9F10 4.7KR9F10 4.7K

R9H3 100R9H3 100

R9F4 4.7KR9F4 4.7K

21

Y9G1

10MHZ

Y9G1

10MHZ

R9V13 4.7KR9V13 4.7K

R9G2

10K

.

R9G2

10K

.

R9G2710K

.5%

R9G2710K

.5%

R9V15 8.2KR9V15 8.2K

12

CR9G2GREENCR9G2GREEN

R9F6 4.7KR9F6 4.7K

P43/TMI1/SCK2/TCMCKI1/TCMMCI1C3

P44/TMO1/PWMU2B/TCMCYI2B1

P45/PWMU3B/TCMCKI2/TCMMCI2C2

P46/PWX0/PWMU4B/TCMCYI3D3

P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3C1

RES#E3

MD1E2

PH0/ExIRQ6#/TDPCYI2E1

NMIF4

PH1/ExIRQ7#/TDPCKI2/TDPMCI2F3

P52/SCL0F2

P51/FRxDG4

P50/FTxDG1

P97/SDA0/IRQ15#G2

P96/PHI/EXCLH1

MD2K1

PH2K2

ETRST#L1

PE4*/ETMSL2

PE3*/ETDOL4

PE2*/ETDIM1

PE1*/ETCKM2

PE0/ExEXCLM3

PA7/KIN15#/PS2CDN1

PA6/KIN14#/PS2CCM4

PA5/KIN13#/PS2BDN2

PA4/KIN12#/PS2BCR1

PA3/KIN11#/PS2ADN3

PA2/KIN10#/PS2ACR2

PA1/KIN9#/PA2DDP3

PA0/KIN8#/PA2DCR3

PF7/PWMU5AN5

PF6/PWMU4AP5

PF5/PWMU3AR5

PF4/PWMU2AM6

PF3/IRQ11#/TMOX/TDPCKI0/TDPMCI0N6

PF2/IRQ10#/TMOY/TDPCYI0R6

PF1/IRQ9#/PWMU1AP6

PF0/IRQ8#/PWMU0AM7

PG7/ExIRQ15#/ExSCLBR7

PG6/ExIRQ14#/ExSDABP7

PG5/ExIRQ13#/ExSCLAM8

PG4/ExIRQ12#/ExSDAAR8

PG3/ExIRQ11#/SCL2P8

PG2/ExIRQ10#/SDA2N9

PG1/ExIRQ9#/TMIY/TDPCKI1/TDPMCI1R9

PG0/ExIRQ8#/TMIX/TDPCYI1P9

PD7/AN15M10

PD6/AN14N10

PD5/AN13R10

PD4/AN12P10

PD3/AN11N11

PD2/AN10R11

PD1/AN9P11

PD0/AN8M11

P70/AN0N12

P71/AN1R13

P72/AN2P13

P73/AN3R14

P74/AN4P14

P75/AN5R15

P76/AN6N13

P77/AN7P15

P60/KIN0#L13

P61/KIN1#L14

P62/KIN2#L15

P63/KIN3#K12

P64/KIN4#K13

P65/KIN5#K14

P66/IRQ6#/KIN6#J12

P67/IRQ7#/KIN7#J13

PC7/TIOCB2/TCLKD/WUE15#H12

PC6/TIOCA2/WUE14#H13

PC5/TIOCB1/TCLKC/WUE13#H15

PC4/TIOCA1/WUE12#H14

PC3/TIOCD0/TCLKB/WUE11#G12

PC2/TIOCC0/TCLKA/WUE10#G13

PC1/TIOCB0/WUE9#G15

PC0/TIOCA0/WUE8#G14

P27F14

P26E13

P25E15

P24E14

P23E12

P22D15

P21D14

P20D13

P17C15

P16D12

P15C14

P14B15

P13B14

P12A15

P11C13

P10B12

PB7/RTS#D11

PB6/CTS#A12

PB5/DTR#C11

PB4/DSR#B11

PB3/DCD#/PWMU1BA11

PB2/RI#/PWMU0BD10

PB1/LSCIA10

PB0/LSMI#B10

P30/LAD0D9

P31/LAD1C9

P32/LAD2A9

P33/LAD3B9

P34/LFRAME#D8

P35/LRESET#C8

P36/LCLKA8

P37/SERIRQD7

P80/PME#C7

P81/GA20A7

P82/CLKRUN#B7

P83/LPCPD#D6

P84/IRQ3#/TxD1C6

P85/IRQ4#/RxD1A6

P86/IRQ5#/SCK1/SCL1B6

P40/TMI0/TxD2/TCMCYI0A5

P41/TMO0/RxD2/TCMCKI0/TCMMCI0B5

P42/SDA1/TCMCYI1D5

PH3C4

PH4D4

PH5B3

XTALA2

EXTALB2

P94/IRQ13#J4

P91/IRQ1#J2

P92/IRQ0#J1

P90/IRQ2#K4

P95/IRQ14#H2

P93/IRQ12#J3

U9G2A

H8S2117 BGA176

U9G2A

H8S2117 BGA176

www.laptop-schematics

.com

Page 41: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H8S_EEPROM_WPVBRK_MONVBRK_MON_IN

VCL

GFX_PWRMN_R_EC

CPU_VCC_EC

CPU_ICC_EC

VIRTUAL_DOCK_DET#

HDA_DOCK_EN#_R

VIRTUAL_DOCK_DET#

DOCK_PE_PWRGD#

MCH_TSATN_EC

MCH_TSATN_LVL

MC

H_

TS

AT

N_

Q

MCH_TSATN_R

MCH_TSATN_EC

HYBRID_GFX_SW

HYBRID_GFX_SW

HYBRID_GFX_SW

HYBRID_GFX_SW

GND_SYS_CURRENT

GND_SYS_CURRENT

AGND_VCORE

AGND_VCORE

AGND_VCORE

H8S_I2C_CLK 40H8S_I2C_DATA 40

+V3.319,27,32,39,42,43,55,57

+VAC_IN_L44,50+V3.3A

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A_KBC 40,42

+V3.3A_KBC40,42

+V3.3A

+VREF_ADC51

+V3.3A_KBC 40,42

PLT_RST# 7,19,22,25,26,38,57

PCI_RST# 22,32

SMC_RSTGATE# 40,43

CPU_VCC52

CPU_ICC52

GFX_VR_PWRIN49,52

VBRK_MON 40

SMC_LID40,43

VIRTUAL_BATTERY40

GFX_PWRMN_EC 40

CPU_VCC_R_EC 40

CPU_ICC_R_EC 40

EC_PCIE_SLOT3_VAUX_ON26

PLT_GATED_RST#19

PCI_GATED_RST#32

+V3.3A+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57

DOCK_PWR_EN#44

DOCK_PE_PWRGD#44DOCK_PE_RST#44DOCK_PE_QSEN#44DOCK_CRT_EN#16DOCK_LAN_EN#34

VIRTUAL_BATTERY 40

RTC_RST# 21ND_SW#56

BIOS_REC23

VIRTUAL_DOCK_DET#

+V3.3A

+V5A3A_MBL_PWRGD45

ATX_PWROK56

RSMRST#_PWRGD 40,43

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,43,48,49,52,55,56,57

+V1.05S_ICH24

VIRTUAL_DOCK_DET#

SMC_LID 40,43

LIBP_CHG_EN_B51

CHGA_EN#51CHGB_EN#51

DOCK_TV_EN#18

MCH_TSATN#7

HDA_DOCK_EN# 21,27

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Embedded Controller 2 of 2

A

41 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Embedded Controller 2 of 2

A

41 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Embedded Controller 2 of 2

A

41 58Tuesday, August 28, 2007

LAYOUT NOTE: PLACE R, C close toH8 input pins

LAYOUT NOTE: PLACE R, C close toH8 input pins

For External H8 ADC monitor NO_STUFF : R9W7 (Default STUFF) STUFF : R2N19

LAYOUT NOTE: PLACE R, C close toH8 input pins For External H8 ADC monitor

NO_STUFF : R9W5 (Default STUFF) STUFF : R1N27

For Internal H8 ADC monitor STUFF : R9W8 (Default NO_STUFF) NO_STUFF : R1B4

12

J9H4J9H4

R8H51K

.5%

R8H51K

.5%

R2Y4

15K

.1%

R2Y4

15K

.1%

R8W110KR8W110K

C9V30.1uF

.10%

C9V30.1uF

.10%

R9W50

.5%

R9W50

.5%

R8H6 330R8H6 330

R8V6100.

R8V6100.

R9W80

NO_STUFF5%

R9W80

NO_STUFF5%

C9W20.1uF

.10%

C9W20.1uF

.10%

R9H810K R9H810K

21

3

SW9H1

SPDT_SLIDE

SW9H1

SPDT_SLIDE

R8V74.7K

.5%

R8V74.7K

.5%

R9H1810K

.

R9H1810K

.

5

3

4

CR8H1A3904CR8H1A3904

R8H8 0.0021%

R8H8 0.0021%

C9V20.1uF

.10%

C9V20.1uF

.10%

R9H6 100

.

1%R9H6 100

.

1%

A01

A12

A23

GND4

SDA5

SCL6

WP7

VCC8

U8V1

AT24C02N

U8V1

AT24C02N

3

1

2

Q8H2BSS138Q8H2BSS138

R7J110K R7J110K

R2F20 100KR2F20 100K

C9H20.1uF

.10%

C9H20.1uF

.10%

PJ2C10

PJ1B8

PJ0C5

VSS9A4

VSS10B4

NC7A3

PJ7K15

PJ6J14

PJ5F15

PJ4A14

PJ3C12

PI7G3

PI6H4

PI5H3

PI3L3

PI2M5

PI1N7

PI0N8

PI4K3

NC6L12

NC5M13

NC4M12

NC3M9

NC2N4

NC1E4

VSS8A13

VSS7B13

VSS6F13

VSS5F12

VSS4R4

VSS3P4

VSS2D1

VSS1D2

AVSS1R12

AVSS2P12

VCC1A1

VCC2P1

VCC3P2

VCC4J15

AVCC1N14

AVCC2N15

AVref1M14

AVref2M15

VCLF1

U9G2B

H8S2117 BGA176

U9G2B

H8S2117 BGA176

C9V10.1uF

.10%

C9V10.1uF

.10%

R8V84.7K

.5%

R8V84.7K

.5%

3

1

2

Q8H3BSS138

Q8H3BSS138

R8V910K

NO_STUFF1%

R8V910K

NO_STUFF1%

12

J9H3J9H3

13

CR4W1

BAT54

CR4W1

BAT54

21

3

SW9H3

SPDT_SLIDE

SW9H3

SPDT_SLIDE

R9W20

.

R9W20

.

R9W70

.5%

R9W70

.5%

21

3

SW9H2

SPDT_SLIDE

SW9H2

SPDT_SLIDE

C2Y31uF

.20%

C2Y31uF

.20%

2468

13

79111315

10121416

J8F1

2X8_HDR_KEY12

J8F1

2X8_HDR_KEY12

2

6

1

CR8H1B3904CR8H1B3904

R9C210K R9C210K

C9H30.1uF

.10%

C9H30.1uF

.10%

C2Y10.1uF

.10%16V

C2Y10.1uF

.10%16V

R9W4 100

.

1%R9W4 100

.

1%

21

3

SW7J1

SPDT_SLIDE

SW7J1

SPDT_SLIDE

R9H1610K

.

R9H1610K

.

C9W10.1uF

.10%

C9W10.1uF

.10%

3

21

8

4

+

-

U2J4A

AD8552

+

-

U2J4A

AD8552

R8H41K

.5%

R8H41K

.5%

R2Y54.02K

.1%

R2Y54.02K

.1%

R8W210K

R8W210K

R2P4

0

.5%

R2P4

0

.5%

C8H30.1uF

.10%

C8H30.1uF

.10%

C8G30.1uF10%.

C8G30.1uF10%.

C9V40.1uF

.10%

C9V40.1uF

.10%

C9H10.1uF

.10%

C9H10.1uF

.10%

C8H222uFC8H222uF

R8H7

54.9

1%

R8H7

54.9

1%

R9H4 100

.

1%R9H4 100

.

1%

www.laptop-schematics

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Page 42: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GP_DATAGP_CLK

TP_INVD2

PS

2_

PW

R_

L

SMC_INIT_CLK3SMC_INIT_CLK2

SMC_RST SMC_INITCLK#

MOUSE_DATA

INVD2

SMC_INIT_CLK1

SMC_INIT_CLK4

KBD_DATA

SMC_RST#_D

MOUSE_CLK

KBD_CLK

OE#_PS2

KBC_SCANIN0KBC_SCANIN3 KBC_SCANIN2

KBC_SCANIN7KBC_SCANIN4KBC_SCANIN5KBC_SCANIN6

KBC_SCANIN1

KBC_SCANOUT6

KBC_SCANOUT1 KBC_SCANOUT0

KBC_SCANOUT13

KBC_SCANOUT2KBC_SCANOUT4

KBC_SCANOUT9

KBC_SCANOUT12

KBC_SCANOUT3

KBC_SCANOUT14

KBC_SCANOUT5

KBC_SCANOUT11 KBC_SCANOUT10

KBC_SCANOUT7

KBC_SCANOUT15

KBC_SCANOUT8

L_

KB

D_

CL

K

KBD_CLK

MOUSE_CLK

L_MOUSE_CLK

GP_CLK

L_GP_CLK

L_

KB

D_

DA

TA

KBD_DATA

GP_DATA

MOUSE_DATA

L_GP_DATA

SMC_INITCLK_J

L_MOUSE_DATA

L_PS2_PWR

KBC_GP_CLK40

KBC_KB_CLK40

KBC_MOUSE_CLK40

KBC_GP_DATA40

KBC_KB_DATA40

KBC_MOUSE_DATA40

+V3.3A_KBC40,41

+V5_PS2

+V3.3A_KBC40,41

+V3.3A_KBC40,41

+V5_PS2

+V5_PS2

+V5_PS2

+V5_PS2

+V5_PS2

+V5_PS2

+V5_PS2

+V5_PS2

+V3.3A_KBC40,41

+V3.319,27,32,39,41,43,55,57 +V3.319,27,32,39,41,43,55,57

+V5_PS2 +V5 27,32,43,48,52,55,56,57

NMI_GATE40

KBC_SCANOUT[15:0] 40

KBC_SCANIN[7:0] 40

SMC_INITCLK 40

SMC_RST# 40

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PS2

A

42 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PS2

A

42 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

PS2

A

42 58Tuesday, August 28, 2007

Circuitry provides an interrupt to the SMC every 1swhile in suspend (this allows the SMC to completehousekeeping functions while suspended)

Spare gate

CBTD has integrateddiode for 5V to 3.3Vvoltage translation

NMI JumperNOTE: Shunt J9H1 for SMC Programming

J9H1

Scan Matrix Key Board

Spare

1Hz ClockDisable ShuntEnable No Shunt (Default)

J9G2Boot Block Programming

NormalProgram No Shunt

Shunt (Default)

3

1

2

Q9H1BSS138

.

Q9H1BSS138

.

R9G10 100KR9G10 100K

FB1A4

60ohm@100MHz.

FB1A4

60ohm@100MHz.

45

RP1B1D4.7KRP1B1D4.7K

18

RP1B2A4.7KRP1B2A4.7K

C1A647pFC1A647pF

11 10

7

14U9F2E

74HC04

U9F2E

74HC04

36

RP

1B

2C

4.7

K

RP

1B

2C

4.7

K

R9V3 100

.

R9V3 100

.R9V1100KR9V1100K

R9F1 100

.

R9F1 100

.

FB1A7

60ohm@100MHz.

FB1A7

60ohm@100MHz.

1 2

7

14U9F2A

74HC04

U9F2A

74HC04

135791113151719

2468

10121416

202123252729

22

18

24262830

J9E1

2x15-SHD-HDR

J9E1

2x15-SHD-HDR

18

RP1B1A4.7KRP1B1A4.7K

3

6

CP1B1C47PFCP1B1C47PF

C9G14.7uF

.10%

C9G14.7uF

.10%

27

RP1B1B4.7KRP1B1B4.7K

R1A1 0.002

.

1%R1A1 0.002

.

1%

GN

D1

RST#2

VC

C3

U9V1

MAX809

U9V1

MAX809

36

RP1B1C4.7KRP1B1C4.7K

FB1A3

60ohm@100MHz.

FB1A3

[email protected]

5

CP1B1D47PFCP1B1D47PF

FB1A5

60ohm@100MHz.

FB1A5

60ohm@100MHz.

C9N10.1uF20%.

C9N10.1uF20%.

FB1A631Ohm@100MHz

.

FB1A631Ohm@100MHz

.

1A13

1A37

1A511

2A217

2A421

1A24

1A48

2A114

2A318

2A522

1OE#1

2OE#13

1B12

1B36

1B510

2B216

2B420

1B25

1B49

2B115

2B319

2B523

VCC24

GND12

U8B1

SN74CBTD3384

.

U8B1

SN74CBTD3384

.

R9H17 1MR9H17 1MC9U10.1uF20%.

C9U10.1uF20%.

13 12

7

14U9F2F

74HC04

U9F2F

74HC04

9 8

7

14U9F2D

74HC04

U9F2D

74HC04

C1M147pFC1M147pF

12

+

F1A11.1A

+

F1A11.1A

R8N1100

.

R8N1100

.

1 2

J9G2J9G2

FB1A8

60ohm@100MHz.

FB1A8

60ohm@100MHz.

3

1

2

Q9H4BSS138

.

Q9H4BSS138

.

5 6

7

14U9F2C

74HC04

U9F2C

74HC04

R9V2100K

R9V2100K

12

J9H1J9H1

3 4

7

14U9F2B

74HC04

U9F2B

74HC04

27

RP1B2B4.7KRP1B2B4.7K

C1A522uFC1A522uF

C1B10.1uF20%.

C1B10.1uF20%.

45

RP

1B

2D

4.7

KR

P1

B2

D4

.7K

FB1A2

60ohm@100MHz.

FB1A2

60ohm@100MHz.

2

7

CP1B1B47PFCP1B1B47PF

1

8

CP1B1A47PFCP1B1A47PF

11

22

33

4

4

55

66

77

88

9

9

1010

1212

1111

1313

1414

1515

1616

1717

J1A1

DUAL_PS2

J1A1

DUAL_PS2

www.laptop-schematics

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Page 43: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PM_CLKRUN#

PM_SUS_STAT#

LPC_AD0

PM_DPRSLPVR

INT_SERIRQ

BUF_PLT_RST#

PM_CLKRUN#

LPC_FRAME#

LPC_AD3

+V1.05S_CPU_RSVDSTPCLK#

LPC_AD1LPC_AD2

+V3.3A_R1_TPM

+V3.3S_R1_TPM

+V5_R1_TPM

LPC_AD1 21,38,40

INT_SERIRQ 23,38,40

LPC_AD221,38,40

SMB_THRM_DATA5,12,40

SMB_BS_DATA37,40,51,52

LPC_AD021,38,40

SMB_DATA_S4 19,23

SMB_BS_CLK37,40,51,52

SMB_THRM_CLK5,12,40

LPC_AD3 21,38,40

+V5_LPCSLOT

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,48,49,52,55,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,44,45,46,47,48,50,51,52,55,56,57 +V5 27,32,42,48,52,55,56,57

+V3.3_LPCSLOT

+V12S25,26,30,31,32,55,57

+V5 27,32,42,48,52,55,56,57

+V5_LPCSLOT

+V3.3_LPCSLOT

+V3.3_LPCSLOT

+V3.319,27,32,39,41,42,55,57

+V3.3A

+V12S 25,26,30,31,32,55,57

+V5_LPCSLOT

+V1.05S_CPU 3,4,20,35,39,52,54

SMB_DATA_ME 23,40SMB_CLK_ME 23,40

RSMRST#_PWRGD 40,41

SUS_PWR_ACK 23,40

PM_SLP_M# 23,40,44,47,55,57

LAN_WOL_EN 23,40,55,57

CLK_PCI_LPC 36

H_STPCLK#3,21

SMC_ONOFF#40,56

SUS_CLK23

SMB_CLK_S419,23

SMB_BS_ALRT#40,51

PM_SUS_STAT# 23,38,40

SMC_LID40,41

LPC_FRAME#21,38,40

PM_SLP_S3#11,23,40,44,46,47,49,55,57PM_S4_STATE#23,32,40,44,55,57

BC_ACOK 40,50

ATX_DETECT# 40,56

LPCSLOT_B12

ALL_SYS_PWRGD 23,40,47

CLK_REF_LPC35

TPM_DRQ#0 38

BUF_PLT_RST#22,40

NETDETECT#40,56

PM_DPRSLPVR 7,23,52

CPU_TACHO_FAN 5,40

MCH_TACHO_FAN12,40

CLK_PCI_TPM36

PM_SLP_M# 23,40,44,47,55,57

BS_DISB# 40,51

H_CPUSLP# 3,6H_DPSLP# 3,21

PM_STPCPU# 23,35PM_STPPCI# 23,35

BS_CLR_LTCH# 40,51

BS_CHGA# 40,51

PCI_PME# 22,32CPU_PWM_FAN 5,40

BS_CHGB# 40,51

PM_RI# 23,38

H_DPRSTP# 3,7,21

BS_DISA# 40,51

AC_PRESENT 23,40,56SMC_RUNTIME_SCI#23,40

PM_RSMRST#23,40,56

H_NMI3,21

LPC_DRQ#0 38

SMC_SHUTDOWN40,56

PM_PWRBTN#23,40

H_A20GATE21,40

SMC_EXTSMI#23,38,40,44

LPC_DRQ#138

SMC_RSTGATE#40,41

IMVP_VR_ON 40

LPCS_PME# 38

PM_BATLOW#23,40

PM_LAN_ENABLE23,33,40

H_SMI#3,21

SMC_WAKE_SCI#23,40

PM_THRM#5,12,23,40

H_PWRGD3,21

MCH_PWM_FAN 12,40

H_RCIN#21,40PM_CLKRUN# 23,32,38,40

LIBP_BAT_SEL40,51 LIBP_CHG_EN_A 40,51

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LPC Slot and TPM Header

A

43 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LPC Slot and TPM Header

A

43 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

LPC Slot and TPM Header

A

43 58Tuesday, August 28, 2007

CAD NOTE:

Note: LPC_SLOT_B12 , H_STPCLK# and +V1.05S_CPU have beenrouted to LPC slot pins testing purpose.

Place close to LPC Slot J8E1

TPM HEADER

LPC SIDE BAND HEADER

LPC SLOT

Decaps for LPC Slots

R8F20

NO_STUFF R8F20

NO_STUFF

1 23 45 67 8

J1G2

8Pin HDR

J1G2

8Pin HDR

TP7E1NO_STUFF TP7E1NO_STUFF

C8E40.1uF20%

C8E40.1uF20%

TP7B1NO_STUFF TP7B1NO_STUFF

R9M1 0.0021%

R9M1 0.0021%

R8E3 0.0021%

R8E3 0.0021%

C9A20.1uF20%

C9A20.1uF20%

R9A3 0.0021%

R9A3 0.0021%

C8E322uFC8E322uF

R6V110

NO_STUFF

R6V110

NO_STUFF

R8F1 0.0021%

R8F1 0.0021%

C9A40.1uF20%

C9A40.1uF20%

TP6H1NO_STUFF TP6H1NO_STUFF

+V12S_1B1

+V12S_2A1

SUSCLK_32KHZB2

NC1(-12V)A2

GND1B3

TACHO_FANB4

GND2A3

+V3_3B5

PM_DPRSLPVRA4

NC7B6

GND3B7

+V3_1A5

NC8B8

NC2A6

NC9(NETDETECT#)B9

GND4B10

GND5A7

LIBP_BAT_SELB11

NC3A8

NC10(CPU_PECI)B12

GND6B13

NC4A9

+V3ALWAYSB14

GND7A10

NC11(STPCLK#)B15

CPU_RESET#B16

LIBP_CHG_ENA11

KBC_A20_GATEB17

NC5A12

GND8B18

+V5_3B20

+V5_1A13

LDRQ1#B21

NC6(VTTCPU)A14

LFRAME#B22

GND9B23

GND10A15

LSMI#B19

LAD2B24

SERIRQA16

LAD0B25

GND11B26

CLKRUN#A17

LRST#B27

GND12A18

GND13B28

OSC_14MHZB29

+V3_4B30

+V5_2A20

PWM_FANA19

LDRQ0#A21

GND14A22

LAD3A23

LAD1A24

GND15A25

LCLKA26

LPCPD#A27

GND16A28

PME#A29

+V3_2A30

KEY

J8E1

60Pin_CardCon

KEY

J8E1

60Pin_CardCon

2

68

13579

111315

10121416

17 1819 20

J9A1

2x10-HDR_P4KEY

J9A1

2x10-HDR_P4KEY

C8F20.1uF20%

C8F20.1uF20%

R9M2 0.0021%

R9M2 0.0021%

TP9C1NO_STUFF TP9C1NO_STUFF

C8G20.1uF20%

C8G20.1uF20%

TP9A2NO_STUFF TP9A2NO_STUFF

C8G10.1uF20%

C8G10.1uF20%

A11

A33

A55

A77

A99

A1111

A1313

A1515

A1717

A1919

A2121

A2323

A2525

A2727

A2929

A3131

A3333

A3535

A3636

A3434

A3232

A3030

A2828

A2626

A2424

A2222

A2020

A1818

A1616

A1414

A1212

A1010

A88

A66

A44

A22

A3737

A3939

A3838

A4040

J9G1

LPC Sideband Header

J9G1

LPC Sideband Header

TP9B1NO_STUFF TP9B1NO_STUFF

C8F122uFC8F122uF

C9A50.1uF20%

C9A50.1uF20%

TP6G2NO_STUFF TP6G2NO_STUFF

www.laptop-schematics

.com

Page 44: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SMB_DATA_DOCK

SMI#_DOCK

SMB_CLK_DOCK

TP_1A5

TP_1B5

PCIE_WAKE#_DOCK

PCIE_WAKE#_DOCK

SMB_DATA_DOCK

PE_OPNREQ#

SMB_CLK_DOCK

SMI#_DOCK

HDA_SPKR_DOCK

TP_2B2TP_2B3TP_2B4TP_2B5

TP_2B1TP_2A3TP_2A2TP_2A1

TP_2A4TP_2A5

PE_OPNREQ#

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,45,46,47,48,50,51,52,55,56,57

LAN_MDI0N_Q_DOCK 34LAN_MDI0P_Q_DOCK 34

LAN_MDI1P_Q_DOCK 34

SMB_CLK_A123,25,26,32SMB_DATA_A123,25,26,32

CRT_DDC_CLK_DOCK16CRT_DDC_DATA_DOCK16

LAN_MDI2N_Q_DOCK34LAN_MDI3P_Q_DOCK34LAN_MDI3N_Q_DOCK34

LAN_MDI1N_Q_DOCK34LAN_MDI2P_Q_DOCK34

+V5A 24,29,34,38,46,47,50,51,56,57

+VAC_IN_L41,50

+V3.3A

+V3.3A_1.5A_HDA_IO24,27,28

+V1.8_VCT_LAN_DOCK34

USB_PN9_R22

USB_PP9_R22

SATA_TXP4_DOCK 21SATA_TXN4_DOCK 21

LAN_LED_100#_DOCK 34

PM_SLP_S3#11,23,40,43,46,47,49,55,57

PM_S4_STATE#23,32,40,43,55,57

PM_SLP_M#23,40,43,47,55,57

PCIE_TXN1_DOCK 22

PCIE_TXP1_DOCK 22

PCIE_TXP2_DOCK 22PCIE_TXN2_DOCK 22

CLK_PCIE_DOCK 36CLK_PCIE_DOCK# 36

HDA_DOCK_RST# 21,27

CRT_HSYNC_DOCK16

CRT_VSYNC_DOCK16

CRT_RED_DOCK16

CRT_BLUE_DOCK16

CRT_GRN_DOCK16

LAN_LED_LINK#_DOCK34

HDA_SYNC_DOCK27HDA_SDO_DOCK27

TV_DACC_OUT_DOCK 18

TV_DCONSEL1_DOCK 18

TV_DACB_OUT_DOCK 18

TV_DACA_OUT_DOCK 18

TV_DCONSEL0_DOCK18

LAN_LED_1000#_DOCK34

HDA_SPKR 23,27

SATA_RXP4_DOCK 21SATA_RXN4_DOCK 21

HDA_SDATAIN_DOCK27

DOCK_PE_DET#40

DOCK_SYS_PWRGD#40PS_ON_SW#56

RSTBTNDB 56

DOCK_EXP_CPPE#40

PCIE_RXP1_DOCK 22

PCIE_RXN2_DOCK 22PCIE_RXP2_DOCK 22

PCIE_RXN1_DOCK 22

PCIE_WAKE#19,23,25,26SMC_EXTSMI#23,38,40,43

HDA_BCLK_DOCK 27

CLK_REQ#_DOCK 36

DOCK_PE_PWRGD# 41

DOCK_PWR_EN# 41

DOCK_PE_RST# 41

DOCK_PE_QSEN#41

PE_OPNREQ# 40

AMPS_CONTROL50

+V3.3M_WOL22,24,33,34,48,55,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Docking

A

44 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Docking

A

44 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Docking

A

44 58Tuesday, August 28, 2007

PCI-Express Docking Interface

Reserved

NOTE: Power pins ratedat 7A per pin.

Reserved

Note: PE_DET# - GND in CRB,Shorted to PE_DET# inDocking Board

R9C3100K5%

R9C3100K5%

1A13

1A37

1A511

2A217

2A421

1A24

1A48

2A114

2A318

2A522

1OE#1

2OE#13

1B12

1B36

1B510

2B216

2B420

1B25

1B49

2B115

2B319

2B523

VCC24

GND12

U9C1

SN74CBTD3384

U9C1

SN74CBTD3384

C9P20.1uF20%

C9P20.1uF20%

R9C1 10K

.

5%R9C1 10K

.

5%

S1S1

S2S2

S3S3

S4S4

S5S5

S7S7

S8S8

S9S9

S10S10

S12S12

S13S13

S14S14

S15S15

S16S16

S17S17

S18S18

S19S19

S20S20

S21S21

S23S23

S24S24

S25S25

S26S26

S27S27

S28S28

S29S29

S30S30

S31S31

S32S32

S33S33

S34S34

S35S35

S36S36

S37S37

S38S38

S43S43

S44S44

S45S45

S46S46

S47S47

S48S48

S49S49

S51S51

S52S52

S53S53

S54S54

S56S56

S57S57

S58S58

S60S60

S61S61

S62S62

S64S64

S65S65

S66S66

S67S67

S68S68

S69S69

S70S70

S71S71

S72S72

S73S73

S74S74

S75S75

S77S77

S80S80

S85S85

S86S86

S87S87

S88S88

S89S89

S90S90

S91S91

S92S92

S93S93

P1P1

P2P2

P3P3

P4P4

G1G1

G2G2

G3G3

G4G4

G5G5

G6G6

G7G7

G8G8

G9G9

G10G10

G11G11

G12G12

S101S101

S103S103

S104S104

S105S105

S107S107

S108S108

S109S109

S110S110

S111S111

S112S112

S113S113

S114S114

S115S115

S116S116

S119S119

S120S120

S121S121

S122S122

S127S127

S128S128

S129S129

S130S130

S131S131

S132S132

S133S133

S135S135

S136S136

S137S137

S139S139

S140S140

S141S141

S143S143

S144S144

S145S145

S158S158

S147S147

S148S148

S149S149

S150S150

S151S151

S152S152

S153S153

S154S154

S155S155

S156S156

S157S157

S161S161

S162S162

S163S163

S164S164

S95S95

S96S96

S97S97

S99S99

S100S100

S79S79

M84M84

M126M126

J9C2

PCI-E DOCKING CONN

J9C2

PCI-E DOCKING CONN

R9E50 NO_STUFFR9E50 NO_STUFF

www.laptop-schematics

.com

Page 45: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

51120_+V5A_MBL_Q

+V5_LDO_FILT_RC2

51120_EN1

+V

5_

LD

O_

EN

3

VR

_A

LW

_E

NA

BL

E_

R

51120_DRVH1_R

51120_COMP251120DRVH2_+VBATA_Q

51120_DRVL1_Q

51120_+V5A_MBL_QL

51120_SKIPSEL

51120_DRVL2_Q

51120_VBST1

51

12

0_

VR

_A

LW

_E

NA

BL

E

51120_CS2_R

+V

5_

LD

O_

FIL

T_

RC

1

V5A_MBL_PWRGD

51120_COMP1

V5A_MBL_PWRGD

51

12

0V

BS

T2

51120_DRVH1_Q

51

12

0_

TO

NS

EL

51

12

0D

RV

H2

_R

Q

51120DRVH2

51120_CS1_R

51

12

0V

BS

T2

_L

R

51120VBST2_Q

51120_DRVH1_+VBATA

51120_EN1_C

51120_VFB2

51120_VFB1

+V5A3A_MBL_PWRGD

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

AGND_51120

+V3.3A_MBL 56

VREF2

VREF2

+V3_LDO

+V5_LDO_FILT

+V5_LDO_FILT

+V5A_MBL56

+V3.3A

+VBATA 26,46,47,56,57

+V3.3A_MBL56

+VBATA 26,46,47,56,57

+V5_LDO

+V5A_MBL 56

+V5A_MBL 56

+VBATA26,46,47,56,57+V3_LDO

+V3.3A_MBL 56

VREF2

+V3_LDO

+V3_LDO

+V5_LDO

VR_ALW_ENABLE28,56

3.3V_EV

VR_ALW_ENABLE 28,56

+V5A3A_MBL_PWRGD41

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

TPS51120 System Power

A

45 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

TPS51120 System Power

A

45 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

TPS51120 System Power

A

45 58Tuesday, August 28, 2007

PWM FAULTS OFF

LDO ON

N/A

LDO OFF

D-CAP MODE

SHOULD NOT BE USED

380KHz/590KHz

SWITCHER OFF

COMP290KHz/440KHzTONSEL(CH1/2) 220KHz/330KHz (DEFAULT)

VFB1180KHz/280KHz

SHOULD NOT BE USED

AGND

VFB2 SHOULD NOT BE USED

VREF2

EN1,EN2

N/A

FLOAT

EN3,EN5SHOULD NOT BE USED

N/A

+V5_LDO_FILTPIN

5V FIXED OUTPUTN/A

N/A

SKIPSEL

3.3V FIXED OUTPUTN/A

N/A

AUTO-SKIP

PROGRAMMING TABLE

N/AAUTO-SKIP FAULTS OFF

SWITCHER ON

PWM

N/A

Icc-max=8AOCP=15A

Icc-max=8AOCP=18A

Note: RC network for manually adjusting soft start delay

C3H9, R3W12 & R3H9V5 Output Mode Selection

STUFFNO_STUFFSTUFF

R3H8Fixed Output Mode

NO_STUFFAdjustable Mode (default)

V5 Mode Selection

Current ModeD_CAP Mode (default)

NO_STUFFR3W15

STUFF

R3H10, C3H10 & C3W5STUFFNO_STUFF

V3.3 Output Mode Selection

Fixed Output ModeAdjustable Mode (default)

C3W3, R3H10 & R3W9NO_STUFFSTUFF

R3H6STUFFNO_STUFF

V3.3 Mode Selection

Current ModeD_CAP Mode (default)

R3H5NO_STUFFSTUFF

R3W7, C3H4 & C3W2STUFFNO_STUFF

12

+ C3J1220uF10%.

+ C3J1220uF10%.

R3W180

.

R3W180

.

R3H110

.

R3H110

.

R3H50

.

R3H50

.

C3H20.1uF10%

NO_STUFF

C3H20.1uF10%

NO_STUFF

C3H4100pF NO_STUFF

5%C3H4

100pF NO_STUFF

5%

4

5 6 7 831 2

Q3H4IRF7822Q3H4IRF7822

R3H130

.

R3H130

.

C3H610uF

.20%

C3H610uF

.20%

R3J2 0.0021%

R3J2 0.0021%

R3W610K

.

5%

R3W610K

.

5%

12

+ C3Y1220uF10%.

+ C3Y1220uF10%.

4

5 6 7 831 2

Q3H1IRF7822Q3H1IRF7822

1 2R3W1410.7K1%

R3W1410.7K1%

C3H30.47uFC3H30.47uF

3

1

2

Q3W3

BSS138

.Q3W3

BSS138

.

R3W812.4K1%

R3W812.4K1%

R3W110

NO_STUFF

R3W110

NO_STUFF

R3W730.1K

NO_STUFF1%

R3W730.1K

NO_STUFF1%

R3H180.0021%

R3H180.0021%

C4Y20.1uF

NO

_S

TU

FF

10%

C4Y20.1uF

NO

_S

TU

FF

10%

R3H120

NO_STUFF

R3H120

NO_STUFF

R3H10

.

R3H10

.

C3H130.1uF10%.

C3H130.1uF10%.

C3H80.1uF10%.

C3H80.1uF10%.

R3H80NO_STUFF

R3H80NO_STUFF

4

5 6 7 831 2

Q3H2IRF7811AQ3H2IRF7811A

1 2L3G23.3uHL3G23.3uH

R3W910K1%

R3W910K1%

VO11

COMP12

VFB13

VREF24

EN

59

EN

31

0

PG

OO

D2

11

EN

21

2

VREG521

VIN22

CS123

PGND124

EN

12

9

PG

OO

D1

30

TO

NS

EL

31

SK

IPS

EL

32

VB

ST

21

3

DR

VH

21

4

LL

21

5

DR

VL

21

6

V5FILT20

VREG319

PGND217

CS218

VB

ST

12

8

DR

VH

12

7

LL

12

6

DR

VL

12

5

GND5

VFB26

COMP27

VO28

TH33

EU3H1

TPS51120

EU3H1

TPS51120

C3W60.1uF10%

NO_STUFF

C3W60.1uF10%

NO_STUFF

R3H150

NO_STUFF

R3H150

NO_STUFF

C3H1222uFC3H1222uF

R3W20

.

R3W20

.

+ C4G4330uF20%

+ C4G4330uF20%

R3H40

.

R3H40

.

21

CR3H1

B320ANO_STUFF

CR3H1

B320ANO_STUFF

C3H91000pF5%

C3H91000pF5%

C3W52200PF

NO_STUFF

C3W52200PF

NO_STUFF

R3H910K1%

R3H910K1%

C3W2470pF

NO_STUFF5%

C3W2470pF

NO_STUFF5%

R3W1049.91%

R3W1049.91%

C3W41000pF5%

C3W41000pF5%

R3W220

NO_STUFF

R3W220

NO_STUFF

C3H510uF

.20%

C3H510uF

.20%

C3H122uFC3H122uF

1 2

L3H1

3.3uH

L3H1

3.3uH

C3H110.47uFC3H110.47uF

R3W30

.

R3W30

.

C3H10470pF

NO_STUFF5%

C3H10470pF

NO_STUFF5%

R3H140

NO_STUFF

R3H140

NO_STUFF

R3H723.7K

.1%

R3H723.7K

.1%

R3H16220K

.

5%

R3H16220K

.

5%

C3W31000pF5%

C3W31000pF5%

C3H71.0uF20%.402

C3H71.0uF20%.402

R3H60

NO_STUFF

R3H60

NO_STUFF

R3W200

.

R3W200

.

C3G80.1uF10%.

C3G80.1uF10%.

C4H10.1uF

NO

_S

TU

FF

10%

C4H10.1uF

NO

_S

TU

FF

10%

R3G50.0021%

R3G50.0021%

4

5 6 7 831 2

Q3H5IRF7811AQ3H5IRF7811A

21

CR3G2

B320ANO_STUFF

CR3G2

B320ANO_STUFF

R3W40

NO_STUFF

R3W40

NO_STUFF

R3H109.76k_1%NO_STUFF

R3H109.76k_1%NO_STUFF

R3W1240.2K1%

R3W1240.2K1%

R3W190

NO_STUFF

R3W190

NO_STUFFR3W150

.

R3W150

.

R3H1710K

.

5%

R3H1710K

.

5%

+ C3G6330uF20%

+ C3G6330uF20%

R3H2100KR3H2100K

R3H30.0021%

R3H30.0021%

www.laptop-schematics

.com

Page 46: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CANTIGA_DDR_PWRGD

1.8_VIN

DDR_BST_R DDR_BST_RC

DDR_POK_RU

DDR_DH_R

DDR_DL_R

DDR_DH_RQ

DDR_DL_RC

DDR_LX

1.8

_V

IN

DD

R_

SS

DDR_TON

DD

R_

PO

K_

RU

2

DD

R_

SH

DN

_R

U

DDR_REF

DDR_SKIP#

DDR_OVP

DDR_ILIM

DDR_AVDD

LVDS_AD

LVDS_OUT

LV

DS

_S

HD

N

+V0.9_R

DDR_FB_RR

DD

R_

VT

TR

+V

1.8

_E

VM

C_

R

DDR_REFIN

DDR_AVDD

+V1.8_L_R

SM_PWROK_U

PM

_S

LP

_S

3_

S4

_L

DO

AGND_DDR

AGND_DDR

AGND_DDR

AGND_DDR

AGND_DDR

AGND_DDR

AGND_DDR

AGND_DDR

AGND_DDR

+V3.3A

+V3.3A

+VBATA26,45,47,56,57

+V5A24,29,34,38,44,47,50,51,56,57

+V1.8_LDO10

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,47,48,50,51,52,55,56,57

+V0.915,55

+V1.89,10,13,14,48,55,57

+V1.89,10,13,14,48,55,57

PM_SLP_S4#23,55

+V1.8_EVMC_V_CNTL

PM_SYS_PWRGD48

PM_PGOOD_1_05M47

VRPWRGD_3.3M_WOL48

PM_PWROK 47

MPWROK 7,23

M_VREF_MCH7,48

+V1.8_LDO_EVMC_V_CNTL

+V3.3A

PM_SLP_S4#23,55

SM_PWROK 7

PM_SLP_S4#23,55

PM_SLP_S3#11,23,40,43,44,47,49,55,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DDR2 VR

A

46 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DDR2 VR

A

46 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DDR2 VR

A

46 58Tuesday, August 28, 2007

DDR2 VREG

Adds 3.3M to the MPWROK tree.Needed to support G3->M1 andMoff to M1 transitions.

Note: Stuff these parts for DDR3 memory only.NO_STUFF for DDR2 memory.

Note: C4B7 adjusts the soft-start time for the VTToutput. The charge rate at the SS pin is 4uA and thethreshold voltage is 1.6V. A 4700pF capacitor gives a1.88mS soft-start. This roughly matches the 1.7mSdigital soft-start built in to the switching output.

Note: C4B6 should be placed close to the VTTR pin.

NOTE: Place C4N3 and C4B8 near VTTIpin and C4B5 near REFIN pin.

NOTE: Place VTT bypass caps as close to VTT andPGND2 pins as possible. Connect VTT sense line(VTTS) separately to VTT at the point of regulation.

NOTE: R4N19to bechanged to11.5K, 1%.(for DDR3board)

Note: Keep trace from FB pin short(feedback resistors near pin).

DDR2, DDR3, EVMC (remote adjust) Selection:

STUFF : R4N19, R4N21

STUFF : R4N20

1.5V, 0.75V

1.8V, 0.9V

1.5V, 0.75V

Vout, VTTDDR2

DDR3

EVMC enabled

Resistor used Mode selected

NOTE: LX and PGND1 pin connections to the low-side FET must be made as Kelvin-sense connections.

NOTE: TAB must be star-connected to GND pin(analog gnd) and to PGND2 through R4B8(0-ohmresistor). PGND2 and the low side of the VTTbypass caps are connected to the PGND plane.

Disabled

DisabledEnabled

Enabled

UVPEnabled

200KHz

EnabledDisabled

TON (Switching Frequency Select)Resistor used: Frequency:

450KHz600KHz

R4B3

R4B4R4N6

None (Default) 300KHz

Disabled

OVP/UVP (Protection/Discharge Enable)Resistor used: OVP, DischargeR4N12 (Default)

R4N9R4B5

None (open)

DisabledEnabled

SKIP# (Pulse Skipping Enable)Resistor used: Skip mode:

R4N1R4B2(Default)

Note: Place EVMC control resistor near U6V1

Note: EU4N1 needs to be moved to MPAD.OLB

NO_STUFF : R4N19, R4N21

NO_STUFF : R4N20

NO_STUFF : R4N20STUFF : R4N19, R4N21, R4N22

Note: U4A3, R4M8, C4M4 to be stuffed only for DDR3 board

C4N410uF

.20%

C4N410uF

.20%

R5V1

0.01 1%NO_STUFF

R5V1

0.01 1%NO_STUFF

R4B1

10.

5%

R4B1

10.

5%

R5F20

0NO_STUFF

5%

R5F20

0NO_STUFF

5%

R5U28

20K1%

NO_STUFF

R5U28

20K1%

NO_STUFF

C4A910uF25VC4A910uF25V

R4B4

10KNO_STUFF

R4B4

10KNO_STUFF

R5U240

NO_STUFF

R5U240

NO_STUFF1

24

53

U4M2

74AHC1G08

.

U4M2

74AHC1G08

.

R4N220

NO_STUFF

R4N220

NO_STUFF

R4N9

10KNO_STUFF

R4N9

10KNO_STUFF

R4N50

.5%

R4N50

.5%

C5B1330uF

NO_STUFF

20%2.5V

C5B1330uF

NO_STUFF

20%2.5V

R4N1723.7K

.1%

R4N1723.7K

.1%

R4M910K

.

5%

R4M910K

.

5%

C4B61uF

.20%

C4B61uF

.20%

R4N2110K

NO_STUFF1%

R4N2110K

NO_STUFF1%

C5V322uFNO_STUFF

C5V322uFNO_STUFF

C4N510uF

.20%

C4N510uF

.20%

R4A4

0.002

.

1%

R4A4

0.002

.

1%

C6V21.0uF10%NO_STUFF

C6V21.0uF10%NO_STUFF

R4N19 10K

NO_STUFF1%

R4N19 10K

NO_STUFF1%

R4B2

10K.

R4B2

10K.

R5B2

0.002.

1%

R5B2

0.002.

1%

R4B10

0.002

.

1%

R4B10

0.002

.

1%

C4B3

0.22uF

.

20%

C4B3

0.22uF

.

20%

R5F210

NO_STUFF

5%R5F21

0

NO_STUFF

5%

C4B20.22uF

.20%

C4B20.22uF

.20%

TON1

OVP/UVP2

RE

F3

ILIM4

POK15

POK26

STBY#7

SS

8

VT

TS

9

VT

TR

10

PG

ND

21

1

VT

T1

2

VT

TI

13

RE

FIN

14

VIN

17

BST20

VD

D2

2

GN

D2

4

SK

IP#

25

AV

DD

26

TA

B2

9

TP

O2

8

SHDN#27

PGND123

FB15

DH18

OUT16

LX19

DL21

EU4N1

MAX8632

EU4N1

MAX8632

C4N10.1uF

.10%16V

C4N10.1uF

.10%16VC4B10.1uF

.10%16V

C4B10.1uF

.10%16V

R4N100

.5%

R4N100

.5%

R4B5

10KNO_STUFF

R4B5

10KNO_STUFF

R4N15100K

.1%

R4N15100K

.1%

C4N30.1uF

NO_STUFF

10%16V

C4N30.1uF

NO_STUFF

10%16V

R4N12

10K

.

R4N12

10K

.

C4A710uF25VC4A710uF25V

C4B810uF

.20%

C4B810uF

.20%

R4N110K

NO_STUFF

R4N110K

NO_STUFF

R4M710K

.1%

R4M710K

.1%

1

24

53

U4A4

74AHC1G08

.

U4A4

74AHC1G08

.

R4N70

.

R4N70

.

R6G10

NO_STUFF

R6G10

NO_STUFF

4

1 2 38765

Q4N1

IRF7834

Q4N1

IRF7834

R6V310K

NO_STUFF

5%

R6V310K

NO_STUFF

5%

R4N30

.

R4N30

.

SHDN1

IN5

OUT4

GND

2

ADJ

3

U6V1SC1563NO_STUFFU6V1SC1563NO_STUFF

21

CR4N1

MBR0530

.

CR4N1

MBR0530

.

C4B7

4700PF

C4B7

4700PF

1

24

53

U4A5U4A5

R4N6

10KNO_STUFF

R4N6

10KNO_STUFF

R4N130

.5%

R4N130

.5%

1 3

CR4B1

CMPSH-3

CR4B1

CMPSH-3

R4B3

10KNO_STUFF

R4B3

10KNO_STUFF

R4N2010K

.

R4N2010K

.

R5V210K

NO_STUFF1%

R5V210K

NO_STUFF1%

R4B80

.

R4B80

.

4

5 6 7 831 2

Q4B1IRF7811A.

Q4B1IRF7811A.

C4M40.1uF

NO_STUFF10%16V

C4M40.1uF

NO_STUFF10%16V

3

1

2

Q6F1BSS138NO_STUFF

Q6F1BSS138NO_STUFF

R4B722

.5%

R4B722

.5%

R4N18

10

.

5%

R4N18

10

.

5%

1 2

L4B1

1.0uH

L4B1

1.0uH

1

24

53

U4A3

74AHC1G08

NO_STUFF

U4A3

74AHC1G08

NO_STUFF

C4A810uF25VC4A810uF25V

C6V30.1uF

NO_STUFF10%

C6V30.1uF

NO_STUFF10%

C4M60.1uF

.10%16V

C4M60.1uF

.10%16V

R4B60

.

R4B60

. C4B5

0.1uF

.

10%

C4B5

0.1uF

.

10%

R4M812.1K

NO_STUFF1%

R4M812.1K

NO_STUFF1%

C4B41uF

.10%

C4B41uF

.10%

C4N24.7uF

.10%

C4N24.7uF

.10%

C4B1310uF

.20%

C4B1310uF

.20%

www.laptop-schematics

.com

Page 47: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

51124_DRVH151124_DRVH1

51124_DRVL151124_DRVL1

V1.05M_VIN

51124_LL151124_LL1

51124_VBST2_R

51124_DRVH1_R

51117_LL

V1.5S_VIN

51117_TRIP

51117_DRVH51117_VBST

51117_VFB

51117_TON

51117_V5FILT

51124_LL1_L51124_LL2_L

PM_1.5_1.05S_PGOOD

51117_DRVL

V1.05S_VIN

51

12

4_

TR

IP1

51

12

4_

V5

FIL

T

51

12

4_

TR

IP2

51117_LL_L

51124_VBST151124_VBST1

51124_DRVH2_R

51124_VBST1_R

PM_1.5_1.05S_PGOOD

51

11

7_

PG

OO

D

PM_PGOOD_1_05M

PM_1.5_1.05S_PGOOD

51

12

4_

PG

D1

51117_VBST_R

CANTIGA_VR_PWRGD

51

12

4_

VB

2

51

12

4_

VB

1

51117_DRVH_R

EV_VCC_1.5S_R

EV_VCC_V1.05S_R 1.05M_EV_R

51124_DRVH2

51124_PGD2

51124_VBST2

51124_LL2

51124_DRVL2

51

12

4_

TO

NS

EL

51124_TONSEL

AGND_51124

AGND_51124

AGND_51124

AGND_51124

AGND_51117

AGND_51117

AGND_51117

AGND_51124

AGND_51117

AGND_51117

AGND_51124

+VBATA26,45,46,56,57

+V5A 24,29,34,38,44,46,50,51,56,57

+VBATA26,45,46,56,57

+V5A24,29,34,38,44,46,50,51,56,57+V1.05S4,9,10,24,55

+V1.05S4,9,10,24,55

+V5A24,29,34,38,44,46,50,51,56,57

+V1.05M9,10,15,35,55+V1.05S

+V1.05M9,10,15,35,55

+V1.05M9,10,15,35,55

+V5A 24,29,34,38,44,46,50,51,56,57

+V1.5S4,10,11,24,28,55,57

+VBATA26,45,46,56,57

+V5A 24,29,34,38,44,46,50,51,56,57

+V5A

+V1.5S4,10,11,24,28,55,57

+V3.3A

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,48,50,51,52,55,56,57

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,48,50,51,52,55,56,57

PM_SLP_M# 23,40,43,44,55,57PM_SLP_S3#11,23,40,43,44,46,49,55,57

PM_SLP_S3#

PM_PWROK46

EV_VCC_V1.5S

EV_VCC_V1.05S1.05M_EV

ALL_SYS_PWRGD 23,40,43

+V5A 24,29,34,38,44,46,50,51,56,57

PM_PGOOD_1_05M 46

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Cantiga VR

A

47 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Cantiga VR

A

47 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Cantiga VR

A

47 58Tuesday, August 28, 2007

TONSEL PIN CH1 CH2

FLOAT 300kHz 360kHz

Switching Frequency

VR Current Capability

Rail I continuous Nominal OCP

+V1.05M+V1.05S

9A 15A14A3A

VR Current Capability

Rail I continuous Nominal OCP

+V1.5S 3A 7.5A

TON PIN

200K 400kHz

Switching Frequency

Power Good Logic

Note: NO_STUFF V1.5S VR for DDR3. DDR3 will generate V1.5S.

Place C5V1 closeto U5F1.10

1

3

CR5U1

BAT54

CR5U1

BAT54C4G2

22UFC4G2

22UF

C5V11uF

.20%

C5V11uF

.20%

EN_PSV1

TON2

VOUT3

V5FILT4

VFB5

PGOOD6

GND7

PGND8

DRVL9

V5DRV10

TRIP11

LL12

DRVH13

VBST14

U5F1

TPS_51117

U5F1

TPS_51117

R5U290

.

R5U290

.

R5G1 3.9

.

1%

R5G1 3.9

.

1%

R5U210

.

R5U210

.

R5U200

NO_STUFF

R5U200

NO_STUFF

DRVH121

TR

IP2

14

EN123

VBST122

VF

B1

2

GN

D3

TO

NS

EL

4

VF

B2

5

VO

11

PGD27

EN28

VBST29

V5

FIL

T1

5

LL211

DRVH210

PG

ND

21

3

DRVL119

PG

ND

11

8

TR

IP1

17

DRVL212

V5

IN1

6

LL120

PGD124

VO

26

TH

M2

5

EU5G1

TPS51124

EU5G1

TPS51124

4

3

5 6

Q4F1BIRF9910

Q4F1BIRF9910

R4V42.8K1%R4V42.8K1%

R4V30

.

R4V30

.

R5G20.002

.

1%R5G20.002

.

1%

1 2

L4G1

1.0uH

L4G1

1.0uH

C5V222UFC5V222UF

C5G40.1uF10%.

C5G40.1uF10%.

R5U22

20K1%

.

R5U22

20K1%

.

R4G4

0.002

.

1%R4G4

0.002

.

1%

C5U6270uF

.20%

C5U6270uF

.20%

R5U260

.

R5U260

.

C5F30.1uF10%.

C5F30.1uF10%.

4

3

56

Q5G2BIRF9910Q5G2BIRF9910

R5G3 10K

NO_STUFF

R5G3 10K

NO_STUFF

C4V60.1uF

.10%16V

C4V60.1uF

.10%16V

R5U230

.

R5U230

.

R5U330

.

R5U330

.

R5G60

.

R5G60

.

C5G50.1uF10%.

C5G50.1uF10%.

21

CR5G2

B320A

CR5G2

B320A

C3U1270uF

.20%

C3U1270uF

.20%

R5U307.87K

.

1%R5U307.87K

.

1%

4

5 6 7 831 2

Q5V1IRF7811A

.

Q5V1IRF7811A

.

R4G17.5K

.

1%

R4G17.5K

.

1%

C5F4

18PF

C5F4

18PF

1

24

53

U4W1

74AHC1G08

.

U4W1

74AHC1G08

.

2

1

78

Q5G2AIRF9910Q5G2AIRF9910

C4G30.1uF

.10%

C4G30.1uF

.10%

12

+ C5V4220uF10%.

+ C5V4220uF10%.

21

CR5G3

B320A

CR5G3

B320A

C5U5270uF

.20%

C5U5270uF

.20%

C5G30.1uF10%.

C5G30.1uF10%.

C5F21uF

.20%

C5F21uF

.20%

R4V20

NO_STUFFR4V20

NO_STUFF

R5H110K

.1%

R5H110K

.1%

R5V50.002

.

1%

R5V50.002

.

1%

R5F180

.

R5F180

.

C5G24.7uF

.10%

C5G24.7uF

.10%

1

3

CR5V1BAT54CR5V1BAT54

C5G11uF

.20%

C5G11uF

.20%

1

3

CR5G1BAT54

CR5G1BAT54

R5U2520K1%

.

R5U2520K1%

.

C4U1270uF

.20%

C4U1270uF

.20%

R5V30

.

R5V30

.

R5G50

.

R5G50

.

C4V522UFC4V522UF

C4G50.1uF

.10%

C4G50.1uF

.10%

R4G3

0.002

.1%

R4G3

0.002

.1%

R4F7

0.002

.

1%

R4F7

0.002

.

1%

C4F40.1uF

.10%

C4F40.1uF

.10%

C4G10.1uF10%.

C4G10.1uF10%.

1 2

L4F1

1.0uH

L4F1

1.0uH

R4G27.5K

.

1%

R4G27.5K

.

1%

C6V40.1uF

.10%

C6V40.1uF

.10%

C4V2270uF20%

C4V2270uF20%

R4V100.002

.

1%R4V100.002

.

1%

R5F153011%

R5F153011%

R5F19 12.1K

.

1%

R5F19 12.1K

.

1%

R5U32

10K

NO

_S

TU

FF

R5U32

10K

NO

_S

TU

FF

R5G4

6.49K

.

1%

R5G4

6.49K

.

1%

C4V40.1uF10%.

C4V40.1uF10%.

R5V40

.

R5V40

.

21

CR4F1B320ACR4F1B320A

R5F16200K

.1%

R5F16200K

.1%

R5F170

.

R5F170

.

2

1

7 8

Q4F1AIRF9910

Q4F1AIRF9910

R4U62.8K1%R4U62.8K1%

R4V510K

.1%

R4V510K

.1%

1 2

L5G1

1.0uH

L5G1

1.0uH

R5G70

.

R5G70

.

1

24

53

U4H1

74AHC1G08

.

U4H1

74AHC1G08

.

C4F3270uF20%

C4F3270uF20%

C7U1270uF

.20%

C7U1270uF

.20%

4

5 6 7 831 2

Q5G1IRF7822

.

Q5G1IRF7822

.

R5U270

.

R5U270

.

R4V10

NO_STUFF

R4V10

NO_STUFF

www.laptop-schematics

.com

Page 48: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VREF_DIMM1_MARGOPAMP2_SHTDN#

VREF_MCH_MARGOPAMP3_SHTDN#

OPAMP1_SHTDN#

+V3.3S_TVDAC_PWRGD+V5S_PWRGD

PP_REFIN

+V3.3S_PWRGD

PP_HYST

+V3.3M_WOL_PWRGD

UNUSED_BUF_U6A1A_P1

UN

US

ED

_B

UF

_U

6A

1A

_P

2

UN

US

ED

_B

UF

_U

6A

1A

_P

3

OPAMP4_SHTDN#

VREF_DIMM0_MARG

+V5S5,11,12,16,17,18,24,28,30,31,32,39,49,52,55,56,57+V527,32,42,43,52,55,56,57

+V527,32,42,43,52,55,56,57

+V527,32,42,43,52,55,56,57

+V5 27,32,42,43,52,55,56,57

+V527,32,42,43,52,55,56,57

+V527,32,42,43,52,55,56,57

+V527,32,42,43,52,55,56,57

+V3.3S_TVDAC10,11,55+V3.3M_WOL22,24,33,34,44,55,57

+V1.89,10,13,14,46,55,57

+V1.89,10,13,14,46,55,57

+V1.89,10,13,14,46,55,57

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,50,51,52,55,56,57+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,49,52,55,56,57

M_VREF_DIMM_A

M_VREF_MCH_A

M_VREF_DIMM_B

M_VREF_DIMM1 14

M_VREF_DIMM0 13

M_VREF_MCH 7,46

PM_SYS_PWRGD 46

VRPWRGD_3.3M_WOL46

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DDR2 VREF

A

48 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DDR2 VREF

A

48 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

DDR2 VREF

A

48 58Tuesday, August 28, 2007

VREF = 1.221V

Adds 3.3M_WOL to the MPWROK tree.

R3N1610K

NO_STUFF5%

R3N1610K

NO_STUFF5%

R3N410K

.1%

R3N410K

.1%

R4W12100KR4W12100K

C3N20.1uF

.10%

C3N20.1uF

.10%

R4N80

.

R4N80

.

R4N40

.

R4N40

.

R3B1110K

.1%

R3B1110K

.1%

R4W510K

.1%

R4W510K

.1%

R4N1610K

.

5%

R4N1610K

.

5%R4W910K

.1%

R4W910K

.1%

R4W12.4M.

R4W12.4M.

R4W1324.9K

.1%

R4W1324.9K

.1%

R3N20

.

R3N20

.

R4W313K

1%

R4W313K

1%

OUTB1

OUTA2

V+3

INA-4

INA+5

INB-6

INB+7

REF8

OUTC16

OUTD15

HYST14

IND+13

IND-12

INC+11

INC-10

V-9

U4H2

LTC1444

U4H2

LTC1444

R4W410K

.1%

R4W410K

.1%

R4N20

NO_STUFF

R4N20

NO_STUFF

R3N90

NO_STUFF

R3N90

NO_STUFF

R3B1210K

.

5%

R3B1210K

.

5%

R4N1410K

NO_STUFF

5%

R4N1410K

NO_STUFF

5%

R6P10

.

R6P10

.

R4N1110K

.

5%

R4N1110K

.

5%

C3B6220pF

.10%

C3B6220pF

.10%

9

7

8

4

6

10VDD+

GND

-

+

U4B1B

TLV2463

VDD+

GND

-

+

U4B1B

TLV2463

C3N50.1uF

.10%

C3N50.1uF

.10%

9

7

8

4

6

10VDD+

GND

-

+

U3B1BTLV2463

VDD+

GND

-

+

U3B1BTLV2463

R4W8100KR4W8100K

R4W710K

.

5%

R4W710K

.

5%

R3N1710K

.

5%

R3N1710K

.

5%

R3N110K

.1%

R3N110K

.1%

R3B1410K

NO_STUFF

5%

R3B1410K

NO_STUFF

5%

1

3

2

4

5

10VDD+

GND

-

+

U3B1ATLV2463

VDD+

GND

-

+

U3B1ATLV2463

R3N710K

NO_STUFF

5%

R3N710K

NO_STUFF

5%

R3N110

NO_STUFF

R3N110

NO_STUFF

TP4H1NO_STUFFTP4H1NO_STUFF

R4W1013K

1%

R4W1013K

1%

1

3

2

4

5

10VDD+

GND

-

+

U4B1ATLV2463

VDD+

GND

-

+

U4B1ATLV2463

R4W213K

1%

R4W213K

1%

R3B510K

.1%

R3B510K

.1%

C4W10.1uF

.10%

C4W10.1uF

.10%

R3N1310K

.1%

R3N1310K

.1%

C3N3220pF

.10%

C3N3220pF

.10%

R4W1110K

.1%

R4W1110K

.1%

C3N7220pF

.10%

C3N7220pF

.10%

R3N1510K

.1%

R3N1510K

.1%

www.laptop-schematics

.com

Page 49: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GVR_STRAP_VID1GVR_VID0

GVR_VID3GVR_VID4

GVR_VID2

GVR_STRAP_VID0GVR_VID1

GVR_VR_EN_R

GVR_V5_S0

GVR_REF

GV

R_

VID

2

GV

R_

VID

1

GV

R_

OF

S

GV

R_

VID

0

GVR_GNDS

GV

R_

TH

RM

GVR_BST_R

+V5S_GVR

GV

R_

CS

N

GV

R_

VC

C

GV

R_

CS

P

GVR_DRVL_G

GVR_DRVH_G

GVR_VRHOT#

GVR_BST

GV

R_

VC

C

GV

R_

VR

_E

N

GVR_TIME

GV

R_

PG

DL

Y

GV

R_

VB

AT

GVR_NTC

GV

R_

VID

3

GV

R_

VID

4

GV

R_

TO

N

GVR_FB

GVR_POUT

GVR_SW_PHASE

GVR_FB_R

GVR_CCV

OP_GVR_POUT_R

GVR_8552B_OUT

GVR_POUT_R-

GVR_POUT

OP_GVR_POUT_R

GVR_POUT_R+

GVR_S2_S1

GVR_STRAP_VR_ENGVR_STRAP_VID4

GVR_STRAP_VID2

GVR_STRAP_EXTRA

GVR_STRAP_VID3

GVR_VR_EN

GVR_VID0

GVR_VID4

GVR_VID1

GVR_VID2

GND_GVR_R

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

AGND_VCORE

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_GVR

GND_SYS_CURRENT

+V3.3S

+V3.3S

+V3.3S

+V5S

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,52,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,52,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,52,55,56,57

+V3.3S

+VBAT17,53,55,56,57

+VCC_GFXCORE9

+VGFX_CORE

+V3.3S

VSS_AXG_SENSE 9

VCC_AXG_SENSE 9

GFXVR_VID_17

GFXVR_EN7

GFXVR_VID_27GFXVR_VID_37GFXVR_VID_47

GFX_VR_PWRIN 41,52

GFXVR_VID_07

PM_SLP_S3#

11,23,40,43,44,46,47,55,57

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,52,55,56,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Graphics Core VR

A

49 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Graphics Core VR

A

49 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Graphics Core VR

A

49 58Tuesday, August 28, 2007

S2Input

B

C

1 1D

1A

1

S1

D

S01

1

A

1

0CB

0

Output

1

1

1

Attach VCC_AXG_SENSE and VCC_AXG_SENSE underneath Cantiga. Ground and outputresistors should be tied to +VGFX_COREbypass caps.

Connect Power ground to Controllerground under the controller

Refdes R2F21.05V (Default)1.25V 7.87K, 1%

11K, 1%

Note: Place R2G2, R2G6, R2G7 & R2G1 close to U2G1 and keepinput lines (pins 2 and 3) short. Extend GND (bothinputs) and GVR_POUT_R as a pair and connect locally tographics VR (EU3G1).

GAIN ADJUSTED FOR 4.02

Note: Extend this ground and theoutput as a pair to the point wherethe output is being delivered (A/D).

Note:Place the 0 ohm resistors close tothe source and route a thick trace from source to destination

Placement of R4T1 and R4R12Place R4R12 close to GMCH pins on +VGFX_COREPlace R4T1 close to GMCH GND pins

NO_STUFF: R2V3STUFF: R2V6

GVR_VR_ENFor Teenah

For Cantiga STUFF: R2V3NO_STUFF: R2V6

Graphics VR Controller

R3G620K

NO_STUFF1%

R3G620K

NO_STUFF1%

R2G1920K

NO_STUFF1%

R2G1920K

NO_STUFF1%

12

RT3V1100K

RT3V1100K

R2G1420K

NO_STUFF1%

R2G1420K

NO_STUFF1%

5

67

8

4

+

-

U2G1B

AD8552

+

-

U2G1B

AD8552

R2G15

20K

1%

R2G15

20K

1%

R3G213.7K

.1%

R3G213.7K

.1%

R2G13100KR2G13100K

1 2

RT3F1

1K

RT3F1

1K

R2F2 11K

.1%

R2F2 11K

.1%

R2G1

40.2K .1%

R2G1

40.2K .1%

C3G547uF20%

C3G547uF20%

R3F61K1%

R3F61K1%

4

25

31

G

S

D

Q3V3HAT2168H

G

S

D

Q3V3HAT2168H

R2G740.2K

.

1%

R2G740.2K

.

1%

R3V10

.

R3V10

.

R2G210K .1%R2G210K .1%

R2G4 101%

R2G4 101%

C3F30.22uFC3F30.22uF

R2G10 10K

.

R2G10 10K

.

R3F93.57K1%.

R3F93.57K1%.

3

21

8

4

+

- U2G1A

AD8552

+

- U2G1A

AD8552

R3V2

.002

1%

R3V2

.002

1%

R2

V4

8.2

KR

2V

48

.2K

R2G510K5%

R2G510K5%

C3F11000pF10%

C3F11000pF10%

2 4 6 8

1 3 5 7 91

11

31

5

10

12

14

16

J2H2J2H2

C3G747uF

NO_STUFF20%

C3G747uF

NO_STUFF20%

12

J4G1

NO

_S

TU

FF

J4G1

NO

_S

TU

FF

R3F4100

1%R3F4100

1%

R2G90

.5%

R2G90

.5%

C2G3 0.1uF.10%

C2G3 0.1uF.10%

C3V547uF20%

C3V547uF20%

C3V64.7uF20%

C3V64.7uF20%

1 2R4R1210

.

R4R1210

.

C2G60.1uF

.10%

C2G60.1uF

.10%

1 2R4T110

.

R4T110

.

R2

V1

18

.2K

R2

V1

18

.2K

R2G80

NO_STUFF5%

R2G80

NO_STUFF5%

R2V1430.1K

NO_STUFF

1%

R2V1430.1K

NO_STUFF

1%

C3V20.01uF10%402

C3V20.01uF10%402

C3G10.1uF

.10%

C3G10.1uF

.10%

C3G40.22uFC3G40.22uF

4

25

31

G

S

D

Q3V1HAT2164H

NO_STUFF

G

S

D

Q3V1HAT2164H

NO_STUFF

R2G610K .1%R2G610K .1%

R2

V2

8.2

KR

2V

28

.2K

C2G2

0.22uF

C2G2

0.22uF

C3V74.7uF20%

C3V74.7uF20%

21

CR3G1

B320A

CR3G1

B320A

R9H140

NO_STUFF

R9H140

NO_STUFF

C3V447uF

NO_STUFF20%

C3V447uF

NO_STUFF20%

R2

V7

8.2

KR

2V

78

.2K

R2G1820K

NO_STUFF1%

R2G1820K

NO_STUFF1%

R2V100

NO_STUFF

R2V100

NO_STUFF

C3G31.0uF20%.402

C3G31.0uF20%.402

R3F7 30.1

.1%

R3F7 30.1

.1%

R2V60NO_STUFF

R2V60NO_STUFF

C3G21000pF5%

C3G21000pF5%

R3F50.002

.

1%

R3F50.002

.

1%

C3V11.0uF20%.402

C3V11.0uF20%.402

R2G12

10K.

5%

R2G12

10K.

5%

4

25

31

G

S

D

Q3V2HAT2164H

G

S

D

Q3V2HAT2164H

R1J80

.

R1J80

.

R2V5 200K1%

R2V5 200K1%

1 2

L3G1

0.88uH

L3G1

0.88uH

12

R3G310

.5%

R3G310

.5%

C3V30.01uF10%402

C3V30.01uF10%402

R2

V1

8.2

KR

2V

18

.2K

A02

A15

A28

A311

A413

B03

B16

B29

B312

B414

S01

S148

C046

C144

C241

C338

C436

D045

D143

D240

D337

D435

VCC7

GND04

A516

A618

A721

A823

B517

B619

B722

B824

C533

C631

C728

C826

D532

D630

D727

D825

S247

GND110

GND215

GND320

GND534

GND639

GND429

GND742

U2G2

74CBT16209A

U2G2

74CBT16209A

R2

V9

8.2

KR

2V

98

.2K

R3G40

.5%

R3G40

.5%

C2G5.01uF20%

C2G5.01uF20%

R2

V1

38

.2K

R2

V1

38

.2K

R3F81.78kR3F81.78k

R2G3 71.5K 1%R2G3 71.5K 1%

C3F20.01uF10%.402

25V

C3F20.01uF10%.402

25V

C3V90.01uF10%402

C3V90.01uF10%402

R2V30

.

R2V30

.

C2G1100pF

5%

C2G1100pF

5%

R3G10

.5%

R3G10

.5%

C3V80.01uF10%402

C3V80.01uF10%402

R2

G1

18

.2K

R2

G1

18

.2K

C2G40.1uF

.

10%16V

C2G40.1uF

.

10%16V

www.laptop-schematics

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Page 50: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AM

PS

_A

D+

_Z

NR

AMPS_COMP

AMPS_IBATT

AMPS_PAD_MAX

AMPS_AD+_Q1AMPS_AD+_Q1+V_JACK_PWR

PWR_JACK_GND

AMPS_CONT

AMPS_CELLS

AM

PS

_S

AM

BP

AMPS_LDO

AMPS_DCIN

AMPS_PA

AMPS_SBM

AM

PS

_C

OM

P_

R

AMPS_CP_C

AMPS_CP

AMPS_ACPRES

AMPS_IPROG

AMPS_VPROG

AMPS_PAD

BC_SHDN

AMPS_CA

AMPS_REF_EN

AM

PS

_L

M3

58

A_

IN+

AMPS_PAD_MAX_LM358

AMPS_PAD_MAX

AMPS_VBS_LM358

AMPS_LM358B_OUT

AMPS_LM358B_IN-AMPS_REF_R_LM358A

MP

S_

RE

F_

LM

35

8A

_IN

-

AMPS_CONT

AMPS_VBS_LM358

AM

PS

_A

D+

_R

AMPS_VPROG

BC_SHDN

AMPS_ACPRES_R

BC_ACOK#

AMPS_ACPRES

BC_SHDN

AMPS_BATT

AMPS_IPROG

AMPS_AD+_Q

AMPS_OVP

+V_JACK_PWR

+VAC_IN_L

AGND_AMPS

AGND_AMPS

AGND_AMPSAGND_AMPS

AGND_AMPS AGND_AMPS

AGND_AMPS

AGND_AMPSAGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS AGND_AMPS AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS AGND_AMPS

AGND_AMPS AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS

AGND_AMPS

+VCHGR_OUT51

AMPS_REF

+V5A 24,29,34,38,44,46,47,51,56,57

+VCHGR_OUT51

+VBS51,56

+VBS51,56

AMPS_REF

+V3.3A

+VBS 51,56

+VBS51,56

+VCHGR_OUT51

AMPS_REF

AMPS_REF

VCHRM 40

ICHRM 40

ICHRM 40

BC_SHDN40

VCHRM40

BC_ACOK40,43

BC_ACOK_BATT56

POS_SENSE 51

+VAC_IN_L 41,44

PSYS40PBATT 40

AMPS_CONTROL44

+VBS51,56

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

System Charger AMPS

A

50 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

System Charger AMPS

A

50 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

System Charger AMPS

A

50 58Tuesday, August 28, 2007

(Vzener=16V)Battery Wakeup Threshold

Hi Z

3 Cells

Threshold Voltage

2 Cells

Number of Cells

Number of Cells

AMPS_REF

LOW

4 Cells

AMPS_CELLS

0 V

3 V

2.9 V/Cell

3.2 V/Cell

WK_TH

Vcell = Vvprog/10 + 4.1 AMPS_VPROG : To set maximum charging voltage for

Vvprog = 1 V for 4.2V per cell

each cell

AMPS_IPROG : To set maximum charging current Set to 1.25V for a Charging current of 2A

Adapter Over Voltage Protection

Route resistor senselines from the PADsof the resistor(R1H1)

R2V1639.2K1%

R2V1639.2K1%

C1V31uF10%

..

C1V31uF10%

..

1 3

CR1W4BAT54

NO_STUFF

CR1W4BAT54

NO_STUFF

R2H74.99k_1%R2H74.99k_1%

R2G230

.

R2G230

.

R2H4

232K

.

1%

R2H4

232K

.

1%

R2H91M

.5%

R2H91M

.5%

C2V50.1uF

.10%

C2V50.1uF

.10%

C1W1 2.2uF

NO_STUFF

10%

C1W1 2.2uF

NO_STUFF

10%C2V44.7uF

.20%

C2V44.7uF

.20%

C1W222uF20%

NO_STUFF

C1W222uF20%

NO_STUFF

R2V24100K

.5%

R2V24100K

.5%

C2H14.7uF

.10%

C2H14.7uF

.10%

R2H180

NO_STUFF

R2H180

NO_STUFF

C1W322uF20%

.25V

C1W322uF20%

.25V

C2V60.47uF

NO_STUFF

C2V60.47uF

NO_STUFF

R2V1523.7K

.1%

R2V1523.7K

.1%

R2G17

0

.

R2G17

0

.

R2G200

.

R2G200

.

3

1

2

Q2W1

2N7002

Q2W1

2N7002

CASE11

CASE22

CASE33

CASE44

GND15

GND26

PWR17

PWR28

CNTRL_ADFC9

J1G9

PWR_JACK

J1G9

PWR_JACK

1 2

R2V27

84.5K

1%

R2V27

84.5K

1%

1 3

CR1W3

BAT54

NO_STUFF CR1W3

BAT54

NO_STUFF

3

1

2

Q2V1BSS138

.

Q2V1BSS138

.

R1G11100

.5%

R1G11100

.5%

R2W8100K

.5%

R2W8100K

.5%

R2V260

NO_STUFF

R2V260

NO_STUFF

3

21

8

4

+

-

U2H1A

LM358

+

-

U2H1A

LM358

21

CR1W2

B320A

CR1W2

B320A

R2G22100K

.5%

R2G22100K

.5%

R1H24.7K

.5%

R1H24.7K

.5%

R2V220

.

R2V220

.

R1G101K

.5%

R1G101K

.5%

C2V11uF10%

..

C2V11uF10%

..

R2G25330K

.5%

R2G25330K

.5%

3

1

CR2W2

MMBZ5246BN

.CR2W2

MMBZ5246BN

.

R2H10100K

.5%

R2H10100K

.5%

C1W40.1uF10%

.

C1W40.1uF10%

.

C2H4 2.2uF

NO_STUFF

10%C2H4 2.2uF

NO_STUFF

10%

R2V230

NO_STUFF

R2V230

NO_STUFF

4

123

5

Q1H2

SI7483ADP

Q1H2

SI7483ADP

PAD_MAX1

VPROG2

COMP3

PA20

WUPD19

CA18

SBM17

SAP16

IBAT8

REF_EN9

WK_TH5

REF10

NC22

CONT24

PAD23

VSYS13

CP14

IPROG6

ACPRES4

LDO11

DCIN12

CELLS7

SAMBP15

BAT21

THRM25

EU2G1

JASPERSI_0X

EU2G1

JASPERSI_0X R2V2010K

.

R2V2010K

.

R1H1.007

.

1%

R1H1.007

.

1%

R2V170

NO_STUFF

R2V170

NO_STUFF C2V30.1uF

.10%

C2V30.1uF

.10%

R2V18

330K

.5%

R2V18

330K

.5%

C2G73.3uF

.10%

C2G73.3uF

.10%

R1G12 0.020R1G12 0.020

4

123

5

Q1H1

SI7483ADP

Q1H1

SI7483ADP

R2W4100K

.1%

R2W4100K

.1%

2 3

1 4

L1G1

1k@100MHz

4A, 50V, DCresist=12mohm-1 line-

L1G1

1k@100MHz

4A, 50V, DCresist=12mohm-1 line-

R2H540.2K

.1%

R2H540.2K

.1%

3

1

2Q2W52N7002Q2W52N7002

3

1

2

Q2G1BSS138

.

Q2G1BSS138

.

R2V25

100K

R2V25

100K

C2V20.1uF

.10%

C2V20.1uF

.10%

R2W2162K

.1%

R2W2162K

.1%

R2H149.9K

.1%

R2H149.9K

.1%

C2H24.7uF

.10%

C2H24.7uF

.10%

2 1

CR1W1

B320A

CR1W1

B320A

R2W10

.

R2W10

.

3

1

2Q2H12N7002Q2H12N7002

R2V1949.9K

.1%

R2V1949.9K

.1%

R1G132.2

.5%

R1G132.2

.5%

C2G81000pF10%.

C2G81000pF10%.

3

1

2

Q2W6BSS138

.

Q2W6BSS138

.

R2H8

1K

R2H8

1K

1

3

CR2V1

BAT54

CR2V1

BAT54

5

67

8

4

+

-

U2H1B

LM358

+

-

U2H1B

LM358

R2W310K

.

R2W310K

.

R2G1616.9K

.1%

R2G1616.9K

.1%

C2W1 1uF10%

..

C2W1 1uF10%

..

2468

13579111315

10121416

17181920

22 21

J2Y1

2x11-PLG

NO_STUFF

J2Y1

2x11-PLG

NO_STUFF

R2H610K

.1%

R2H610K

.1%

R1W110K

.5%

R1W110K

.5%

3

1

2

Q2G22N7002

NO_STUFF

Q2G22N7002

NO_STUFF

R2G21330K

.

5%

R2G21330K

.

5%

R2G26100K

.1%

R2G26100K

.1%

C1V21uF10%

NO_STUFF

C1V21uF10%

NO_STUFF

C2G90.47uF

10%

.

C2G90.47uF

10%

.

3

1

2

Q2H2BSS138

.

Q2H2BSS138

.

R2H11100K

.5%

R2H11100K

.5%

C1V122uF20%

NO_STUFF

C1V122uF20%

NO_STUFF

4

123 8

765

Q1H3

FDS6679AZ

Q1H3

FDS6679AZ

R2G24 330K

.

5%R2G24 330K

.

5%

R2V21100

.

5%

R2V21100

.

5%

www.laptop-schematics

.com

Page 51: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BS_CHGB

BS_CHGA

DISB#

SMB_DATA_BATT_ABC_THERMA

SMB_DATA_BATT_BBC_THERMB

SMB_CLK_BATT_A

SMB_CLK_BATT_B

PRE_L

FLIPFLOP_Q#

VBS_TRIP#VBS_TRIP

FLIPFLOP_Q

VBS_DIV

VBS_TRIP#

MAX4072_OUTMAX4072_REFIN

EC_CS_GAIN_SEL

+VAC_IN_L_APOS_SENSE_A

EC_CS_GAIN_SEL

SMB_CLK_BATT_A

LIBP_DA1

SMB_DATA_BATT_A

LIBP_CL1

LIBP_DA2

LIBP_CL2

SMB_DATA_BATT_BSMB_CLK_BATT_B

LIBP_I2C_EN_NOT

BC_THERMA

BC_THERMB

LIBP_CHG_EN_ALIBP_BAT_SEL

SMB_CLK_BATT_ASMB_DATA_BATT_A

SMB_CLK_BATT_BSMB_DATA_BATT_B

CHGB

DISB#

CHGB_XOR

GATE_CHGB

CHGA_XOR

GATE_CHGADISA#

CHGA

LIBP_CHG_EN_B

GATE_CHGA

GATE_CHGB

MAX4072_OUT_RC

CHGB

+VAC_IN_L_R

+V

AC

_IN

_L

_R

GND_SYS_CURRENT

GND_SYS_CURRENT

GND_SYS_CURRENT

GND_SYS_CURRENT

GND_SYS_CURRENT

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

+V3.3A

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

+VCHGR_OUT50

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

+VBS50,56

+VREF_ADC41

+V5A 24,29,34,38,44,46,47,50,56,57

+V3.3A

+VREF_ADC41

+V5A 24,29,34,38,44,46,47,50,56,57

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

+V3.3A

+V3.3A

SMB_BS_CLK37,40,43,52SMB_BS_DATA37,40,43,52

+V3.3A

BS_CHGB# 40,43

BS_DISB# 40,43

BS_CHGA# 40,43

BS_DISA# 40,43LIBP_CHG_EN_A40,43

BS_CLR_LTCH# 40,43

LIBP_BAT_SEL40,43

LIBP_CHG_EN_A40,43

POS_SENSE50

SMB_BS_ALRT#40,43

EC_BRK_CURRENT 40

+V3.3A

LIBP_CHG_EN_B41

LIBP_CHG_EN_B41

+V3.3A +V3.3A

CHGA_EN# 41

CHGB_EN# 41

+V3.3A+V3.3A

+V3.3A

+VBS

POS_SENSE 50

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

System Charger Battery

A

51 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

System Charger Battery

A

51 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

System Charger Battery

A

51 58Tuesday, August 28, 2007

1800

Address

11200

Total (Host + 200)

490070006800

4100

22

1A

2000

1C

2700

9100

Host Resistor

Batt A

1E

Battery Address Key

2900

20

1020

3900

1618

14

11000

Batt B

9300

820

4700

* CAD Note:

System current groud trace needs to be

20 mil or larger going from the brick to

the EC and MAX4072 current sense

amp.

*

(Place close to the sense resistor near the brick connector)

3.0V Precision ADCReference circuit

System Current Sense Amp (6A Dynamic Range)

(Place very close to the EC)

H8 ADC Reference

The precision ADC and and 3.3 ADC reference

optons are mutually exclusive. DO NOT STUFF

BOTH AT THE SAME TIME OR THE PRECISION

REFERNCE COULD BE DAMAGED.

3.3V ADC reference

0 - 3A: EN_CS_GAIN_SEL = 3.3V 0-6A

EN_CS_GAIN_SEL = 0V (DEFAULT)

CURRENT SENSE RANGE

SMBUS Address for Battery A = 1C

SMBUS Address for Battery B = 1E

SMBUS Address for LIBP = 16

MAX809 Trip Point = 2.93VVBS Trip Point = 6.0V

C2Y222UFC2Y222UF

11

22

33

44

55

66

77

J1H2

CON_1X7_156mil_HDR

J1H2

CON_1X7_156mil_HDR

C8G40.1uF20%N

O_

ST

UF

FC8G40.1uF20%N

O_

ST

UF

F

C1J60.1uF

.10%16V

C1J60.1uF

.10%16V

R1Y31K

5%

R1Y31K

5%

R2J20

.

R2J20

.

R1W6 4.7KR1W6 4.7K

C1J30.1uF

.10%16V

C1J30.1uF

.10%16V

R2J320KR2J320K

1

24

53

U1J2

74AHC1G08

.

U1J2

74AHC1G08

.

1

2

5

4

3

U1J1

74AHC1G02

U1J1

74AHC1G02

R1Y110K

.

R1Y110K

.

R8H3

10K

R8H3

10K

R2Y1

100K.

1%

R2Y1

100K.

1%C1Y50.1uF

.10%

C1Y50.1uF

.10%

1

24

53

U1Y1

74AHC1G08

.

U1Y1

74AHC1G08

.

C1W7 0.1uFNO_STUFF

C1W7 0.1uFNO_STUFF

R2H14 10KR2H14 10K

C8H10.1uF20%N

O_

ST

UF

F

C8H10.1uF20%N

O_

ST

UF

F

C2J20.1uF10%.

C2J20.1uF10%.

C1Y70.1uF

.10%16V

C1Y70.1uF

.10%16V

1

24

5

3

U2J1

74AHC1G86

U2J1

74AHC1G86

11

22

33

44

55

66

77

J1H1

CON_1X7_156mil_HDR

J1H1

CON_1X7_156mil_HDR

C1W5 0.1uFNO_STUFF

C1W5 0.1uFNO_STUFF

EXPSCL11

EXPSCL22

EXPSDA118

EXPSDA219

SCL03

SDA04

EN17

EN211

EN314

EN417

VSS10

VCC20

SCL15

SDA16

SCL28

SDA29

SCL312

SDA313

SCL415

SDA416

U2H2

EXP. 5-CH-I2C HUB

U2H2

EXP. 5-CH-I2C HUB

R8V12

10K

R8V12

10K

C2H50.1uF20%.

C2H50.1uF20%.

2 4

5

3

U1H1

INVERTER

U1H1

INVERTER

R1W5 4.7KR1W5 4.7K

R8V11 100KR8V11 100K

5

67

8

4

+

-

U2J4B

AD8552

+

-

U2J4B

AD8552

C1W80.1uF

.

C1W80.1uF

.

R1J410K

.

R1J410K

.

R2H16 10KR2H16 10K

R2Y6 1K

.

1%R2Y6 1K

.

1%

C1Y60.1uF

.10%16V

C1Y60.1uF

.10%16V

3

1

2

Q1Y1BSS138

.

Q1Y1BSS138

.

R8G8

10K

R8G8

10K

R9H10475

.1%

R9H10475

.1%

1

2

5

4

3

U1Y2

74AHC1G02

U1Y2

74AHC1G02

C1Y347uF

.

C1Y347uF

.

R1Y510K

.5%

R1Y510K

.5%

R1J1 4.7KR1J1 4.7K

3

1

CR1J1BZX84C2V4LT1CR1J1BZX84C2V4LT1

3

1

2

Q8G2

BSS138

.

Q8G2

BSS138

.

R9H90

NO_STUFF

R9H90

NO_STUFF

C1W90.1uF

.10%16V

C1W90.1uF

.10%16V

OUT6

RS+3

RS-2

VCC7

SHDN#1

GND4

GSEL8

RFIN5

U2J3

MAX4072

U2J3

MAX4072

C1W610UF25V

C1W610UF25V

R1Y413K1%

R1Y413K1%

C2W547uF

.

C2W547uF

.

R1W3 6.81K1%R1W3 6.81K1%

R2H15 10KR2H15 10K

C1H110UF25V

C1H110UF25V

1

24

5

3

U2J2

74AHC1G86

U2J2

74AHC1G86

R1Y980.6

.1%

R1Y980.6

.1%

R2Y2

10K

.

R2Y2

10K

.

R1Y612.4K

.1%

R1Y612.4K

.1%

R8G7

1M

.

R8G7

1M

.

R1J5 100KR1J5 100K

R1W10 100KR1W10 100K

R8H2

1M

.

R8H2

1M

.

R1J9

10K

NO

_S

TU

FF

R1J9

10K

NO

_S

TU

FF

R2Y3 1K

.

1%R2Y3 1K

.

1%

R1Y722

.5%

R1Y722

.5%

R2H12 10KR2H12 10K

3

1

2

Q8H1

BSS138

.

Q8H1

BSS138

.

C2J11uF

.20%

C2J11uF

.20%

C1Y40.1uF

.10%16V

C1Y40.1uF

.10%16V

R1W8 4.7KR1W8 4.7K

1

2

U9H1LM4040U9H1LM4040

R1W9 4.7KR1W9 4.7K

R2W11 10KR2W11 10K

C2W30.1uF20%.

C2W30.1uF20%.

C1J222uF

.

25V

C1J222uF

.

25V

R2J4

10K

.

R2J4

10K

.

C9H422UFC9H422UF

C1Y110UF

25VC1Y110UF

25V

R1Y8475

.1%

R1Y8475

.1%

R1W2 100KR1W2 100K

R8G9

10K

.

R8G9

10K

.

R1Y210K

.5%

R1Y210K

.5%

R1J3 100KR1J3 100K

R1W7 10K

NO_STUFF5%

R1W7 10K

NO_STUFF5%

R1J20

NO_STUFF

R1J20

NO_STUFFCLK

1

D2

Q#3

GND4

Q5

CLR#6

PRE#7

VCC8

U1J3

1G D-FLIP FLOP

U1J3

1G D-FLIP FLOP

R8G10

10K

R8G10

10K

C1Y80.1uF

.10%16V

C1Y80.1uF

.10%16V

C1Y20.1uF

.10%16V

C1Y20.1uF

.10%16V

R1W4 10K

NO_STUFF

R1W4 10K

NO_STUFF

R1W110

NO_STUFF

R1W110

NO_STUFF

3

1

2

Q2J2 BSS138

.

Q2J2 BSS138

.

3

1

2

Q1J2BSS138

.

Q1J2BSS138

.

C2Y40.1uF10%.

C2Y40.1uF10%.

3

1

2

Q2J1 BSS138

.

Q2J1 BSS138

.

C9W30.1uF

.10%

C9W30.1uF

.10%

GN

D1

RST#2

VC

C3

U1J4

MAX809

U1J4

MAX809

R2J1 100KR2J1 100Kwww.laptop-schematics

.com

Page 52: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

U1N1_TP

CPU_ICC_R

AD7417_A0

CONVST#

AD7417_A1AD7417_A2

CPU_VCC_R

6262_F

B_R

6262_V

W6262_C

OM

P_R

6262_VDIFF

PSI#_R6262_PMON

6262_F

B_C

6262_D

RO

OP

6262_VSUM_R

SPR_GT_6

VCCSENSE

VSSSENSE

OP_CPU_ICC_R

6262_VIN

6262_VO_RR

6262_DROOP

6262_DROOP_R

6262_DFB

DLL_FET

OP_CPU_ICC_R

6262_DFB_Q

CPU_ICC

6262_BOOT1 6262_BOOT1_R

6262_BOOT2 6262_BOOT2_R

6262_OCSET

PM_DPRSLPVR_IMVP6

AD7417_A0AD7417_A1AD7417_A2

CPU_VCCS2_S1

V3_3_S0

6262_FET

6262_VDD

6262_FB

6262_SOFT

CPU_ICC_R

CPU_VCC_R

6262_NTC_MID

6262_C

OM

P

6262_RBIAS6262_P

MO

NIT

OR

6262_PMON

6262_DFB_EX

6262_FB

6262_FB_RC

6262_PIN

6262_DFB_NS

6262_NTCVT_TT#_R

6262_PMON

GFX_VR_PWRIN_R

6262_VO_R

6262_COMP_RC

H_PROCHOT#

6262_FB2

SPR_GT_6

SPR_GT_5

PSI#_R

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE AGND_VCORE AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

AGND_VCORE

+V5S_IMVP6

+V3.3A

+V3.3A+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,55,56,57

+V3.3S

+VDC_PHASE53

+V527,32,42,43,48,55,56,57

+V5 27,32,42,43,48,55,56,57

+V3.3A

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,55,56,57

+V3.3S

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,55,56,57

+V5S_IMVP6

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,55,56,57

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,55,56,57+V5S_IMVP6

SMB_BS_CLK37,40,43,51

SMB_BS_DATA37,40,43,51

ISEN2 53

ISEN1 53

GFX_VR_PWRIN41,49

VSUM 53

VR_VID639

VR_VID139

VR_VID439

VR_VID039

PM_DPRSLPVR7,23,43

VR_VID239

VR_VID539

VR_VID339

H_DPRSTP#3,7,21,43

PSI#3

IMVP_VR_ON40,43

VSSSENSE4

VCCSENSE4

H_VID24H_VID14

H_VID54

H_VID04

H_VID44H_VID34

H_VID64

VCC_PRM 53

6262_UGATE1 53

6262_LGATE1 53

6262_UGATE2 53

6262_LGATE2 53

6262_PHASE2 53

6262_PHASE1 53

VR_VID1 39

VR_VID3 39VR_VID2 39

VR_VID4 39VR_VID5 39

VR_VID0 39

VR_VID6 39

CPU_ICC 41

CPU_VCC 41

DELAY_VR_PWRGOOD7,23

VR_PWRGD_CLKEN#23

H_PROCHOT#3

IMVP6_STRAP_VID0

IMVP6_STRAP_VID1IMVP6_STRAP_VID2IMVP6_STRAP_VID3IMVP6_STRAP_VID4IMVP6_STRAP_VID5IMVP6_STRAP_VID6

V3_3_S0

+V1.05S_CPU3,4,20,35,39,43,54

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

IMVP-6 Controller

A

52 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

IMVP-6 Controller

A

52 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

IMVP-6 Controller

A

52 58Tuesday, August 28, 2007

CPU VCC_Core VR and MUX Buffer

Place R2N22 nearController

Layout Note: Use27.4 Ohm routingfor Vssense andVccsense

Put the thermistor RT2C1 as physicallyclose to the inductor L2C1 as possible

Power Monitoring

VCORE Signal

To enable -5.1mOhm LL stuff: R2B16 ,Q2B2, Q2B1, R3B13, J3B1 unstuff: R2B11

Load Line: -2.1mOhmLL(default)

J3B1 (1-X): -2.1mOhmLL (DEFAULT)

GAIN ADJUSTED FOR 27

SMBUS address: 100

Input

1B1S1

1C

S21

Output

C0AS0

1

D1

B 1 011DA 1

Connect Vdd and PVCC toV5S_IMVP6 separately

Connect PGND1 directly tothe sources of the lowerFETs of phase 1, Q2C2 andQ2C4.

Connect PGND2 directlyto the sources of thelower FETs of phase 2,Q2C6 and Q2C3

Connect from ICH & daisy chainthrough CPU - Do not 'T'Place RT2C2 thermistor between the

inductor L2C1 and one of the bottomswitches Q2C2, Q2C3, Q2C4, Q2C6

J3B1 (1-2): -5.1mOhmLL

CPU Core VRController

R3B260

NO_STUFF

R3B260

NO_STUFF

R2N180

NO_STUFF

R2N180

NO_STUFF

NC11

SDA2

SCL3

VDD14

A013

A112

NC216

CONVST#15

A_IN39

A_IN410

A211

OTI4

REF_IN5

GND6

A_IN17

A_IN28

U1N1

AD7417

.

U1N1

AD7417

.

R1N3510K

.5%

R1N3510K

.5%

R1N14

8.2K

R1N14

8.2K

R1N46

10K

NO_STUFF

5%

R1N46

10K

NO_STUFF

5%

R1N34

10K

NO_STUFF

5%

R1N34

10K

NO_STUFF

5%

C2B120.1uF10%

NO

_S

TU

FF C2B12

0.1uF10%

NO

_S

TU

FFR3B13

1K

NO_STUFF1%

R3B131K

NO_STUFF1%

R3N25 392K

.

1%R3N25 392K

.

1%

C3B11

100pF

C3B11

100pF

R2B16

154K

NO

_S

TU

FF

1%

R2B16

154K

NO

_S

TU

FF

1%

R1N11

8.2K

R1N11

8.2K

R1N4510K

.5%

R1N4510K

.5%

R2B2402K1%.

R2B2402K1%.

C2P21uF

.10%

C2P21uF

.10%

R1N3010K

.5%

R1N3010K

.5%

R3B25 1.87kR3B25 1.87k

R2N13 49.9KNO_STUFF 1%

R2N13 49.9KNO_STUFF 1%

C2N9330pFC2N9330pF

C2B11 1.0uF

10% .

C2B11 1.0uF

10% .

C2B130.22uF

.10%

C2B130.22uF

.10%

R2N190

.

R2N190

.

R1B3

100

NO_STUFF1%

R1B3

100

NO_STUFF1%

R2B121.07kR2B121.07k

R1N19

8.2K

R1N19

8.2K

R2N22475

.1%

R2N22475

.1%

R1B1.002

1%R1B1.002

1%

C1N710uF

.20%

C1N710uF

.20%

R2N17 499

.

1%R2N17 499

.

1%

12

RT2C110KRT2C110K

C1B40.1uF

.10%

C1B40.1uF

.10%

C1N60.1uF

.10%

C1N60.1uF

.10%

R1N27100

NO_STUFF

1% R1N27100

NO_STUFF

1%

R3B2811K

.1%

R3B2811K

.1%

C2N7330pFC2N7330pF

R2B136.49K

.1%

R2B136.49K

.1%

R3B272.74K

.1%

R3B272.74K

.1%

R2N975K1%

R2N975K1%

C2N6 0.1uF

10%

NO_STUFFC2N6 0.1uF

10%

NO_STUFF

C2B91000pF10%.

C2B91000pF10%.

C2N40.1uF

NO_STUFF10%

C2N40.1uF

NO_STUFF10%

R2B1749.9K

.1%

R2B1749.9K

.1%

C3B1056pF

.5%

C3B1056pF

.5%

C2B8 0.015uF

10%

C2B8 0.015uF

10%

12

J3B1

NO_STUFF

J3B1

NO_STUFF

R2B7 4.02K

.1%

R2B7 4.02K

.1%

3

21

8

4

+

- U2B1A

AD8552

+

- U2B1A

AD8552

C1B3

0.1uF.10%

C1B3

0.1uF.10%

2468

1357911

13

15

10

12

14

16

J2B2

.

J2B2

.

1 2

RT2C2

470K

RT2C2

470KC1N40.1uF

.10%

C1N40.1uF

.10%

R2N3 7.5K

.

1%R2N3 7.5K

.

1%

C2B7180pF

.5%

C2B7180pF

.5%

R2N811K

.1%

R2N811K

.1%

R1N4010K

.5%

R1N4010K

.5%

C2B3

100pF

5%

C2B3

100pF

5%

R2B15 147K

.

1%R2B15 147K

.

1%C3P1 1.0uF

10% .

C3P1 1.0uF

10% .

R2N57.5K

.

1%

R2N57.5K

.

1%

C3B121uF

NO_STUFF20%

C3B121uF

NO_STUFF20%

A02

A15

A28

A311

A413

B03

B16

B29

B312

B414

S01

S148

C046

C144

C241

C338

C436

D045

D143

D240

D337

D435

VCC7

GND04

A516

A618

A721

A823

B517

B619

B722

B824

C533

C631

C728

C826

D532

D630

D727

D825

S247

GND110

GND215

GND320

GND534

GND639

GND429

GND742

U1B2

74CBT16209A

U1B2

74CBT16209A

C2P30.22uF

.10%

C2P30.22uF

.10%

C1B20.1uF

.10%

C1B20.1uF

.10%

R2N2427.4

NO

_S

TU

FF R2N24

27.4

NO

_S

TU

FF

C2B150.1uF

NO_STUFF

10%C2B15

0.1uFNO_STUFF

10%

C2N50.1uF

NO_STUFF

10%16V

C2N50.1uF

NO_STUFF

10%16V

C1N3.01uF

.20%

C1N3.01uF

.20%

R2B200

.5%

R2B200

.5%

3

1

2

Q2B2BSS138

NO

_S

TU

FF

Q2B2BSS138

NO

_S

TU

FF

C2P11uF

.10%

C2P11uF

.10%

R2B10

100K

NO_STUFF

5%

R2B10

100K

NO_STUFF

5%

R2N2327.4

NO

_S

TU

FF R2N23

27.4

NO

_S

TU

FF

R1B4

100

.

1%

R1B4

100

.

1%

C2N110.1uF10%.

C2N110.1uF10%.

R1N25

100.

1%R1N25

100.

1%

R2N1090.9K 1%

R2N1090.9K 1%

R2B1113K1%

R2B1113K1%

R1N7

8.2K

R1N7

8.2K

R2B2249.9K. 1%R2B2249.9K. 1%

R2P30

.

R2P30

.

R2C50

.

R2C50

.

R1N9

8.2K

R1N9

8.2K

C2N100.01uF10%.402

C2N100.01uF10%.402

R2B60

NO_STUFF

R2B60

NO_STUFF

R3B22

0

NO

_S

TU

FF

R3B22

0

NO

_S

TU

FF

R1N5

8.2K

R1N5

8.2K

R2B21100

.

1%R2B21

100

.

1%

C2B160.1uF

NO

_S

TU

FF

10%

C2B160.1uF

NO

_S

TU

FF

10%

C2B40.1uF10%NO_STUFF

C2B40.1uF10%NO_STUFF

R2B90

NO_STUFF

R2B90

NO_STUFF

R2N210

.

R2N210

.

R1N4210K

.5%

R1N4210K

.5%

R2B3 15K

.

1%R2B3 15K

.

1%

R2B190

NO_STUFF

R2B190

NO_STUFFR3B24 1K

.

1%R3B24 1K

.

1%

R2B5

1.07k

NO_STUFFR2B5

1.07k

NO_STUFF

C2B50.1uF

.10%16V

C2B50.1uF

.10%16V

R2B8 101%

R2B8 101%

R1N3910K

NO

_S

TU

FF

5%

R1N3910K

NO

_S

TU

FF

5%

R1N1

8.2K

R1N1

8.2K

R2N26

0

.

5%

R2N26

0

.

5%

C2B6

0.01uF10%

.

C2B6

0.01uF10%

.

C3B130.1uF

.10%

C3B130.1uF

.10%

R2N16 75K

1%

R2N16 75K

1%

R2N12 49.9KNO_STUFF

1%R2N12 49.9KNO_STUFF

1%

12

J1E1NO_STUFF

J1E1NO_STUFF

R2B18226 1%

R2B18226 1%

5

67

8

4

+

-

U2B1B

AD8552

+

-

U2B1B

AD8552

R2N20 101%

R2N20 101% R2B14

10

1%

R2B14

10

1%

C2B10

560pF

C2B10

560pF

31

2

Q2B1BSS138

NO

_S

TU

FF

Q2B1BSS138

NO

_S

TU

FF

C2N8330pFC2N8330pF

R1N3

8.2K

R1N3

8.2K

C2C40.22uF

.10%

C2C40.22uF

.10%

R2N2510K

NO_STUFF

5%

R2N2510K

NO_STUFF

5%

R2N110

.5%

R2N110

.5%

R2B2368

.

5%

R2B2368

.

5%

R1B2

10K

.

1%

R1B2

10K

.

1%

R2N7402K1%.

R2N7402K1%.

R1N3110K

NO_STUFF5%

R1N3110K

NO_STUFF5%

www.laptop-schematics

.com

Page 53: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VBAT 17,49,55,56,57

+VDC_PHASE52

+VDC_PHASE52

+VDC_PHASE52

+VCC_CORE4,54,55

6262_UGATE1

6262_LGATE1

6262_PHASE152

6262_UGATE2

6262_PHASE252

6262_LGATE2

VCC_PRM 52

ISEN1

VSUM 52

ISEN1

VSUM52ISEN2

VCC_PRM52

ISEN2

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

1.0

IMVP-6 Drivers and FET

A

53 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

1.0

IMVP-6 Drivers and FET

A

53 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

1.0

IMVP-6 Drivers and FET

A

53 58Tuesday, August 28, 2007

Connect at the

same point.

Connect at the

same point.

Phase1

Phase2

Place near Controller

Place near Controller

LAYOUT NOTES:

Place R2P2 & R2C6 right next to

each other. Route a single trace

from the input pad of the inductor

and T at the resistors. --> Do not

use plane flood. This applies for

R2P1 & R2C4

as well.

Place CR2P2 near Q2C2, Q2C4 and

Q2C1 . Route

sharing the ground and switch

nodes with low side FETs. This

applies for CR2P1 and Q2C3, Q2C6

and Q3C1as well.

Place the 0402 caps near the drain

of the high side FETs for each

phase.

Use a large pad forthis voltage.

Use a large pad forthis voltage.

The jumper and senseresistor for this side ofthe inductor must be in thesame layout fashion as theones for the other side ofthe inductor.

The jumper and senseresistor for this side ofthe inductor must be in thesame layout fashion as theones for the other side ofthe inductor.

21

CR2P1

B320A

CR2P1

B320A4

25

31

G

S

DQ2C3

HAT2164H

G

S

DQ2C3

HAT2164H

R2D20.002NO_STUFFR2D20.002NO_STUFF

C2C810UFC2C810UF

R2D10.002NO_STUFFR2D10.002NO_STUFF

R2P13.32k1%

R2P13.32k1%

C3C80.01uF10%.402

25V

C3C80.01uF10%.402

25V

C3C11

10UF

C3C11

10UF

R2C11.00

.1%

R2C11.00

.1%

C2B14 0.1uF

10%

C2B14 0.1uF

10%

21

CR2P2

B320A

CR2P2

B320A

C3P2

10UF

C3P2

10UFC3C1010UFC3C1010UF

C2C710UFC2C710UF

4

25

31

G

S

D

Q2C2HAT2164H

G

S

D

Q2C2HAT2164H

C2C90.01uF10%.402

25V

C2C90.01uF10%.402

25V

C2C100.01uF10%.402

25V

C2C100.01uF10%.402

25V

R2P23.32k1%

R2P23.32k1%

C2C210UFC2C210UF

C2C1247uF

NO_STUFF

20%16V

C2C1247uF

NO_STUFF

20%16V

12

J3C3

.

J3C3

.

R1P5.002

1%R1P5.002

1%

4

25

31

G

S

D

Q2C4HAT2164H

G

S

D

Q2C4HAT2164H

C3C210UFC3C210UF

C2C3 0.1uF

10%

C2C3 0.1uF

10%

4

25

31

G

S

D

Q2C1HAT2168H

G

S

D

Q2C1HAT2168H

C2C1 0.1uF10%

C2C1 0.1uF10%

C3C6

10UF

C3C6

10UF

R2C31.00

.1%

R2C31.00

.1%

R2C711K

NO_STUFF1%

R2C711K

NO_STUFF1%

R2C2 11K

NO_STUFF

1%R2C2 11K

NO_STUFF

1%

C2C50.01uF10%.402

25V

C2C50.01uF10%.402

25V

R2C411K

.1%

R2C411K

.1%

C2C130.01uF10%.402

25V

C2C130.01uF10%.402

25V

4

25

31

G

S

D

Q3C1HAT2168H

G

S

D

Q3C1HAT2168H

4

25

31

G

S

D

Q2C6

HAT2164H

G

S

D

Q2C6

HAT2164H

C2P410UFC2P410UF

C3P347uF

NO_STUFF

20%16V

C3P347uF

NO_STUFF

20%16V

1 2

J2C1

.

J2C1

.

4

25

31

G

S

D

Q3C2HAT2168HNO_STUFF

G

S

D

Q3C2HAT2168HNO_STUFF

4

25

31

G

S

D

Q2C5HAT2168H

NO_STUFF

G

S

D

Q2C5HAT2168H

NO_STUFF

C3C147uF

NO_STUFF

20%16V

C3C147uF

NO_STUFF

20%16V

C3C30.01uF10%.402

25V

C3C30.01uF10%.402

25V

C2C1110UFC2C1110UF

R2C611K

.1%

R2C611K

.1%

C3C120.01uF10%.402

25V

C3C120.01uF10%.402

25V

C3C90.01uF10%.402

25V

C3C90.01uF10%.402

25V

C2P547uF

NO_STUFF

20%16V

C2P547uF

NO_STUFF

20%16V

44

33

11

22

*

*L2C1

Coupled_Inductor 310nH

*

*L2C1

Coupled_Inductor 310nH

C2C6 0.1uF10%

C2C6 0.1uF10%

www.laptop-schematics

.com

Page 54: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V1.05S_CPU3,4,20,35,39,43,52

+VCC_CORE4,53,55

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

CPU Decoupling

A

54 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

CPU Decoupling

A

54 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

CPU Decoupling

A

54 58Tuesday, August 28, 2007

Vcc Core Decoupling

Vccp Core Decoupling

Place these inside socketcavity on L8 ( North sideSecondary)

Place these outside socketcavity on L8 ( North side Secondary)

Place these inside socketcavity on L8 ( North sideSecondary)

Place these inside socketcavity on L8 ( North sidePrimary)

Place these inside socketcavity on L8 ( South sidePrimary)

Place these outside socketcavity on L8 ( South side Secondary)

Place these inside socketcavity on L8 ( South sideSecondary)

C2E822uF

.20%

C2E822uF

.20%

C2E122uF

.20%

C2E122uF

.20%

C2T1522uF

.20%

C2T1522uF

.20%

C2E1122uF

.20%

C2E1122uF

.20%

C2T2022uF

.20%

C2T2022uF

.20%

C2E522uF

.20%

C2E522uF

.20%

C3T1330uF

NO_STUFF

10%

C3T1330uF

NO_STUFF

10%

C2U10.1uF

.10%

C2U10.1uF

.10%

C2T322uF

.20%

C2T322uF

.20%

C2T2422uF

.20%

C2T2422uF

.20%

C2T1622uF

.20%

C2T1622uF

.20%

C3T322uF20%

C3T322uF20%

C2T422uF

.20%

C2T422uF

.20%

C3T6330uF10%

C3T6330uF10%

C3T522uF

.20%

C3T522uF

.20%

C2T22330uF10%

C2T22330uF10%

C2T1922uF

.20%

C2T1922uF

.20%

C2T2322uF

.20%

C2T2322uF

.20%

C2T10.1uF

.10%

C2T10.1uF

.10%

C2T1322uF

.20%

C2T1322uF

.20%

C2T1022uF20%

C2T1022uF20%

C2T822uF

.20%

C2T822uF

.20%

C2E1222uF

.20%

C2E1222uF

.20%

C2E322uF

.20%

C2E322uF

.20%

C2E422uF

.20%

C2E422uF

.20%

C2E622uF

.20%

C2E622uF

.20%

C2T622uF

.20%

C2T622uF

.20%

C2T1722uF20%

C2T1722uF20%

C2E722uF

.20%

C2E722uF

.20%

C2T1422uF

.20%

C2T1422uF

.20%

C2T20.1uF

.10%

C2T20.1uF

.10%

C3T70.1uF

.10%

C3T70.1uF

.10%

C2T1122uF

.20%

C2T1122uF

.20%

C2T2122uF

.20%

C2T2122uF

.20%

C2T260.1uF

.10%

C2T260.1uF

.10%

C2E222uF

.20%

C2E222uF

.20%

C2E1022uF

.20%

C2E1022uF

.20%

C2T250.1uF

.10%

C2T250.1uF

.10%

C2E922uF

.20%

C2E922uF

.20%

C2T1822uF

.20%

C2T1822uF

.20%

C2T1222uF

.20%

C2T1222uF

.20%

C2T5330uF10%

.

C2T5330uF10%

.

C3T422uF20%

C3T422uF20%

C2T722uF

.20%

C2T722uF

.20%

C3T222uF

.20%

C3T222uF

.20%

C2T922uF

.20%

C2T922uF

.20%

www.laptop-schematics

.com

Page 55: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PM_SLP_S3_BUF_R

PP_VIMVPDIS

PP_BATS4DIS

PP_V3DIS

PP_V1.8DIS

PP_S4GT

VBATA_DISCHARGE

PP_12DIS

PP_V5DIS

PM_SLP_M

PP_V3STVDIS

PM_SLP_S3

PP_V3MDIS

PP_V105M_DIS

PP_V1.5SDIS

PP_V12SDIS

PP_V5SDIS

PP_V3SDIS

DDR_DIS

PP_V0.9DIS

PM_SLP_S3_BUF

PP_V33MCKDIS

PP_V33M_DIS

+VBAT17,49,53,56,57

+V1.89,10,13,14,46,48,57+V1.5S4,10,11,24,28,47,57

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,56,57

+V1.05S4,9,10,24,47

+V3.3S_TVDAC10,11,48

+V0.915,46+VBATS16,19,27,30,31,57

+VCC_CORE4,53,54

+V3.319,27,32,39,41,42,43,57+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,56,57

+VBAT_S419,57+V5 27,32,42,43,48,52,56,57

+V12S25,26,30,31,32,43,57

+V3.3A

+V3.3M_WOL22,24,33,34,44,48,57

+V1.05M9,10,15,35,47 +V3.3M13,14,15,23,35,57

PM_S4_STATE#23,32,40,43,44,57

PM_SLP_S3#11,23,40,43,44,46,47,49,57

PM_SLP_S3#11,23,40,43,44,46,47,49,57

PM_SLP_M#23,40,43,44,47,57

PM_SLP_S4#23,46

LAN_WOL_EN 23,40,43,57

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DISCHARGE CIRCUITS

A

55 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DISCHARGE CIRCUITS

A

55 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

3556591.0

DISCHARGE CIRCUITS

A

55 58Tuesday, August 28, 2007

SLP_S3# DISCHARGE CKTDESIGNED FOR ~100msDISCHARGE ON ALL S3RAILS.

SLP_S4# DISCHARGE CKTDESIGNED FOR ~100msDISCHARGE ON ALL S4RAILS.

ATX Mounting Holes

3

1

2

Q4G5BSS138

.

Q4G5BSS138

.

R5B368

.

5%

R5B368

.

5%

45

23

6789

MT5J1

MT156NO_STUFF

MT5J1

MT156NO_STUFF

45

23

6789

MT1J1

MT156NO_STUFF

MT1J1

MT156NO_STUFF

3

1

2

Q4H3BSS138

.

Q4H3BSS138

.

3

1

2

Q4B2BSS138

.

Q4B2BSS138

.

R4R847R4R847

R4B9

220

R4B9

220

3

1

2

Q5H1BSS138

.

Q5H1BSS138

.

R5V1197.6

.

R5V1197.6

.

45

23

6789

MT1F1

MT156NO_STUFF

MT1F1

MT156NO_STUFF

3

1

2

Q4W1BSS138

.

Q4W1BSS138

.

R4G5100K5%

R4G5100K5%

45

23

6789

MT9A1

MT156NO_STUFF

MT9A1

MT156NO_STUFF

R4W1497.6

.

R4W1497.6

.

12

R5H5180R5H5180

R4V91MR4V91M

R4D3100KR4D3100K

R3R51MR3R51M

R4V647R4V647

3

1

2

Q3R2BSS138

.

Q3R2BSS138

.

R5V101MR5V101M

R4V14100KR4V14100K

3

1

2

Q4G2

BSS138

.

Q4G2

BSS138

.

R5W197.6

.

R5W197.6

.

45

23

6789

MT9F1

MT156NO_STUFF

MT9F1

MT156NO_STUFF

45

23

6789

MT1B1

MT156NO_STUFF

MT1B1

MT156NO_STUFF

3

1

2

Q4D1BSS138

.

Q4D1BSS138

.

C3P522UFC3P522UF

3

1

2

Q3R1BSS138

.

Q3R1BSS138

.

3

1

2

Q5N1BSS138

.

Q5N1BSS138

.

3

1

2

Q4G3BSS138

.

Q4G3BSS138

.

1

3

CR3R1BAT54CR3R1BAT54

12

R7B1180R7B1180

R3D3470

.5%

R3D3470

.5%

3

1

2

Q5V2BSS138

.

Q5V2BSS138

.

12

R6N5180R6N5180

R4V1110K

.

R4V1110K

.

3

1

2

Q5G3BSS138

.

Q5G3BSS138

.

3

1

2

Q4G4BSS138

.

Q4G4BSS138

.

R4W1597.6

.

R4W1597.6

.

45

23

6789

MT5A1

MT156NO_STUFF

MT5A1

MT156NO_STUFF

3

1

2

Q7B1BSS138

.

Q7B1BSS138

.

3

1

2

Q3R4BSS138

.

Q3R4BSS138

.

3

1

2

Q4V1BSS138

.

Q4V1BSS138

.

3

1

2

Q6N2BSS138

.

Q6N2BSS138

.

R3R124.87K

.1%

R3R124.87K

.1%

R4V1297.6

.

R4V1297.6

.

3

1

2

Q4H1BSS138

.

Q4H1BSS138

.

3

1

2

Q4G6BSS138

.

Q4G6BSS138

.

R4V13470

.5%

R4V13470

.5%

3

1

2

Q3R5BSS138

.

Q3R5BSS138

.

R3R1100KR3R1100K

R4H1470

.5%

R4H1470

.5%

3

1

2

Q3R3BSS138

.

Q3R3BSS138

.

45

23

6789

MT9J1

MT156NO_STUFF

MT9J1

MT156NO_STUFF

R3R6100KR3R6100K

www.laptop-schematics

.com

Page 56: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FRONT1

PWR_CONN_D

PS_ON_SW#

PS_LATCH#

RST_PUSH#_D

PS_LATCH#

PS_ON#

PWRONLATCHG

PS_ON_SW#

MASTER_RESET#

PS_ACENABLE

V12ATXSW

ATXPWR

VBSGT

PS_LATCH#

5S

B_

AT

XA

_R

+V3.3_DL_Q

+V5_DL_Q

PS

_A

TX

SE

NS

5V_DL

+V3.3_DL_QR 3.3V_DL_R

5V

_D

L_

R

ADAPT_PRES_R

SHUTDWN#

SHUTDWN#

+V

BA

TA

_P

S_

LA

TC

H

PS

_P

WR

BT

N

NETDETECT_12V#NETDETECT_12V

FRONT2

ME

_G

3_

TO

_M

1

SMC_SHUTDOWN_R

+VBATA_LATCH_SHUTDOWN

+V5 27,32,42,43,48,52,55,57

+VBATA26,45,46,47,57 +VBAT17,49,53,55,57

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,57

+V3.3S+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,57

+V5S

+V5SB_ATXA

+V5A_MBL45

+V5A24,29,34,38,44,46,47,50,51,57

+VBATA26,45,46,47,57

+V3.3A_MBL

+VBS50,51

+V3.3A

+V5SB_ATXA

+V3.3A

+VBATA26,45,46,47,57

+V3.3_ATX

+V3.3_ATX +V3.3_ATX

-V12A57-V12_ATX

+V5_ATX

+V5_ATX

+V5_ATX

+V12_ATX

+V5SB_ATXA+V5SB_ATX

+V5SB_ATX

+V5SB_ATX

+VBATA26,45,46,47,57

+VBATA26,45,46,47,57

+V3.3A

+V3.3A

SATA_LED#21

XDP_DBRESET#_R

BC_ACOK_BATT50

SMC_SHUTDOWN40,43

AC_PRESENT 23,40,43

ND_SW#41

PM_SYSRST# 23

ATX_DETECT# 40,43

ATX_PWR_CNTRL 57

ATX_PWROK 41

VR_ALW_ENABLE 28,45

PS_ON_SW# 44

RSTBTNDB 44

SMC_ONOFF# 40,43

NETDETECT# 40,43

ME_G3_TO_M1#40

+V3.3A

PM_RSMRST#23,40,43

+V5A

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Start Up Sequence

A

56 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Start Up Sequence

A

56 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Start Up Sequence

A

56 58Tuesday, August 28, 2007

MOBILE OPTION

POWER ONand S5ENTER/EXITButton

RESETBUTTON

ATX ALWAYS ONDT OPTION

5V MIN CURRENTDUMMY LOAD: Gives0.5A min currentload

3V MIN CURRENTDUMMY LOAD:Gives 0.5A mincurrent load

ATX POWER

Front Panel Header

Shunt pins 13 & 15for SV forcing ATXon and VBAT on forpower cycling

Stuff R3W17 onlyfor G3 Mobilepower cycling

Active High: When AC brickpresent charger starts andasserts this signal, whichstarts the on board alwaysrails by forcing theassertion on VR_ALW_ENABLEassuming ATX_PWR_CNTRL isasserted. Ignored by H8 inATX mode.

BC_ACOK_BATT

PS_ON#

PS_ON# internally pulled upto 5V standby in all ATXsupply per ATX 12V spec.

Active High: Goes highon pwr button pressturing on the on boardalways rails in batterymode. ForcesVR_ALW_ENABLE high whenATX_PWR_CNTRL is high(in mobile mode). Alsoallows H8 to shut theboard down viaSMC_SHUTDOWN when R3W17is stuffed.

SHUTDWN#

Active High: SHUTDWN#||BC_ACOK_BATT)&ATX_PWR_CNTRL

VR_ALW_ENABLE

Enables on board Always VRs (5MBL,3.3MBL, and 1.5A) when running offAC brick or battery. Low in ATXmode.

Battery Mode: ATX_PWR_CNTRL = VBATABrick Mode: ATX_PWR_CNTRL = VBATA ATX Mode: ATX_PWR_CNTRL=0V

ATX_PWR_CNTRL

3.3V=Mobile Mode (BATT or Brick)0V=ATX mode powerd by ATX supply

Acitve Low: Indicates system ispowered by ATX supply to H8: Note H8 looks at this signalbefore BC_ACOK#.

ATX_DETECT#

Power

Button Latch

Force Shutdown

Signals EC of a netdetect button event.

SMC_NET_DETECT: NetDetect trigger signalto ICH9M. Also clearsnetdetect buttonlatch.

Net Detect

3.3V Net Detect Level Shifter

Button Latch

Net DetectButton

Jumper J4H1Open (Default) No After_G3 support 1-2 After G3 support with ATX supply2-3 After G3 Support with AC brick

3

1

2

Q9H5BSS138

.

Q9H5BSS138

.

1

2

7

8

Q3H6A

SI4965DY

Q3H6A

SI4965DY

R8E4100KR8E4100K

4

123

5

Q1J1SI7483ADP

Q1J1SI7483ADP

C1J50.1uF10%.

C1J50.1uF10%.

R9H2210K

.

5%

R9H2210K

.

5%

R5H610K

.

5%

R5H610K

.

5%

+ C2W215uF

.20%

+ C2W215uF

.20%

R2W10100KR2W10100K

R2W70

.

R2W70

.

3

1

2

Q4J1BSS138

.

Q4J1BSS138

.

R4W203.0

.

5%

R4W203.0

.

5%

R8E2100KR8E2100K

3

1

2

Q2W3BSS138

.

Q2W3BSS138

.

R7H16330

.

R7H16330

.

R8T3100KR8T3100K

13

CR2W3

BAT54

CR2W3

BAT54

R5H73.0

.

5%

R5H73.0

.

5%

R5J1 3.0

.

5%R5J1 3.0

.

5%

R4W191K

5%

NO_STUFF

R4W191K

5%

NO_STUFF

1 23 4

SW1C1Push_ButtonSW1C1Push_Button

3

1

2

Q3G1BSS138

.

Q3G1BSS138

.

R3W1343KNO_STUFF

R3W1343KNO_STUFF

R5W203.0

.

5%

R5W203.0

.

5%

32

1

CON3_HDR

J4H1

CON3_HDR

J4H1

13

CR8E1

BAT54

CR8E1

BAT54

3

1

2

Q2W7BSS138

.

Q2W7BSS138

.

C4V30.1uF10%.

C4V30.1uF10%.

13

2

CR2W4

BAR43S

CR2W4

BAR43S

C8E21000PF

.10%

C8E21000PF

.10%

3

1

2

Q4G1BSS138

.

Q4G1BSS138

.

12

J2G1J2G1

12

34

SW1C2

Push_Button

SW1C2

Push_Button

R3W170

NO_STUFF

R3W170

NO_STUFF

R2G27

3.3K

.

5%

R2G27

3.3K

.

5%

R5H910K

.

5%

R5H910K

.

5%

C7H6470pF

.5%

C7H6470pF

.5%

3

46521

Q5Y1

SI3442BDV

Q5Y1

SI3442BDV

1 2

R4W21

0NO_STUFF

R4W21

0NO_STUFF

R5W13 100KR5W13 100K

4

123 8

765

Q2W8

FDS6679AZ

Q2W8

FDS6679AZ

1

3

CR6W1BAT54CR6W1BAT54

R4H5390KR4H5390K

21

3

CR1

BAT54A

CR1

BAT54A

C7H8470pF

.5%

C7H8470pF

.5%

3

1

2

Q4H10BSS138

.

Q4H10BSS138

.

R9H1910K

.

5%

R9H1910K

.

5%

R1J6390KR1J6390K

C1J4

0.33uF

. 80%

C1J4

0.33uF

. 80%

C5W50.1uF

.10%

C5W50.1uF

.10%

12

+ C5H2220uF10%.

+ C5H2220uF10%.

R4Y20.002

.

1%

R4Y20.002

.

1%13579

111315

24681012

16

J6H5

HDR_2x8

J6H5

HDR_2x8

R1J7100KR1J7100K

R9H2110K

.

5%

R9H2110K

.

5%

VCC4

OUT3

GND1

IN2

U5H2

MAX6816

U5H2

MAX6816

4

5678

3

12

Q4G7

IRF7822

.

Q4G7

IRF7822

.

+ C4H2220uF10%.

+ C4H2220uF10%.

+ C1J115uF

.20%

+ C1J115uF

.20%

12

J3J2J3J2

3

1

2

Q8E4BSS138

.

Q8E4BSS138

.

C6H4470pF

.5%

C6H4470pF

.5%

R3W21 100KR3W21 100K

C3W14700PF

C3W14700PF

3

46521

Q4H9

SI3442BDV

Q4H9

SI3442BDV

3

1

2

Q3W1BSS138

.

Q3W1BSS138

.

C7H4470pF

.5%

C7H4470pF

.5%

13

CR3V1

BAT54

CR3V1

BAT54

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

11

22

33

44

55

66

77

88

99

1010

J4J1

CON20_PWR

J4J1

CON20_PWR

3

1

2

Q3W2BSS138

.

Q3W2BSS138

. 3

1

2

Q8E1BSS138.

Q8E1BSS138.

R2H13100KR2H13100K

1 23 4

SW8E1Push_ButtonSW8E1Push_Button

R3W5100KR3W5100K

R3V4

20K

R3V4

20K

12

+ C4H5220uF10%.

+ C4H5220uF10%.

3

1

2

Q8E2BSS138

.

Q8E2BSS138

.

R4H4 3.0

.

5%R4H4 3.0

.

5%

R2H171MR2H171M

1

3

2

CR2W1BAT54CCR2W1BAT54C

R5W1210K

.

R5W1210K

.

3

4

5

6

Q3H6BSI4965DYQ3H6BSI4965DY

1 2

R4J1

0NO_STUFF

R4J1

0NO_STUFF

R5H8 0.002

.

1%R5H8 0.002

.

1%

3

1

2

Q2W2BSS138

.

Q2W2BSS138

.

R4Y1 0.002

.

1%R4Y1 0.002

.

1%

R4V70

.

R4V70

.

R2W5100KR2W5100K

C5W60.01uF.

10%

C5W60.01uF.

10%

2

1

3CR4W2BAT54ACR4W2BAT54A

R2W6100KR2W6100K

R3V310K

.

5%

R3V310K

.

5%

R8E143KNO_STUFF

R8E143KNO_STUFF

3

1

2

Q2W4BSS138

.

Q2W4BSS138

.

R2W9100KNO_STUFF

R2W9100KNO_STUFF

1

24

53

U5H1

74AHC1G08

.

U5H1

74AHC1G08

.

R3W120KR3W120K

R4H3220K

.

5%

R4H3220K

.

5%

3

1

2

Q8E3BSS138

.

Q8E3BSS138

.

R4V81K5%

R4V81K5%

+ C2W415uF

.20%

+ C2W415uF

.20%

C7H7470pF

.5%

C7H7470pF

.5%

+ C4H4220uF10%.

+ C4H4220uF10%.

+ C5B215uF

.20%

+ C5B215uF

.20%

13

CR7H2

BAT54

CR7H2

BAT54

R7H17330

.

R7H17330

.

3

1

2

Q1V4

BSS138

.

Q1V4

BSS138

.

www.laptop-schematics

.com

Page 57: Laptop Schematic Diagram (Intel Montevina Mobile Platform)

www.laptop-schematics

.com

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PP_S0LED

PP_S3CLEDSW

VBATA_SLEEP

V3M_G_SWITCH

SLPS4#_CONTROL

PS_12SSW

PS_12SG

PS_VBATSW

PP_S5LEDSW

PM_S3#_AND

PS_S3CNTRL

PS_S3CNTRL_R

PS_VBAT_S4_D

SYS_STATUS_PU

PS_-12OPTSW

PS_S4CNTRL_R

PP_S4LED

PS

_V

BA

T_

S4

_G

PS

_V

BA

TS

G

ATX_PWR_CTRL_1SYS_STATUS_CR

PS_S3CNTRL

WOL_GPIO56

V3.3M_SWITCH

V3M_G_SWITCH_OR

V3.3M_INV

PP_M0_LED

PP_S0_LEDSW

PP_S4_LEDSW2

PP_S3CLEDSW_D

PP_S5LED

PP_S3CLEDSW_DPP_S0_LEDSWPP_S4_LEDSW2

PP_S5LED

PP_S4LEDSW1

PP_S4LEDSW1

PP_S3CLED

PP_S3CLED

PS_S4CNTRL

PS

_-1

2S

SW

+V3.3M_WOL22,24,33,34,44,48,55

+V3.3A

+VBATA26,45,46,47,56

+V3.3S

+V3.319,27,32,39,41,42,43,55

+V3.3A

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56

+V3.319,27,32,39,41,42,43,55

+V12S25,26,30,31,32,43,55

-V12S32

+VBAT_S419,55

+V3.3A

+VBATS 16,19,27,30,31,55

+VBATA26,45,46,47,56

+VBAT17,49,53,55,56

+V3.3S

+V5A24,29,34,38,44,46,47,50,51,56

+V5 27,32,42,43,48,52,55,56

+V5S

+V3.3A

+V3.3A

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56

+VBAT17,49,53,55,56

+V3.3S

-V12A56

+V3.3M13,14,15,23,35,55

+VBATA26,45,46,47,56

+V3.3A+V3.3M13,14,15,23,35,55

+V3.3A

PM_SLP_S3#11,23,40,43,44,46,47,49,55

PM_SLP_S3#11,23,40,43,44,46,47,49,55

PM_SLP_S3#11,23,40,43,44,46,47,49,55

ATX_PWR_CNTRL56

PM_SLP_S5#23

PM_S4_STATE#23,32,40,43,44,55

PM_S4_STATE#23,32,40,43,44,55

PM_SLP_S3#11,23,40,43,44,46,47,49,55

PM_SLP_S3#11,23,40,43,44,46,47,49,55

PM_SLP_S5#23

PM_S4_STATE#23,32,40,43,44,55

PM_SLP_M#23,40,43,44,47,55

PLT_RST#7,19,22,25,26,38,41

LAN_WOL_EN 23,40,43,55

+V1.89,10,13,14,46,48,55+V1.5S4,10,11,24,28,47,55

+V3.3M13,14,15,23,35,55

+VBATA26,45,46,47,56

+V5A24,29,34,38,44,46,47,50,51,56

+VBATA26,45,46,47,56

ICH_GPIO12 23

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Sleep control

A

57 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Sleep control

A

57 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

Sleep control

A

57 58Tuesday, August 28, 2007

System Power Good

75 ohms chosen for ~16mA ofLED current

M0/M1

S3

COLD

SO

S5

S4

Added for WOL inS3/Moff. Enabled by CLGPIO3=LAN_WOL_EN.

Added to isolate CK505 from 3.3Mwhen WOL/Moff is enabled.

SLP_M# LAN_WOL_EN 3.3M_WOL 3.3M SYSTEM STATE0 00

011 1

10V3.3V 0V

0V

3.3V 3.3V3.3V 3.3V

Moff / No WOLLegacy WOL / Moff

M1M1

Note: only stuff Q4U1 and C4V1 for DDR3 Board

ICH_GPIO1211110 0 1 0V 0V Moff / No WOL

C3W80.1uF

.10%

C3W80.1uF

.10%

1

32

SI2307DSQ5W4

.

SI2307DSQ5W4

.

R5W1175R5W1175

12

CR5H6GREEN

.

CR5H6GREEN

.

3

1

2

Q6B5BSS138

.

Q6B5BSS138

.

3

1

2

Q7H1BSS138

.

Q7H1BSS138

.

R5V7 100KR5V7 100K

C4H30.1uF10%.

C4H30.1uF10%.

4

32

1

U9B1

TLP280

U9B1

TLP280

R7N1100KR7N1100K

1

32

SI2307DSQ5W3

.

SI2307DSQ5W3

.

12

CR5H5GREEN

.

CR5H5GREEN

.

R5W17100K

.1%

R5W17100K

.1%

R4W675R4W675

C5V8

0.01UF.10%

C5V8

0.01UF.10%

4

5678

3

12

Q4H2IRF7822

.

Q4H2IRF7822

.

4

123 8

765

Q5H3SI4425DYQ5H3SI4425DY

C9A60.1uF10%.

C9A60.1uF10%.

4

5678

3

12

Q4W2IRF7822

.

Q4W2IRF7822

.

1

2

7

8

Q3H3A

SI4965DY

Q3H3A

SI4965DY

4

5678

3

12

Q5W1IRF7822

.

Q5W1IRF7822

.

R6N1100KR6N1100K

R4W23100K

.

5%

R4W23100K

.

5%

C6N10.1uF10%.

C6N10.1uF10%.

3

1

2

Q6M1BSS138

.

Q6M1BSS138

.

R4W17

100K

R4W17

100K

12

CR5H3GREEN

.

CR5H3GREEN

.

3

1

2

Q7C1BSS138

.

Q7C1BSS138

.

3

1

2

Q4W4BSS138

.

Q4W4BSS138

.

C4Y10.33uF

.80%

C4Y10.33uF

.80%

4

123 8

765

Q6B2SI4425DYQ6B2SI4425DY

3

1

2

Q4W3BSS138

.

Q4W3BSS138

.

R5V6100KR5V6100K

3

1

2

Q4W5BSS138

.

Q4W5BSS138

.

R5W1075R5W1075

12

CR7H3GREEN

.

CR7H3GREEN

.

C6N30.33uF

.80%

C6N30.33uF

.80%

1

32

SI2307DSQ5W5

.

SI2307DSQ5W5

.

3

1

2

Q7B2BSS138

.

Q7B2BSS138

.

4

5678

3

12

Q4U1IRF7822

NO_STUFF

Q4U1IRF7822

NO_STUFF

R6N2100KR6N2100K

C5W80.1uF10%.

C5W80.1uF10%.

1

24

53

U5H3

74AHC1G08

.

U5H3

74AHC1G08

.

R9M3330

.

R9M3330

.

3

1

2

Q4H6BSS138

.

Q4H6BSS138

.

R6N3100KR6N3100K

3

1

2

Q4H8BSS138

.

Q4H8BSS138

.

R4W16100KR4W16100K

C6N70.33uF

.80%

C6N70.33uF

.80%

R6N4100KR6N4100K

4

1 2 38765

Q9A3

SI4420DY

Q9A3

SI4420DY

C5W70.1uF

.10%

C5W70.1uF

.10%

3

1

2

Q6N3BSS138

.

Q6N3BSS138

.

12

CR5H4GREEN

.

CR5H4GREEN

.

C4V10.33uF

NO_STUFF80%

C4V10.33uF

NO_STUFF80%

3

1

2

Q4H5BSS138

.

Q4H5BSS138

.

R6M13100KR6M13100K

C6B20.33uF

.80%

C6B20.33uF

.80%

R5W775R5W775

4

123 8

765

Q6N1SI4425DY

Q6N1SI4425DY

C3270.1uF

.10%

C3270.1uF

.10%

C9A70.1uF10%.

C9A70.1uF10%.

3

1

2

Q4H4BSS138

.

Q4H4BSS138

.

R4W18100KR4W18100K

3

1

2

Q4H7BSS138

.

Q4H7BSS138

.

3

1

2

Q5H2BSS138

.

Q5H2BSS138

.

3

1

2

Q5W2BSS138

.

Q5W2BSS138

.

R9A610K

.

5%

R9A610K

.

5%

R5W1610K

.

5%

R5W1610K

.

5%

R3W16100KR3W16100K

R4W22100KR4W22100K

3

1

2

Q6B1BSS138

.

Q6B1BSS138

.

R5W1475R5W1475

R4H210K

NO_STUFF

5%

R4H210K

NO_STUFF

5%

C6N20.01UF.

10%

C6N20.01UF.

10%

R8W975R8W975

4

5678

3

12

Q6B4IRF7822

.

Q6B4IRF7822

.

12

CR5H7GREEN

.

CR5H7GREEN

.

1 23 45 67 8

J8G2

8Pin HDR

J8G2

8Pin HDR

3

1

2

Q5W6BSS138

.

Q5W6BSS138

.

3

4

5

6

Q3H3B

SI4965DY

Q3H3B

SI4965DY

C4W20.01UF.

10%

C4W20.01UF.

10%

R4W24

100K

.

5%

R4W24

100K

.

5%

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www.laptop-schematics

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5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

POWER SEQUENCING TIMING BLOCK DIAGRAM

A

58 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

POWER SEQUENCING TIMING BLOCK DIAGRAM

A

58 58Tuesday, August 28, 2007

Title

Size Document Number Rev

Date: Sheet of

Pillar Rock Intel Confidential

355659 1.0

POWER SEQUENCING TIMING BLOCK DIAGRAM

A

58 58Tuesday, August 28, 2007

PM

_S

LP

_S

3#

PM

_S

LP

_M

#

PM_1.5_1.05S_PGOOD

7

+VBAT

10

SHT 47

H8 SMC

10

+V3.3M_WOL

VR_ALW_ENABLE

1AC

VR

MP

WR

GD

H_CPURST#

+VCC_GMCH_CORE,+VCCP

H_PWRGD

1

SWITCHSHT 57

+V3.3M

4

IMVP6+ CPUCORE VR

SM

C_O

NO

FF

#

11

OR

9

+VCC_CORE,+VCCP

CLG

PIO

3/G

PIO

9

+V3.3A

LAN_WOL_EN9

BC_ACOK_BATT

PM_RSMRST#

ICH9M

MAX-809

6

6

Startup

6

6

6

CPU

12

7

i®AMPSCircuit

7

Circuit

7

15

7

7

99ms DELAY

7

7

7

PWROK

7

PM_PWRBTN#

6

6

6

CANTIGA

8 ALL_S

YS

_P

WR

GD

PLT

_R

ST

#

5AC

2

PS_ON_SW#

PM_PWROK

13

+V1.05M

VR_PWRGD_CLKEN#

PWRGD

PWRGD

17

DDR VR

+VBAT

IMVP_VR_ON

Sequence waits here forbutton press beforedoing step 1BAT = 5AC.

VR_PWRGD_CLKEN

SMC_RST#

PM_SYS_PWRGD

16

SYSTEMVR

PG 56

CLPWROK

1BAT

CK505SystemClock

DELAY_VR_PWRGOOD

+V3.3

+V5

ACAdapter

+V5A

+VBAT_S4 +VBAT

+V3.3A

SHT 56

SLP_S4SWITCHES

Battery OR ACinsertion cause 1

Only AC insertioncauses 1AC

DD

R_P

GG

OD

_R

U

8

+VBATA

5c

+VBAT

SHT 45

SHT 28

SHT 48

5b

SHT 42

+V1.05S

PM_ICH_PWROK

PWRGD

SHT 51

SHT 50

SHT 57

SHT 57

SHT 46

SHT 50

BatteryPack

SHT 35

+VCC_CORE

SHT6,7,8,9,10,11

SHT 3,4IMVP_VR_ON

5aLDO+V3.3A

+VBAT

+V3.3S_TVDAC

VCCP

+V5S

+VBATS

+V5A

11

PM_S4_STATE#PM_SLP_S3#

18

PM_SLP_S4#

8

GMCH

PM_S4_STATE#

PM_SLP_S4#

CANTIGA_VR_PWRGOOD

to lineswitches

SHT 11

+V1.8

to DDR VR

MCH,ICH CORE

+V0.9

PM_SLP_S3#

+V1.5S ICH LOGICSHT 47

PM

_S

LP

_S

3#

+VBAT

3

3

3

SLP_S3SWITCHES

Steps 1 leads to either 1BAT for battery only

mode or 1AC for AC mode. 5AC leads to 5a

to 5b to 5c to 6. Battery mode requires

button press to begin power up. AC mode

requires button press to boot.

Pillar Rock Mobile Power On Sequence

SHT 57

SWITCH+V3.3A+V3.3M_WOL

+VBS

+VBATA

7

7

ENABLE

(300ms MAX)

DB800MCLOCKBUFFERSSHT 36

CLK_PWRGD

SHT 40 & 41

CLK_PWRGD

14

14

SHT 47

SHT21,22,23,24

SHT 23

SHT 46

SHT 47

SHT 52

19

+V3.3S

+V5S

+V3.3S

SYSTEMVR POWERGOODMONITOR

+V3.3M

RSMRST#_PWRGD

+V3.3S

+V3.3A

VRPWRGD_3.3M_R

+V

5A

3A

_M

BL_

PW

RG

D

+V3.3A

SHT 46

3a

+V3.3A

MPWROK

CLPWROK

PWROK

to ICH & MCH

MPWROK

MPWROK

GFX VR

+V3.3A

+V3.3S_TVDAC

+V5A

+VCC_GFXCORE

PM_PGOOD_1_05M

+VBAT

GVR_VR_EN

PM_PWROK

ENABLE

EN

+V3.3S

LDO+V3.3A

7

+V1.5A_HDA_IO

PM_SLP_M#

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