Lab 5 IntroAdvanced Software Writing and Software Debugging Using SDK

Introduction This lab guides you through the process of writing a software application that utilizes timers and

an interrupt controller. You will use XPS to add the interrupt controller and a timer, and then connect the timer output to the interrupt controller. You will then develop an interrupt handler routine using the Software Development Kit (SDK). You will also use SDK to debug the software application.

Procedure1. Add and connect an interrupt controller and XPS timer2. Create a software project in SDK3. Complete a software application by writing an interrupt handler4. Add a linker script5. Verify operation in hardware

Summary This lab led you through assigning an interrupt handler function to an interrupting device such as

XPS timer. An interrupt controller was added to the system. The LibGen tool allowed you to update the parameters on the added and modified system. You also developed an interrupt handler function and viewed how the appropriate function can reduce the code size, which can have a major impact on resource requirements. You also learned how to debug software application using SDK.

Lab 5 – SDK Lab

Targeting MicroBlaze™ on the Spartan-3E™ Starter Kit

Lab 5: SDK LabIntroductionThis lab guides you through the process of adding timer and interrupt controller to an embedded system and writing a software application that utilizes these timer and interrupt controller. The SDK will be used to create and debug the software application.

ObjectivesAfter completing this lab, you will be able to:

• Utilize the XPS timer with interrupt controller• Assign an interrupt handler to the timer• Develop an interrupt handler function• Use SDK Debugger to set break points and view the content of variables and memory

ProcedureYou will extend the hardware design created in lab 5 to include an XPS interrupt controller and XPS Timer (see Figure 5-1). You will develop an interrupt handler to count the interrupts generated from the timer. The steps for completing the lab are listed below:

1. Add a timer and interrupt controller2. Create a SDK software project3. Write an Interrupt Handler4. Add a Linker script5. Verify operation in hardware

Add a Timer and Interrupt Controller Step 1

Create a lab5 folder and copy the contents of the lab4 folder into the lab5 folder, or copy the content of the labsolution\lab4 folder into the lab5 folder. Launch Xilinx Platform Studio (XPS) and open the project file.

1. Create a lab5 folder in the C:\xup\embedded\labs directory and copy the contents from lab4 to lab5, or copy the content of the labsolution\lab4 folder into the lab5 folder

2. Open XPS by selecting Start -> All Programs -> Xilinx ISE Design Suite 12 -> EDK -> Xilinx Platform Studio

3. Browse to the lab5 directory and open the project system.xmp

Add the XPS timer and XPS Interrupt Controller peripherals to the design from the IP Catalog, and connect them to the system according to the following table.

1. Add the XPS Timer/Counter peripheral from the DMA and Timer section of the IP Catalog, check Only One Timer is present option, and change its instance name to delay

2. Add the XPS Interrupt Controller peripheral from the Clock, Reset, and Interrupt section of the IP Catalog with default settings

3. Connect the timer and interrupt controller as a ‘s’ (slave) device to the PLB bus (see Figure 5-2)

4. Select Address tab and click Generate Addresses

5. The generated addresses should look similar to that indicated in the figure below

6. In the Ports section, type in timer1 as the Interrupt port connection of the delay instance, and hit enter

7. Make a new net connection (see Figure 5-4) for the INTERRUPT (external interrupt request) port on the microblaze_0 instance by selecting New Connection from the drop-down box. This will create a net called microblaze_0_INTERRUPT

8. Connect the interrupt controller and timer as follows (refer to Figure 5-5) Connect interrupt output port Irq of the xps_intc_0 instance to the MicroBlaze interrupt input

port using the microblaze_0_INTERRUPT net Click in intr field of xps_intc_0 field to open the Interrupt Connection Dialog. Click on

timer1 on left side, and click on sign to add to the Connected Interrupts field (right), and then click OK

Connect CaptureTrig0 port of delay instance to net_gnd to avoid erroneous interrupt request generated due to noice on the unconnected input port

9. Select Hardware -> Generate Bitstream

Create an SDK Software Project Step 2

Launch SDK and create a new software application project for the lab5 XPS project. Import the lab5.c source file.

1. Open SDK by selecting Project -> Export Hardware Design to SDK …2. Check Include Bitstream and BMM File option and click on Export & Launch SDK button.

This will implement the design if necessary and generate system.bit and system_bd.bmm

3. Right-click on standalone_bsp_0 in the Project Explorer window and select New C Project4. Enter lab5 in the Project Name field and choose Empty Project in Project type window 5. Click Finish6. Select lab5 in the project view, right-click, and select Import7. Extend the General folder and Double-click on File System and browse to c:\xup\embedded\

sources. Select lab5.c and click Finish

8. Right click on lab5 and select Changed Referenced BSP. Select standalone_bsp_0 and click OK. Note that both the Problems and Console tabs on the bottom report several compilation errors Note also that the project outline on the right side is updated to reflect the libraries and routines used in the source file

Correct the errors.

1. In the Problems tab, double-click on the first red x for the parse error. This will open the source file bring you around to the error place.

2. Add the missing global variable declaration as unsigned int, initialize it to the value of 1, and save the file. The first error message should disappear.

3. Click the next error message to highlight the problem in the source code

4. Add the missing global variable declaration as int, inititalize it to the value of 0, and save the file. The additional error messages should disappear.

Write an Interrupt Handler Step 3

Create the interrupt handler for the XPS timer1. Go to where the interrupt handler function has already been stubbed out in the source file (a fast

way to do this is to click on the function in the outline view).

Create new local variable for the timer_int_handler function: unsigned int csr;

The first step in creating an XPS timer interrupt handler is to verify that the XPS timer caused the interrupt. This can be determined by looking at the XPS Timer Control Status Register. Open the API documentation to determine how the Control Status Register works.

1. In the XPS System Assembly View window, right-click the delay instance and select View PDF Datasheet to open the data sheet

2. Go to the Register Description section in the data sheet and study the TCSR0 Register. Notice that bit 23 has the following description:

Timer0 InterruptIndicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1

Read:0 - No interrupt has occurred1 - Interrupt has occurredWrite:0 No change in state of T0INT

1 Clear T0INT (clear to ’0’)The level 0 driver for the XPS timer provides two functions that read and write to the Control Status Register. View the timer API doc by right-clicking on the delay instance in the System Assembly View and selecting Driver:tmrctr_v2_00_a _ View API Documentation. In the API document, click on the File List link at the top of the document, then click on the link labeled xtmrctr_l.h in the file list. This brings up the document on identifiers and the lowlevel driver functions declared in this header file. Scroll down in the document and click on the link for the XTmrCtr_GetControlStatusReg( ) function to read more about this function. Use this function to determine whether an interrupt has occurred. The following is the pertinent information found in the XPS timer documentation:

XTmrCtr_GetControlStatusReg ( BaseAddress, TmrCtrNumber )Get the Control Status Register of a timer counter

o Parameters: BaseAddress is the base address of the device. TmrCtrNumber is the specific timer counter within the device, a zero-based

number, 0 -> (XTC_DEVICE_TIMER_COUNT - 1)o Returns:

The value read from the register, a 32-bit value

3. Add the XTmrCtr_GetControlStatusReg function call to the code with the associated parameters. The resulting 32-bit return value should be stored in the variable csr.

csr = XTmrCtr_GetControlStatusReg(baseaddr, 0);

Note: Substitute baseaddr with the base address for the delay peripheral. Refer to xparameters.

4. Complete the Interrupt handler (see Figure 5-15) according to the steps below1. Test to see if bit 23 is set by ANDing csr with the XTC_CSR_INT_OCCURED_MASK

parameter.2. Increment a counter if an interrupt was taken.3. Display the count value by using the LEDs_8Bit peripheral and print the value using

xil_printf (same functionality as printf with the exception of floating-point handling)Hint: You may use the XGpio_DiscreteWrite () function

4. Clear the interrupt by using the following function call:XTmrCtr_SetControlStatusReg(baseaddr, 0, csr);

The completed handler should look like as shown in the next figure

5. Save the file, this should compile the source successfully.

Add Linker Script Step 4

Generate the linker script by assigning code section to ilmb and data section to xps_bram. Set heap and stack to 0x400 each.

1. Right-click lab5 in project view and select Generate Linker Script2. Set the heap and stack size to 1024 each3. Assign Code section to ilmb_cntlr_dlmb_cntlr and Data, Stack and Heap sections to

xps_bram_if_cntlr (this is necessary as each of the memory is too small to hold everything)

4. Click Generate to generate the linker script, add to the project and recompile the program.

Look in the console to answer the following question.1. What is the size of the compiled program?

.text segment:

.data segment:

.bss segment:Total in decimal:Total in hexadecimal:

Verify Operation in Hardware Step 5

Generate the bitstream and download to the Spartan-3E starter kit.Connect and power the board

1. Select Xilinx Tools -> Program FPGA2. Browse and select system.bit and system_bd.bmm files from the lab5\implementation (this

step is required for 12.2 version. For other version, you may skip this step and try with the default paths to see if it works)

3. Click ProgramThis will execute Data2Mem program to combine the bootloop executable with hardware bitstream, generate the download.bit file, and configure the FPGA.

4. Select Terminal tab (near console area), and click on New Terminal Connection

5. Select correct COM port and 115200 baudrate, and click OK

Launch Debugger and debug

1. From the SDK Menu, select Run -> Run configurations…This will present a screen summarizing the existing Launch Configurations

2. Under Configurations, select Xilinx C/C++ ELF

3. Click on New to add a new Launch configuration.

4. Click on the Run button. The application will run. You should see messages in the Console and the LEDs should be flickering

5. Click Debug to invoke the debug session6. Click YES to stop the current execution. Click YES to launch the Debug perspective7. Right-click in the Variables tab and select Add Global Variables … All global variables will be

displayed. Select count variable and click OK

Monitor variables and memory content.1. Double-click to set a breakpoint on the line in lab5.c where count is written to LED

2. Click on Resume button to continue executing the program up until the breakpoint.As you do step over, you will notice that the count variable value is changing.

3. Click on the memory tab. If you do not see it, go to Window -> Show View -> Memory

4. Click the sign to add a Memory Monitor

5. Enter the address for the count variable as follows, and click OK

6. Click the Resume button to continue execution of the program.Notice that the count variables increment every time you click resume.

7. Terminate the session by clicking on the Terminate button.

8. Close the SDK application and close the XPS project

Conclusion

This lab led you through adding an XPS timer and interrupt controller, and assigning an interrupt handler function to the interrupting device via the software platform settings. You developed an interrupt handler function and tested it in hardware. Additionally, you used the SDK debugger to view the content of variables and memory.

Answers1. What is the size of the compiled program?

.text segment: 6954

.data segment: 388

.bss segment: 2122Total in decimal: 9454Total in hexadecimal: 24ee

Completed MHS File######################################################################## Created by Base System Builder Wizard for Xilinx EDK 12.2 BuildEDK_MS2.63c# Tue Jul 20 10:08:16 2010# Target Board: Xilinx Spartan-3E Starter Board Rev D# Family: spartan3e# Device: XC3S500e# Package: FG320# Speed Grade: -4# Processor number: 1# Processor 1: microblaze_0# System clock frequency: 50.0# Debug Interface: On-Chip HW Debug Module########################################################################PARAMETER VERSION = 2.1.0PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX_pin, DIR = IPORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX_pin, DIR = OPORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin,DIR = O, VEC = [0:7]PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = OPORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0]PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0]PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0]PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0]PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0]PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IOPORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK,CLK_FREQ = 50000000PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1PORT push_GPIO_IO_I_pin = push_GPIO_IO_I, DIR = I, VEC = [0:3]PORT dip_GPIO_IO_I_pin = dip_GPIO_IO_I, DIR = I, VEC = [0:3]PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = [0:6]

BEGIN microblazePARAMETER INSTANCE = microblaze_0PARAMETER C_AREA_OPTIMIZED = 1PARAMETER C_DEBUG_ENABLED = 1PARAMETER HW_VER = 7.30.b

BUS_INTERFACE DLMB = dlmbBUS_INTERFACE ILMB = ilmbBUS_INTERFACE DPLB = mb_plbBUS_INTERFACE IPLB = mb_plbBUS_INTERFACE DEBUG = microblaze_0_mdm_busPORT MB_RESET = mb_resetPORT INTERRUPT = microblaze_0_INTERRUPTEND

BEGIN plb_v46PARAMETER INSTANCE = mb_plbPARAMETER HW_VER = 1.04.aPORT PLB_Clk = clk_50_0000MHzPORT SYS_Rst = sys_bus_resetEND

BEGIN lmb_v10PARAMETER INSTANCE = ilmbPARAMETER HW_VER = 1.00.aPORT LMB_Clk = clk_50_0000MHzPORT SYS_Rst = sys_bus_resetEND

BEGIN lmb_v10PARAMETER INSTANCE = dlmbPARAMETER HW_VER = 1.00.aPORT LMB_Clk = clk_50_0000MHzPORT SYS_Rst = sys_bus_resetEND

BEGIN lmb_bram_if_cntlrPARAMETER INSTANCE = dlmb_cntlrPARAMETER HW_VER = 2.10.bPARAMETER C_BASEADDR = 0x00000000PARAMETER C_HIGHADDR = 0x00001fffBUS_INTERFACE SLMB = dlmbBUS_INTERFACE BRAM_PORT = dlmb_portEND

BEGIN lmb_bram_if_cntlrPARAMETER INSTANCE = ilmb_cntlrPARAMETER HW_VER = 2.10.bPARAMETER C_BASEADDR = 0x00000000PARAMETER C_HIGHADDR = 0x00001fffBUS_INTERFACE SLMB = ilmbBUS_INTERFACE BRAM_PORT = ilmb_portEND

BEGIN bram_blockPARAMETER INSTANCE = lmb_bramPARAMETER HW_VER = 1.00.aBUS_INTERFACE PORTA = ilmb_portBUS_INTERFACE PORTB = dlmb_portEND

BEGIN xps_uartlitePARAMETER INSTANCE = RS232_DCEPARAMETER C_BAUDRATE = 115200PARAMETER C_DATA_BITS = 8PARAMETER C_USE_PARITY = 0PARAMETER C_ODD_PARITY = 0PARAMETER HW_VER = 1.01.aPARAMETER C_BASEADDR = 0x84000000

PARAMETER C_HIGHADDR = 0x8400ffffBUS_INTERFACE SPLB = mb_plbPORT RX = fpga_0_RS232_DCE_RX_pinPORT TX = fpga_0_RS232_DCE_TX_pinEND

BEGIN xps_gpioPARAMETER INSTANCE = LEDs_8BitPARAMETER C_ALL_INPUTS = 0PARAMETER C_GPIO_WIDTH = 8PARAMETER C_INTERRUPT_PRESENT = 0PARAMETER C_IS_DUAL = 0PARAMETER HW_VER = 2.00.aPARAMETER C_BASEADDR = 0x81440000PARAMETER C_HIGHADDR = 0x8144ffffBUS_INTERFACE SPLB = mb_plbPORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pinEND

BEGIN mpmcPARAMETER INSTANCE = DDR_SDRAMPARAMETER C_NUM_PORTS = 1PARAMETER C_SPECIAL_BOARD = S3E_STKITPARAMETER C_MEM_TYPE = DDRPARAMETER C_MEM_PARTNO = MT46V32M16-6PARAMETER C_MEM_DATA_WIDTH = 16PARAMETER C_PIM0_BASETYPE = 2PARAMETER HW_VER = 6.01.aPARAMETER C_MPMC_BASEADDR = 0x8c000000PARAMETER C_MPMC_HIGHADDR = 0x8fffffffBUS_INTERFACE SPLB0 = mb_plbPORT MPMC_Clk0 = clk_100_0000MHzDCM0PORT MPMC_Clk90 = clk_100_0000MHz90DCM0PORT MPMC_Rst = sys_periph_resetPORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pinPORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pinPORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pinPORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pinPORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pinPORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pinPORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pinPORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pinPORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pinPORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pinPORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pinPORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pinPORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pinPORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pinEND

BEGIN clock_generatorPARAMETER INSTANCE = clock_generator_0PARAMETER C_CLKIN_FREQ = 50000000PARAMETER C_CLKOUT0_FREQ = 100000000PARAMETER C_CLKOUT0_PHASE = 90PARAMETER C_CLKOUT0_GROUP = DCM0PARAMETER C_CLKOUT0_BUF = TRUEPARAMETER C_CLKOUT1_FREQ = 100000000PARAMETER C_CLKOUT1_PHASE = 0PARAMETER C_CLKOUT1_GROUP = DCM0PARAMETER C_CLKOUT1_BUF = TRUEPARAMETER C_CLKOUT2_FREQ = 50000000PARAMETER C_CLKOUT2_PHASE = 0

PARAMETER C_CLKOUT2_GROUP = NONEPARAMETER C_CLKOUT2_BUF = TRUEPARAMETER C_EXT_RESET_HIGH = 1PARAMETER HW_VER = 4.00.aPORT CLKIN = dcm_clk_sPORT CLKOUT0 = clk_100_0000MHz90DCM0PORT CLKOUT1 = clk_100_0000MHzDCM0PORT CLKOUT2 = clk_50_0000MHzPORT RST = sys_rst_sPORT LOCKED = Dcm_all_lockedEND

BEGIN mdmPARAMETER INSTANCE = mdm_0PARAMETER C_MB_DBG_PORTS = 1PARAMETER C_USE_UART = 1PARAMETER C_UART_WIDTH = 8PARAMETER HW_VER = 1.00.gPARAMETER C_BASEADDR = 0x84400000PARAMETER C_HIGHADDR = 0x8440ffffBUS_INTERFACE SPLB = mb_plbBUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_busPORT Debug_SYS_Rst = Debug_SYS_RstEND

BEGIN proc_sys_resetPARAMETER INSTANCE = proc_sys_reset_0PARAMETER C_EXT_RESET_HIGH = 1PARAMETER HW_VER = 2.00.aPORT Slowest_sync_clk = clk_50_0000MHzPORT Ext_Reset_In = sys_rst_sPORT MB_Debug_Sys_Rst = Debug_SYS_RstPORT Dcm_locked = Dcm_all_lockedPORT MB_Reset = mb_resetPORT Bus_Struct_Reset = sys_bus_resetPORT Peripheral_Reset = sys_periph_resetENDBEGIN xps_gpioPARAMETER INSTANCE = dipPARAMETER HW_VER = 2.00.aPARAMETER C_GPIO_WIDTH = 4PARAMETER C_ALL_INPUTS = 1PARAMETER C_BASEADDR = 0x81420000PARAMETER C_HIGHADDR = 0x8142ffffBUS_INTERFACE SPLB = mb_plbPORT GPIO_IO_I = dip_GPIO_IO_IEND

BEGIN xps_gpioPARAMETER INSTANCE = pushPARAMETER HW_VER = 2.00.aPARAMETER C_GPIO_WIDTH = 4PARAMETER C_ALL_INPUTS = 1PARAMETER C_BASEADDR = 0x81400000PARAMETER C_HIGHADDR = 0x8140ffffBUS_INTERFACE SPLB = mb_plbPORT GPIO_IO_I = push_GPIO_IO_IEND

BEGIN lcd_ipPARAMETER INSTANCE = lcd_ip_0PARAMETER HW_VER = 1.00.aPARAMETER C_BASEADDR = 0xcf400000

PARAMETER C_HIGHADDR = 0xcf40ffffBUS_INTERFACE SPLB = mb_plbPORT lcd = lcd_ip_0_lcdEND

BEGIN bram_blockPARAMETER INSTANCE = bram_block_0PARAMETER HW_VER = 1.00.aBUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTAEND

BEGIN xps_bram_if_cntlrPARAMETER INSTANCE = xps_bram_if_cntlr_0PARAMETER HW_VER = 1.00.bPARAMETER C_SPLB_NATIVE_DWIDTH = 32PARAMETER C_BASEADDR = 0x88208000PARAMETER C_HIGHADDR = 0x88209fffBUS_INTERFACE SPLB = mb_plbBUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTAEND

BEGIN xps_timerPARAMETER INSTANCE = delayPARAMETER HW_VER = 1.02.aPARAMETER C_ONE_TIMER_ONLY = 1PARAMETER C_BASEADDR = 0x83c00000PARAMETER C_HIGHADDR = 0x83c0ffffBUS_INTERFACE SPLB = mb_plbPORT CaptureTrig0 = net_gndPORT Interrupt = timer1END

BEGIN xps_intcPARAMETER INSTANCE = xps_intc_0PARAMETER HW_VER = 2.01.aPARAMETER C_BASEADDR = 0x81800000PARAMETER C_HIGHADDR = 0x8180ffffBUS_INTERFACE SPLB = mb_plbPORT Intr = timer1PORT Irq = microblaze_0_INTERRUPTEND