Lab3: Pipeline
Transcript of Lab3: Pipeline
Lab3: Pipeline
Dimitar Nikolov
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Goal
• Understand how pipelining works
• Learn what happens in different pipeline stages
• Leran how to avoid pipeline hazzards
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Tools
• Tools used for this exercise:
– MipsIt.exe
– MipsPipeS.exe
Used for program editing
Used for simulation
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Online test
• The online test is scheduled on Monday 23th November
• Access the test from the course web-page
• Example of an online test is provided
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Overview
• Background
• Simulation
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Motivation
• Instructions are exectued one at a time
• Each instruction occupies a set of resources
– access to memory
– access to registers
– access to ALU
• Resources are not occupied all the time
• Execution of an instruction can be split into a number of
stages
• Overlap execution of instructions
• Goal: improve throughput (number of instructions over time)
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Pipeline
• Execution of instructions is split into a sequence of
dependent stages
• Once an instruction has completed with one stage it can
proceed to the next stage, and a new instruction can take
over the stage that has been released
• The time to execute a single instruction is not altered
• The number of executed instructions over time is increased
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MIPS pipeline
• Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register
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IF (Instruction Fetch)
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ID (Instruction decode & register read)
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EX (Execute operation or calculate address)
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MEM (Access memory operand)
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WB (Write result back to register)
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Potential hazards
• Structural hazards
– A resource is used by two instructions that are in
different pipeline stages
• Data hazards
– Due to data dependencies between instructions
• Control hazards
– Due to branch instructions
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Structural hazards
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
Memory
read
IF ID EX MEM WB
time
Use separate Instruction and Data Cache
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Data hazards
ADD $s0, $t0, $t1
SUB $t2, $s0, $t3 Read after Write (RAW) dependency
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Data hazards
Need to stall
for one cycle
Forwarding
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Data hazards
Stall inserted
here
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Control hazards
• Branch is taken or not taken
• The next instruction to be fetched might depend on the
branch condition
• The condition may not be evaluated before the branch
instruction reaches the MEM stage in the pipeline
• Unneeded instructions are already in the pipeline
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Control hazards
• To avoid:
– Delayed branching (place the branch instruction earlier
in the code, without violating data dependencies, and
proceed with the instructions that must be executed
irrespective of the evaluation of the branch condition)
– Delayed branching (add nops after the branch
instruction, such that in case the branch is taken the
nops will fill in the pipeline prior to the execution of
instructions that should be executed when the branch
is taken)
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Overview
• Background
• Simulation
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Compile, Build and Upload
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MipsPipeS
Click to see the pipeline
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MipsPipeS Simulate by stepping
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