ECE 3349 – Introduction to VLSI - Lab 1Digital Gates - Schematic Design and Simulation

1 Lab #1 objectives

In this laboratory experiment the students are expected to design and simulateschematic view of three basic digital gates: INV, NAND2 and NOR2. This partof the design flow includes the following steps:

• Create circuit schematics

• Create the symbol view

• Create simulation test-benches for typical model parameters

• Using the theoretical width-ratio between PMOS and NMOS transistors (ap-proximately two) as a starting point, resize and re-simulate the transistor sizesso that:

1. approximately equal rise and fall times of the signal pulses at the outputs areachieved, i.e. the cross-over point at around VDD/2.2. gate propagation delay and power dissipation of the gates can be measured.3. the gate performance can be measured as a function of varying the load capacitance.

2 Pre-lab requirements

For this lab the students are expected to have fully understand first lab tutorial.

3 Setting up Cadence

All initial setup for Cadence was explained in the first lab tutorial, therefore startcadence by opening the terminal window, change the working directory and startcadence by typing:source Start Cadence AMS.csh

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Figure 1: Virtuoso Command Window

After the software loading is finished the Virtuoso window should be on your screen,Fig. 1. Please keep this window visible at all times, all process messages regardingyour work are reported there.

4 Creating the Schematic

Since this is the first design for this course, we first need to create a new library foryour designs. In the Virtuoso window, use the pull–down menus and select file File→ New → Library. In the new library window dialog window that pops up, entera suitable name for your library (i.e., ECE3349) and select Attach to existing tech filethen click OK. In the next window, change the technology file to gpk090. Click OK.Your new library is now fully created. Now that we have a library we must create aCell View for the schematic. In the Virtuoso window, select File → New → CellView. Fill in the create new file window as described below and then click OK. Usethe same library as specified earlier.Each design consists of several files, referred to as ”Cell View” in Cadence. In thiscourse, for most cells we will create the following views: schematic, symbol, layout,extracted, analog extracted, and config.

4.1 Inverter Design

Create a new cell view for the schematic. Either using the library manager, Fig. 2,or in the Virtuoso window create new cell. If using the library manger, cell nameand view name can be typed in the blank spaces at the headers of the appropriatefields. If the Virtuoso menu is used, select File → New → Cell View. Fill in the”Create New File” window, Fig. 3, and click OK. Whichever method is used, fill inthe following data:

Library Name-the working library for this course is the ece3349b.

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cell name-type inverter.View Name-type schematic.

Figure 2: Library Manger window

4.1.1 Schematic design

The schematic editing window, Fig. 4, shows the schematic for the inverter alreadyentered. To place the transistors, either use the pull down menu Create→ Instanceor press ”i” with the mouse pointer in the schematic editing window. Also, there areshortcut buttons on the upper side of the schematic editing window for the mostcommonly used operations.In the add instance window, shown in Fig. 5, click Browse and choose the followingfrom the library browser window:Library PDKg90n ITDBCell pmos1vView symbol

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Figure 3: Create New File window

Table 1: Recommend Parameters of Transistors.pfet nfet

Width[m] wpfet wnfet

Length[m] 100n 100n

For the transistor parameters, enter the information shown in Table 1. It is assumedthat for digital logic gates design the minimum allowed gate length is used for alltransistors(Do you know why?). That leaves manipulation of the gate width as theonly design parameter. While working on design in progress it is useful to use variablesinstead of fixed numbers. This approach allows designer to easily optimize the designby varying the gate widths using a parametric analysis tool. Make sure that whilesetting the vdd and vss pins, their ”Direction” is set to ”inputOutput”, whilethe in pin direction is set to”input” and the out pin direction is set to ”output”.Once the schematic is entered, either press the ”check and save” icon in the upperleft corner of the schematic editing window, or check and save it using menu File →Check and Save. If there are errors or warnings, check in the Virtuoso window tosee what they are and try to fix them.

4.2 Creating the Symbol View

Select Design → Create Cellview → From Cellview. In the Cellview FromCellview window that pops up, ensure that From View Name is set to schematicand To View Name is set to Symbol, click OK. Manually move ”vss” label into the

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Figure 4: Schematic Editing Window

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Figure 5: Add Instance window

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Figure 6: Symbol Generation Options

”Bottom Pins” section, Fig. 6.When you are finished with the options, click OK. The Symbol Editing windowwill now open. Change the default rectangular symbol shape into the one which iscommonly used to represent an inverter, Fig. 7. Use the upper side tool buttons,Add and Edit commands from the menu to make changes to the symbol. Check andsave the symbol when you are done. Now that you have a symbol created for yourinverter, you can use it in schematics. You are now ready to create a test bench foryour inverter.

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Figure 7: Inverter Symbol

5 Creating a Testbench for the Inverter

Create a new schematic cellview in the library, for example, inverter sim. Placean instance of the inverter, add dc voltage source (vdc from analogLib) as a powersupply, a ground connection, and load capacitor (cap from analogLib). Add pulsevoltage sources at the inputs of the inverters (vpulse from analogLib). Power pinsvdd and gnd are from analogLib, Fig. 8.Note, in a good simulation setup that: 1) a more realistic pulse source is createdby using an inverter as a buffer between the ideal pulse source and the device undertest (DUT); 2) a capacitive load is used with capacitance value set to a variable, forexample ”cload”, so that its value could be swept during the simulation tests. In Fig.8 the white boxes are added to emphasize the point. These text layer objects andcomments can be added from the menu using Create, Note, Shape buttons. In thissimulation setup, wires labelled inand out are used as ”realistic” test points.

5.1 Device Parameters Setup

To access device parameters, point at the device and press Q (deselect by clickinganywhere outside the symbols), then create the following device setup:1. Power supply: set DC voltage to 1.2V2. Capacitve load set capacitance to cload, 10fF is appropriate size for this tech-nology.3. Pulse source: the pulse source parameters used are shown in Fig. 9. A 1GHzsquare wave with 10ps rise and fall times is used. This requires a period of 1ns and apulse width of 490ps (due to the rise and fall times) as the pulse width is measuredbetween the 50% points - therefore 5ps will be added from each of tr and tf to make

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Figure 8: Inverter Testbench

up the total 500ps pulse width.Check and save your testbench.

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Figure 9: Square wave source setup

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6 Simulation

From the inverter sim schematic window select Launch → ADE L to open AnalogDesign Environment window, Fig. 10. There are a number of options to set beforerunning the simulation, as discussed in the following subsections.

6.1 Environment Options

This section is, basically, setting up a virtual electronic test bench, as if there was areal oscilloscope to be used for time domain (transient) tests. Please refer to Chapter4 in Tutorial lab to set up simulation environment.

6.2 Choosing Analyses

Either select Analyses → Choose or use the button on the right side. For settinga transient analysis which will run for 100ns (i.e. which will include 100 pulses fromthe source), fill in the information in the Choosing Analyses window, as shown in Fig.11. Make sure that it is enabled. Click OK.

6.3 Setting Design Variables

Design variables used in the design (cload, wpfet, wnfet) are set as follows.First, to make sure that all variables left in the schematic are listed, select Variables→ Copy From Cellview. The design variables are now listed in the Analog DesignEnvironment sub-window, Fig. 10. Select one by one variable by double-clicking on itand change its value. When finished with all variables, check and save the testbench.

6.3.1 Saving simulation setup

Once the simulation environment is set, it can be saved for the future use, insteadof redoing the setup every time. In the Analog Design Environment window, clickSession → Save State, then give the state a name which can be chosen arbitrarily,for example transient sim, and click OK. Next time just reload this state using thesame menu. It is possible to create as many states as needed.

6.4 Running the Simulation

The simulation is ready to run, either click Simulation → Run from the menu oruse the green light button on the right side. Monitor the output listed in the Virtuosowindow for possible errors. When the simulation has completed successfully, the lastline of the Virtuoso window will say ... successful.To verify correct operation of the inverter, use the calculator to choose and displayvoltage and current waveforms, in the Analog Design Environment window selectTools → Calculator. Click on vt button to initiate selection of voltage waveforms,move the cursor over the schematic window and select the wire labelled as out.Click plot calculator button to erase any previous graph and plot the new one. One

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Figure 10: Analog Design Environment

Figure 11: Setting Transient Analyses

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Figure 12: Setting up eye diagram parameters

hundred pulses long waveform is not much useful displayed in this form. One way tosee single pulses is to zoom in the graph by using the mouse.

6.4.1 Displaying Eye Diagram

The most useful form of displaying a long periodic waveforms is known as ”Eye Dia-gram”. Instead of displaying the full length of the signal at once, a half-period longsections are overlapped on top of each other instead. Effectively, the long signal is”cut” into pieces, each piece containing either a single rising or falling edge. Thataction of ”cutting” is achieved using the calculator’s Special Functions → eyeDia-gram buttons. Eye diagram configuration window, Fig. 12, is then used to determinethe size of the pieces. Although, one could start displaying data from the very begin-ning, it produces more convenient plot if the Start Time is set to one quarter of theinput signal’s period, in this case 0.25ns. Naturally, the Stop Time should be set toinclude all data points to the end of the simulation run, in this case 100ns. Finally,the Period in this window refers to periodicity of the desired overlapping sections,effectively setting the time duration of each of the ”cut” sections. It should be setto one half of the signal’s period, in this case 0.5ns, so that only one edge is insideeach of the sections. This way of setting the eye diagram parameters produces veryconvenient eye diagram plot, Fig. 13. Measuring the edge cross-over point is notstraightforward.

6.5 Tuning the pfet Channel Width to Achieve Equal Riseand Fall Times

To verify that the transistor dimensions do influence the cross-over point, and thatthe value set in the previous sections is the most optimal one, run parametric analysissimulation. Use gate width of the PMOS transistor wpfet as a sweeping parameter,

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Figure 13: Eye diagram of the 1GHz waveform output

while holding the NFET transistor size constant. In that case, size of the PFETchanges relative to the NFET which, effectively, makes one transistor either weakeror stronger in terms of the current carrying capability, relative to the other transis-tor. For a perfect cross-over point at VDD/2 (i.e. 0.6V in this case) both transistorsshould have the same current carrying capability. That happens only when (for thesame gate length) the PMOS transistor is around two times wider, (do you knowwhy?).

After running parametric analysis where wpfet is swept from 0.2µm to 2.0µm in tensteps, Fig. 14, use calculator again then the plot in Fig. 15 is obtained.

6.6 Propagation Delay Time

In ideal case, if there was no propagation delay, effect of the input signal would havebeen instantaneously seen at the output of an inverter. In other words, a risingedge at the input of an inverter would cause falling edge at the output without anydelay. In reality, there is a finite time needed to charge up all capacitances insidethe inverter, and to change all electromagnetic fields of all conductors carrying fastswitching current. Therefore, the propagation delay time of an inverter is the timedifference between the moment when the input edge shows up, and the time whenthe corresponding output edge shows up, Fig. 16.Although the measurement could be done manually by zooming in the eye diagramand measuring the time delay between corresponding edges at the output and input

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Figure 14: Parametric analysis results

Figure 15: Parametric analysis results

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Figure 16: Graphical Representation of Delay Function Parameters

nodes it is much more convenient to use build-in function of the calculator. Bothversions of the calculators can produce the result so, for sake of practising, switch tothe WaveScan tool in the Analog Design Environment options section. Out of thislong stream of events with rising and falling edges, an arbitrarily, the 10th event isused, Fig. 17.This delay usually vary depending on whether the output is changing high-to-low orvice versa. The propagation delay should be measured at the cross-over point, i.e.at half of the supply voltage (in this case at 0.6V). The propagation delay is thencalculated as average value of these two cases: tpd=(tpdr+tpdf)/2

where tpdr is propagation delay of low-to-high transition, and tpdf is propagationdelay of high-to-low transition.

6.7 Power Dissipation

Power consumption is very important parameter. By definition, power is product ofvoltage and current. In case of time varying, i.e. not DC, power it is convenient toreport rms value. In this case, the voltage VDD is at constant DC value of 1.2V. Inthe same time, the gate current consumption is dynamic, i.e. the current flows onlyduring the transition periods.

Therefore, use calculator to measure current consumed by the inverter being simulated

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Figure 17: Measuring low-to-high propagation delay time

(DUT). To do so, before running transient simulation, in Analog Design Window clickOutputs → To Be Saved and then select the vdd terminal of the DUT, (make surethat the right node is selected). Check in the Output sub-window that current ofthis node is added to the list. After re-running the transient simulation, use thecalculator to probe this current, and apply Special Functions → rms. It is nowstraightforward to multiply this value with VDD voltage (1.2V in this case) to findRMS power consumption of a single inverter gate.

6.8 Effect of Load Capacitance on the Inverter

Run a parametric analysis on the testbench, after setting the load capacitance pa-rameter cload on the inverters to be swept from 1fF to 50fF, then display the eyediagram of the output node. Please comment about the output of this experiment.Can you explain what is happening?

7 Design of NAND2 and NOR2 gates

To finish this lab, design two more gates: two input NAND2, and two input NOR2,by repeating the design and simulation steps used to design the inverter.As a reference, schematics of a two input NAND2 and NOR2 gates is shown in Fig. 18.Please, note that these two schematics must be put in separate files.Hints: 1) for NAND2 gate start with all transistors having gate width w=1.2µm.For NOR2 gate start from wpfet=2.4µm and wnfet=0.6µm; 2) for simulations, inputs

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Figure 18: Schematic diagrams of NAND2 and NOR2 gates

of the gates should be connected to pulsed signal sources with periods T and 2T.

8 Summary

Three gates (INV, NAND2 and NOR2), have been designed in this lab. Design detailsand simulation results for: 1) gate propagation; 2) RMS power consumption; and 3)range of values acceptable for the capacitive loads for each gate should be listed inthe final report document.

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9 Common Shortcuts

• ’i’ – Add instance

• ’q’ – Edit properties of selected of selected object

• ’m’ – Move selected object

• ’c’ – Copy selected object

• ’p’ – Add pin

• ’r’ – Rotate selected object

• ’l’ – Add wire name

• ’w’ – Add wire

• ’f’ – Fit schematic in window

• ’F6’ – Redraw Window

• ’shift–v’ – World view

• ’]’ – Zoom in

• ’[’ – Zoom out

• ’shift – x’ – Check and Save

• ’x’ – Check

• ’shift – s’ – Save

• ’shift – m ’ – Move component only. Does not move connected wires

• ’z’ – Zoom on a selected area using the mouse

• ’m + F3’ – When moving a selected object you can press F3 to evoke the Stretchmenu to rotate, sideways (mirror), and upside down the selected object

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