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Lab Report EE4415 Integrated Digital Design

Simon Christen (N0801081J)

April 20, 2009

Contents

1 Introduction 31.1 The Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 This Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 To Generated Reports . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Unit 1: Introduction to Synopsys Chip Synthesis and DesignFlow 42.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 General Questions . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Unit 2: Design Compiler Setup and Synthesis Flow 53.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.2 Task 2 - Invoke Design Vision . . . . . . . . . . . . . . . . . . . . 53.3 Task 8 - Generating a Timing and Area Report . . . . . . . . . . 53.4 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Unit 3: Partitioning for Better Synthesis Results 84.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84.2 Task 1 - Analyze Partitioning of PRGRM_CNT_TOP . . . . . 84.3 Task 2 - Repartition using group and ungroup . . . . . . . . . . . 84.4 Task 3 - Compile and Analyze Results . . . . . . . . . . . . . . . 94.5 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Unit 4: Introduction to DC-Tcl 115.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115.2 Script File: runit.tcl . . . . . . . . . . . . . . . . . . . . . . . . . 115.3 Task 4 - Create and Test runit.tcl . . . . . . . . . . . . . . . . . . 12

6 Unit 5: Apply Timing Constraints to PRGRM_CNT_TOP 146.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146.2 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146.3 Task 2 - Examine the core_slow Library . . . . . . . . . . . . . . 146.4 Task 3 - Constrain PRGRM_CNT_TOP . . . . . . . . . . . . . 146.5 Task 4 - Check your work and Save the Results . . . . . . . . . . 156.6 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1

7 Unit 6: Apply Environmental Attributes 167.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.2 To Get You Started . . . . . . . . . . . . . . . . . . . . . . . . . 167.3 Task 1 - Apply Environmental Constraints and Attributes . . . . 197.4 Task 2 - Check Work and Save Design . . . . . . . . . . . . . . . 217.5 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Unit 7: Design Rules and Min Timing 238.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238.2 Questions: To get You Started . . . . . . . . . . . . . . . . . . . 238.3 Task 1 - Complete Script File . . . . . . . . . . . . . . . . . . . . 238.4 Task 3 - Generate Reports . . . . . . . . . . . . . . . . . . . . . . 238.5 Task 4 - Fix Design Rule Violations and Hold . . . . . . . . . . . 23

9 Unit 8: Timing Reports 259.1 Fazit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259.2 Questions from Task 2.2 . . . . . . . . . . . . . . . . . . . . . . . 259.3 Questions from Task 2.3 . . . . . . . . . . . . . . . . . . . . . . . 259.4 Questions from Task 2.4 . . . . . . . . . . . . . . . . . . . . . . . 279.5 Questions from Task 2.5 . . . . . . . . . . . . . . . . . . . . . . . 279.6 Questions from Task 2.6 . . . . . . . . . . . . . . . . . . . . . . . 30

10 Fazit 3210.1 Lab and Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11 Aditional 3311.1 How to do Remote Access . . . . . . . . . . . . . . . . . . . . . . 33

12 Appendix 3412.1 Lab5 Task4 16a . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3412.2 Lab6 Task2 Report . . . . . . . . . . . . . . . . . . . . . . . . . . 4312.3 Lab6 Task2 Report2 . . . . . . . . . . . . . . . . . . . . . . . . . 4512.4 Lab6 Report Library . . . . . . . . . . . . . . . . . . . . . . . . . 5712.5 Lab6 Task2 Generated Script . . . . . . . . . . . . . . . . . . . . 75

2

1 Introduction

1.1 The Lab

The lab was conducted in the second part of the spring semester 2009 as a partof the lecture Integrated Digital Design.

It consisted of eight compulsory units which's main goal is to introducethe design �ow of digital design and to familiarize with the Synopsys DesignCompiler. I worked mainly in three areas:

• partitioning

• setting constraints (area, timing)

• and analyzing their ful�llment in di�erent reports

1.2 This Report

I wasn't sure how to do the report properly. I knew that it should answer thelab questions, contain some of the output and give a sort of comment on everylab I did.

I tried to make the report as structured as possible, but since the lab wasdone over a long time period, there are sometimes changes in the structure andillustration (e.g. generated reports as a separated picture or included in thetext, in the report or in the appendix, etc.)

1.3 To Generated Reports

Unfortunately I didn't know during the labs (1,2,3,4,5,6,7) that we should attachall the generated reports to this report, so I newer saved them. During writingthis �nal report at the end of the semester, I started to go back and redo thelabs to regenerate this reports. The long ones I attached in the appendix, theshort ones are integrated directly into the report. I did this for Lab 7 and 6.Then I stopped, since �rst it was to much work to redo all the labs and secondlythe report became also quite long.

But out of the answered questions in Lab 1-5 you can see that I generatedthis reports during the labs, I just didn't save them.

3

2 Unit 1: Introduction to Synopsys Chip Synthe-

sis and Design Flow

2.1 Fazit

In this �rst lab I got an impression what the further labs might be like. It waskind of a summarized �go through the basic steps of synthesis� exercise. I saw:

• What synthesis means: TRANSLATION + OPTIMIZATION + MAP-PING

• check the setup-�le of a design

• read a VHDL/Verilog �le

• how to display it in the GUI

• I applied constraints by a script,...

• ... performed a compile, ...

• ... and saved it as a .ddc �le. There I learnt also

� how to save the command history: The button at the bottom edgeof the command window:alternatively you can also look at the .log �le...

• Finally I did the �rst analyzing, which how to do I learnt better in laterlabs.

2.2 General Questions

Q: Is the structure similar to what you expect from the (V)HDL code

• -> yes

2.3 Questions

Q1: Counter with increase from three bits to six?

• - >You have to change the basic RTL-�le.

Q2: Clock frequency increase to 1 GHZ?

• -> change the CONSTRAINTS: in �counter.con� �rst line to:�create_clock -period 1 -name my_clock [get_ports Clock_In]�.

Q3: You have to switch to a di�erent silicon vendor?

• -> change the SETTINGS IN THE DC SETUP: maybe change the linein �.synopsys_dc.setup�: �set target_library�

4

3 Unit 2: Design Compiler Setup and Synthesis

Flow

3.1 Fazit

In this unit I leart:

• How to check a setup �le:

� libraries

� aliases

� enable line editing

• Check libraries from the GUI (Design Vision) + from the command win-dow

• How to read and link a design

• Explored a bit the GUI, which I think is quite intuitive

• how to do a basic synthesis �ow -> Q3

� constrain:how to use script .tcl �les: source file.tcl

� how to compile

� how to make an area and timing report rt & ra

� how to save a design, inclusive:

∗ to remember to use the �Save All Designs in Hierarchy� button,which will save the design hirarchy to a single .ddc �le.

� how to �nally clear up your working history, inclusive:

∗ how to use the command.log �le to redo working steps

3.2 Task 2 - Invoke Design Vision

QT2.3: What is the link/target/symbol library

• core_slow.db

• core_slow.db

• core_slow.db

3.3 Task 8 - Generating a Timing and Area Report

QT8.2: Record the following information:

• Max Delay: Largest violation (Slack): -> −0.17

• Max Area: Actual Area: -> 2255.59

5

3.4 Questions

Q1: How do you select multiple objects in Design Vision?

• -> mark them by mouse by pressing �Ctrl� on the keyboard.

Q2: What functions are available using your right mouse button?

• -> Zoom, Pan Tool, Backward, Forward, Remove from View, Edit At-tributes, Timing Path Report, Properties

Q3: Numerically order the following steps to show the basic synthesis �ow?

• G Set up library variables

• B Read in unmapped design

• D Apply a constraint script �le

• A Compile

• C Generate a constraint Report

• F Determine if the constraints are met

• E Save the mapped design

Q4: How do you optimize and map a design with Design Vision?

• -> type into command prompt: �compile�

Q5: Which Design Vision menu item saves a design?

• -> �Ctrl+s� (if �le speci�ed) or �File->Save as�

Q6: What are the bene�ts of using synthesis design �ow?

• -> you have Translation, Optimization & Mapping. I think, the mostbene�t you have from the Optimization.

Q7: What is the di�erence between �design_vision-xg� and �dc_shell-xg-t�

• -> design_vision-xg: is the command line of design vision, the graphicalinterface of the design compiler.

• -> dc_shell-xg-t: might be the shell to the design compiler.

Q8: Why should you create a �.synopsys_dc.setup' �le?

• -> To set libraries

• -> To set aliases

• -> To set other settings (eg. sh_enable_line_editing)

Q9: How do you verify the library variables are set up correctly?

• -> File->Setup, orCommand line: printvar target_library, etc.

6

Q10: How do zou �read� VHDL or Verilog code into Design Vision?

• -> File->Read

Q11: What are two optimizing goals you can set on a design?

• -> timing and area (&power) (these are more constraints I can give to thecompiler)

Q12: What is the function of the �target_Library� variable?

• -> Tells the compiler which gates from which manufacturer (speci�cations)it shall use. (basically it tells the compiler in which library it �nds thisdata.)

7

Figure 1: Before and After Re-Partitioning

4 Unit 3: Partitioning for Better Synthesis Re-

sults

4.1 Fazit

In this unit I learnt:

• Figuring out timing slack and �x them by repartitioning

• means how to �nd the critical path

� endpoint slack histogram

� use schematic view

• means how to ungroup and group blocks

4.2 Task 1 - Analyze Partitioning of PRGRM_CNT_TOP

Step 3:

• Max Delay: Largest Violation (Slack) -> −0.1172482

• Total Cell Area (Max Area): Actual Area -> 2255.596088

Step 5:

How can you improve the partitioning of this design?

• Registers at the end of every block.

• The drawing is shown in �gure 1.

4.3 Task 2 - Repartition using group and ungroup

Task Compiled Design Timing Slack Actual (Total Cell) AreaTask 1 Initial partitioning −0.172482 2255.596088Task 3 After partitioning nill 2709.760010

(group + ungroup)

8

4.4 Task 3 - Compile and Analyze Results

Step 4:

• Max Delay: Largest Violation (Slack): -> nill

• Max Area: Actual Area: -> 2709.76

Step 5:Does the critical path cross any purely combinational block?

• no

Step 7:Using the results noted in table 4.3, did repartitioning

• Improve Timing? -> yesBy how much ? -> Until there are no violations

• Improve Area? -> no

4.5 Questions

Q1: Why is it important to partition a design correctly in the source code?

• The DC can optimize just within a group. -> maybe it will not meet theconstraints

• if a group is too large, compiling takes very long time

Q2: What is the reason for not ungrouping the entire hierarchy and compilinga ��attened� design?

• The compile time can become very long. it is also good for the designerto group for the reason of keeping the overview. (p.18 chp. 4)

Q3: What are 3 synthesis bene�ts you gain from good partitioning?

• 1. Your compiling takes less time

• 2. the DC can optimize so you will meet the constraints

• 3. you may use less of the given constraints (time, area, power) and sosafe �nally money

this tells the lecture notes (chp4.22)

• 1. better results - faster and smaller designs

• 2. easier synthesis process � simpli�ed constraints and scripts

• 3. faster compiles - quicker turnaround

Q4: How do you implement partitioning in the RTL Code?

• Automatic:during synthesis by directing DC:compile -auto_ungroup area|delay(more possibilities: chp4.19)

9

• Manual:make a group: group -design_name NEW_DES -cell_name U23 U2 U3ungroup: ungroup -start_level 2 U23

Q5: List two partitioning guidelines that will help reduce compile run time.

• Achieve workable size and complexity

• Group Related combinational logic

Q6: Name one partitioning guideline that will help simplify setting constraintson a design.

• place hierarchy boundaries at register output-> e.g. Don't do glue logic

10

5 Unit 4: Introduction to DC-Tcl

5.1 Fazit

In this lab I learnt how to make a tcl script �le which compiles a design. To dothis, I �gured out a small trick:

If you don't know anymore how to write the script, use the �Design Vision�GUI to do the steps and save the command history to a �le. Now you have justto change a bit this �le, add some comments and save it as a .tcl �le.

I also learnt how to deal with long generated reports:

• page on / page o� mode

• view utility view & vrt

• in my eyes, the >> command, which forwards the output of one process tothe input of another, is also a nice solution. e.g. report_ports >> portreport.txt

5.2 Script File: runit.tcl

The �le reports/PRGRM_CNT_TOP.rpt looks like this:

****************************************

Report : constraint

-all_violators

Design : PRGRM_CNT_TOP

Version: X-2005.09-SP4

Date : Sat Mar 14 18:01:06 2009

****************************************

max_delay/setup ('Clk' group)

Required Actual

Endpoint Path Delay Path Delay Slack

-----------------------------------------------------------------

I_PRGRM_CNT/PCint_reg[0]/D

3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)


3.41 3.58 r -0.17 (VIOLATED)

11

I_PRGRM_CNT/PCint_reg[0]/E

3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)


3.32 3.48 f -0.16 (VIOLATED)

max_area

Required Actual

Design Area Area Slack

-----------------------------------------------------------------

PRGRM_CNT_TOP 2000.00 2255.59 -255.59 (VIOLATED)

5.3 Task 4 - Create and Test runit.tcl

The runti.tcl �le looks like this:

# Read the unmapped design netlist

read_file -format ddc {unmapped/PRGRM_CNT_TOP.ddc}

#or: read_ddc unmapped/PRGRM_CNT_TOP.ddc

# Set the current_design

#(Alltought this two stepps are useless, since example.tcl will do the same)

current_design PRGRM_CNT_TOP

# Perorm a link

link

# Constrain the design

source scripts/example.tcl

# Perform a default compile

compile

# Generate and save the design report

redirect -tee reports/PRGRM_CNT_TOP.rpt {report_constraint -all_violators}

# Save the mapped design

12

write -hierarchy -format ddc -output mapped/PRGRM_CNT_TOP.ddc

# Quit DC

quit

13

6 Unit 5: Apply Timing Constraints to PRGRM_CNT_TOP

6.1 Fazit


• what kind of libraries we can use and some speci�cations of ssc_core_slow

• how to apply timing constraints to a design

• how to make a .tcl scripts that executes all these commands

• and how to check them by using di�erent reports (e.g. port report)

6.2 Getting Started

Q1: From the speci�cations above, what are the input/output delays?

• InputDelay = Tclk−q = 1ns

• OutputDelay = Period− Tclk−q = 3ns

6.3 Task 2 - Examine the core_slow Library

Q2: What libraries are in DC memory?

• ssc_core_slow/gtech/standart.slbd

Q3: What is the technology library name for the target library?

• ssc_core_slow

This report is in the Appendix under chapter 12.4Q4: What is the Time Unit?

• 1ns

Q5: What is the Capacitive Load Unit

• 1pf

6.4 Task 3 - Constrain PRGRM_CNT_TOP

The .tcl �le looks like this:

# ./constraints.tcs

# Lab5-------

# Reset the desing

reset_design

# Create Clock name: my_clk, clockport: Clk

create_clock -period 4 -name my_clk [get_ports Clk]

# clock skew

set_clock_uncertainty 0.25 [get_clocks my_clk]

14

# constrain the input ports

set_input_delay 1 -max -clock my_clk [remove_from_collection [all_inputs] [get_ports Clk]]

# constrain the output ports

set_output_delay 3 -max -clock my_clk [all_outputs]

6.5 Task 4 - Check your work and Save the Results

I generated and checked the reports. The report of dc_shell-xg-t> report_port -verbose

is in the appendix in chapter 12.1.

6.6 Questions

Q6: After reading the unmapped ddc �le for PRGRM_CNT_TOP, why should youreset the design before applying design constraints?

• Since there might be older design constraints applied that wouldn't allowus to compile according to our constraints.

Q7: Why is it important to check the library time units before setting con-straints?

• -> normally, a library thinks in 1ns units, but this doesn't have to belike this: so we check it �rst. otherwise we might apply wrong timingconstraints.

Q8: Write the dc_shell-xg-t command for setting a max area goal of 500.

• dc_shell-xg-t> set_max_area 500

Q9: Which has higher priority - timing or area goals?

• timing goals

Q10: The command set_max_area places an attribute on a design. What isthe name of this attribute?

• max_area

Q11: How do you check what area goal has been placed on a design?

• report_constraints -verbose -max_area

(It took me maybe 2h to �gure this out (I tried out report_constraintsquit early, but without the verbose �ag)

15

7 Unit 6: Apply Environmental Attributes

7.1 Fazit


• what kind of wireloadmodell you can apply to a block (or the DC canchoose)

• how to read the library report

• how to apply port environment conditions on a design:set_driving_cell; set_max_capazitance; set_load

• how to report design report_design

• how to save all the constraints and attributes: write_script

• we also turned the unmapped design into a mapped one

Some of the generated reports were really long, so I put them into a separatedappendix.

7.2 To Get You Started

The library report is in 12.4Q1: Under what temperature and voltage conditions will the worst case (slow-est) operating condition occure?

• High temperature, low voltage

• generate �le: view report\_lib ssc\_core\_slow

Q2: Which operation conditions are available?

Operating Conditions:

Operating Condition Name : slow_125_1.62

Library : ssc_core_slow

Process : 1.00

Temperature : 125.00

Voltage : 1.62

Interconnect Model : balanced_tree

Operating Condition Name : slow_125_1.62_WCT


Process : 1.00


Voltage : 1.62

Interconnect Model : worst_case_tree

Q3: From the library report for the core_slow.db library �le, which wire loadmodel will be used?

• Name: AreaBasedWireLoadSelection

16

• depends on the area, by default (I found out later) it is 5KGATES

Wire Loading Model:

Name : 5KGATES

Location : ssc_core_slow

Resistance : 0.000271

Capacitance : 0.00017

Area : 0

Slope : 29.4005

Fanout Length Points Average Cap Std Deviation

--------------------------------------------------------------

1 18.38

2 47.78

3 77.18

4 106.58

5 135.98

Name : 10KGATES




Area : 0

Slope : 33.9956


--------------------------------------------------------------

1 21.25

2 55.24

3 89.24

4 123.23

5 157.23

Name : 20KGATES




Area : 0

Slope : 37.3965


--------------------------------------------------------------

1 23.37

2 60.77

3 98.17

4 135.56

5 172.96

Name : 40KGATES




17

Area : 0

Slope : 41.2229


--------------------------------------------------------------

1 25.76

2 66.99

3 108.21

4 149.43

5 190.66

Name : 80KGATES




Area : 0

Slope : 45.5129


--------------------------------------------------------------

1 28.45

2 73.96

3 119.47

4 164.98

5 210.50

Name : 160KGATES




Area : 0

Slope : 50.3104


--------------------------------------------------------------

1 31.44

2 81.75

3 132.07

4 182.38

5 232.68

Name : 320KGATES




Area : 0

Slope : 55.6653


--------------------------------------------------------------

1 34.79

2 90.46

3 146.12

4 201.79

18

5 257.45

Wire Loading Model Selection Group:

Name : AreaBasedWireLoadSelection

Selection Wire load name

min area max area

-------------------------------------------

0.00 43478.00 5KGATES

43478.00 86956.00 10KGATES

86956.00 173913.00 20KGATES

173913.00 347826.00 40KGATES

347826.00 695652.00 80KGATES

695652.00 1391304.00 160KGATES

1391304.00 2782608.00 320KGATES

Wire Loading Model Mode: enclosed

Wire Loading Model Selection Group: AreaBasedWireLoadSelection.

Q4: Name two DC commands you can use to check your work for this lab? (notperfect yet)

• > report_constraints -verbose

> report_port -verbose

> report_design

> report_wire_load

Q5: If you do not model the port environment accurately, what is likely tohappen?

• I guess the information is not transfered correctly then, e.g. if the load,the capacitance, the transition, the fanout is not set well.

7.3 Task 1 - Apply Environmental Constraints and At-tributes

Q6: What is the default operating condition?

• slow_125_1.62

The library report is in chapter 12.4Q7: How many wire load models are de�ned in core_slow.db?

• 7

Q8: What WLM would DC pick if the block had a size of 200'000?

• 40KGATES

Q9: What is the base unit for resistance in that WLM?

19

Figure 2: Attribute Report

20

• 1 kilo-ohm

The attribute report is in �gure 2Q10: What are the pin names of the cell fdef1a1?

• clk, D, E, Q

Q11: What is the max_capacitance design rule value?

• 5 and2a1 cells, pin A

The constraints look �nally like this:

# ./constraints.tcs

# Lab6-------

set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports Clk]]

set max_cap [expr [load_of ssc_core_slow/and2a1/A] * 5]

# Model the port environment

set_driving_cell -lib_cell fdef1a1 -pin Q $all_in_ex_clk

#set capacitance

set_max_capacitance $max_cap $all_in_ex_clk

#set load

set_load [expr 3 * $max_cap] [all_outputs]

7.4 Task 2 - Check Work and Save Design

• The result of report_design is in chapter 12.2

• The result of report_design -verbose is in chapter 12.3

• The result of write_script is in chapter 12.5

Q12: Did you meet timing?

• Yes!

7.5 Questions

Q13: Why would you want to model pin capacitive load on the output ports inaddition to the timing constraints?

• slide �Design Rule Constraints� says: �... you may apply more conservativedesign rules to:

� anticipate the interface environment your block will see

� prevent the design from operating cells close to their limits, whereperformance degrades rapidly.�

• my answer: I think the basic problem behind is that output capacitancee�ects the timing of a gate, therefore timing calculations can be done moreaccurate with the knowledge of the maximal capacitance allowed.

21

Q14: What 3 pieces of information can the wire load model provide?

• I see this information:

Resistance :

Capacitance :

Area :

Q15: List at least �ve dc_shell-xg-t commands that you have used in this andthe previous lab to place constraints and attributes on a design:

• I used:

# Lab5-------

reset_design

create_clock -period 4 -name my_clk [get_ports Clk]


set_input_delay 1 -max -clock my_clk

[remove_from_collection [all_inputs] [get_ports Clk]]

set_output_delay 3 -max -clock my_clk [all_outputs]

# Lab6-------

set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports Clk]]

set max_cap [expr [load_of ssc_core_slow/and2a1/A] * 5]

set_driving_cell -lib_cell fdef1a1 -pin Q $all_in_ex_clk

set_max_capacitance $max_cap $all_in_ex_clk

set_load [expr 3 * $max_cap] [all_outputs]

# Lab7-------

set ALL_INS_EX_CLK [remove_from_collection [all_inputs] [get_ports Clk]]

set_max_transition 0.25 $ALL_INS_EX_CLK

set_input_delay -min 0.2 -clock my_clk $ALL_INS_EX_CLK

set_output_delay -min -0.3 -clock my_clk [all_outputs]

22

Figure 3: Q1

8 Unit 7: Design Rules and Min Timing

8.1 Fazit

In this lab I learnt how tho set hold constraints, how to mike a setup & holdreport and how to �x some hold constraints violations.

8.2 Questions: To get You Started

Q1: see �gure 3Q2: If you do not constrain the ports accurately, what is likely to happen?

• min: new signal will arrive to early at the �, so it won't be able to holdthe old value.max: new signal will arrive to late at the �, so it won't be able to adaptit when the clk �strokes�.

8.3 Task 1 - Complete Script File

# Lab 7

set ALL_INS_EX_CLK \

[remove_from_collection [all_inputs] [get_ports Clk]]

set_max_transition 0.25 $ALL_INS_EX_CLK

set_input_delay -min 0.2 -clock my_clk $ALL_INS_EX_CLK

set_output_delay -min -0.3 -clock my_clk [all_outputs]

8.4 Task 3 - Generate Reports

For setup report, see �gure 5; for hold report, see �gure 8.

8.5 Task 4 - Fix Design Rule Violations and Hold

The report in �gure 4 was generated after the following commands:

23

Figure 4: Hold report after �xing

> set_fix_hold [all_clocks]

> compile

The hold constraints are satis�ed!

24

9 Unit 8: Timing Reports

9.1 Fazit

In this unit, I learnt how to generate and read timing reports. This includestype, violation (yes/no), where the violation occurs etc.

Commands:

dc_shell-xg-t> vrt

dc_shell-xg-t> vrt -input_pins -significant 6

dc_shell-xg-t> vrt -nets

dc_shell-xg-t> vrt -delay -min

9.2 Questions from Task 2.2

Q1: Are there any unconstrained timing paths in PRGRM_CNT_TOP? (�check_timing�)

• no

Q2: How many path groups are in PRGRM_CNT_TOP? (�report_path_group�)

• two:*default**my_clk


The report is shown in �gure 5

Q3: Is it a setup time or hold time timing report?

• It is a setup time timing report, then:The circuit of the own block needs −.74ns and the external circuit leaves0.75ns so the setup time timing is met by 0.1ns.maybe the -delay max statement in the beginning also refers to this ques-tion.

Q4: What is the start point? (input port or clk pin of internal register?)

• Report says:

I_PRGRM_CNT/PCint_reg[0]

(rising edge-triggered flip-flop clocked by my\_clk)

-> clk pin of internal register

Q5: What is the end point?

• Report says:PC[0] (output port clocked by my_clk) -> the output port

Q6: Under what operating conditions was this timing report generated?

25

Figure 5: result of dc_shell-xg-t> vrt

26

• Report says:slow_125_1.62

Q7: Did this timing path meet or violate its constraint?

• It did meet them, see also Q1,Q3

Q8: What is the clock period for CLK?

• 4ns

Q9: What is �input external delay�, and where did this number come from?

• My report just tells about �output external delay�:It is the delay that every external circuit is allowed to have maximum onits outputWe set this in Lab 5 by the following command: �set_output_delay 3-max -clock my_clk [all_outputs]�

Q10: Does the design's partitioning break a combinational path, if so explain?

• I'm not so sure about this question, but in the whole report I can't seeany statement that would support a 'yes' for this question, so I say 'no'.

Q11: What is the setup time requirement of the capture register?

• 0.74ns at the 'Q' input

Q12: What does the clock uncertainty number represent?

• Also the clock needs a certain time to propagate, so there is no guarantythat every FF receives the clock at the same time t. If there is a clockuncertainty of ∆t, a FF will receive the clock within [t...t + ∆t]. This hasto be included in setup and hold-time calculations.Here ∆t = 0.25ns



Q13: What is di�erent in this timing report from the default tining report?

• It shows 6 signi�cant digits for the timing: Wee see that the timing is notmet by 0.1ns but actually by 0.005453ns.(it also has the �ag -input_pins in the beginning)



Q14: What delay is associated with each net and why is the delay zero?

• The delay associated is just basically the time the information needs topropagate over the net. It is zero since:

� a) we didn't specify any speed of propagation

27

Figure 6: result of dc_shell-xg-t> vrt -input_pins -signi�cant 6

28

Figure 7: result of dc_shell-xg-t> vrt -nets

29

Figure 8: result of dc_shell-xg-t> vrt -delay min

� b) the wires are to short to take their time delay in account

If it is a) of b) i don't know...

Q15: What does the �Fanout� column represent?

• Fanout is the numbers of gates a device can support at its output.



Q16: Is this a setup of hold time report?

• Since we are looking at the minimum delay, it is a hold time report.And by the way, it says one line before: �Use the view utility to generatea timing report for hold.�

Q17: What is the start point?

• The report says:

30

I_PRGRM_FSM/Current_State_reg[2]\\

(rising edge-triggered flip-flop clocked by my_clk)\\

-> the clock of the FF

Q18: What is the end point?

• The report says:

Current_State[2]\\

(output port clocked by my_clk)\\

-> the output port of the circuit.

Q19: Did this timing path meet of violate its constraints?

• It is required to guaranty at the output a delay of min. 0.3ns, includingthe clock uncertainty 0.55ns. But our circuit provides from the FF to theoutput just 0.46ns delay, so the timing path constraints are violated by0.09ns.

Q20: Under what operating conditions was this report generated?

• The report says:slow_125_1.62

according the library report, this means the following:

� Operating Condition Name: slow_125_1.62

� Library: ssc_core_slow

� Process: 1.00

� Temperature: 125.00

� Voltage: 1.62

� Interconnect Model: balanced_tree

Q21: Is this an appropriate operating condition for hold time calculations?

• Honestly I don't now exactly, I also couldn't �nd anything in the scriptthat helped me to answer the question...but: I guess, if there is a �slow� model, there must also be a �fast� one...-> the timing might be evening more violated by the fast one...

Q22: What is he hold time requirement of the end point?Q23: What is the delay through the launching register?Q24: Is this delay enough to satisfy the hold time requirement?

• Q22-24 are answered in Q19.

31

10 Fazit

10.1 Lab and Report

Sometimes during the Lab I didn't understand the meaning of the questionsthat good; I answered them by the knowledge I had at this time. By writingthis �nal report, it appeared often clearer what was meant by the questions.This shows a learning process by doing this lab. I also wasn't sometime thatsure where in the �design �ow� I am at the moment and what I'm doing rightnow etc. Also according to this I see more clearer now by writing the �nalreport.

So there is a learning e�ect in the following areas:

• Better understanding of the synthesis

• Better understanding of the Design Compiler Software

� How to apply constraints

� How to generate and interpret reports

But to get the complete understanding of the content of the lab-tasks I wouldneed more time spending with the software. For example, I'm still not that surewhich report command is the appropriate for every situation.

Also to completely structurized this report would take more time, since asmentioned in the introduction, the content is produced over a eight weeks period.Beside that I didn't follow always the same layout, I also was at di�erent statesof understanding Design Compiler. But although not perfectly structurized, Ithink that this report �reports� what I have done and learnt during the lab.

32

11 Aditional

11.1 How to do Remote Access

Since I made parts of the lab directly from my home computer, I would like togive a short description how to do this (from a Windows OS):

• First you need a NUS IP address. If you're not on campus, use VPN.

• Then you need to setup a ssh connection to a cadcam computer, e.g bythe software 'Putty'.

Host Name: 'numberofcomputer'.cadcam.nus.edu.sg

numberofcomputer e.g. lxb16

Port: 22

• Login by your account.

• if you want to work �graphically�, you can use for example the vnc tech-nology1:

� On the cadcam computer, start a vnc server:

vncserver :numberbetween1and100

� the �st time you run this server, you have to set a password

� On your computer, run a vnc client, e.g. 'vncviewer'.

� login by the following data:

Adress of the server:

'numberofcomputer'.cadcam.nus.edu.sg:numberbetween1and100

Password: the password you have set for the server

� if you want to run on the remote computer the gnome GUI per de-fault, go to your '.vnc' directory, search there the �le 'xstartup' andmake there the following changes:

in .vnc/xstartup:

...

#twm &

gnome-session &

...

• How to stop the vnc server:

� You stop the vnc server by entering:

vncserver -kill :numberbetween1and100

� afterwards you can logout from the remote computer

logout

� But if you just logout without stopping the vnc-server, it keeps onrunning. This can by a useful feature, e.g. if you have to do somesimulation etc.

This is just a basic approach, maybe there are better techniques.

1http://en.wikipedia.org/wiki/Virtual_Network_Computing

33

12 Appendix

12.1 Lab5 Task4 16a

****************************************

Report : port

-verbose



Date : Fri Mar 13 15:47:33 2009

****************************************

Pin Wire Max Max Connection

Port Dir Load Load Trans Cap Class Attrs

--------------------------------------------------------------------------------

Carry_Flag in 0.0000 0.0000 -- -- --

Clk in 0.0000 0.0000 -- -- --

Crnt_Instrn[0] in 0.0000 0.0000 -- -- --

Crnt_Instrn[1] in 0.0000 0.0000 -- -- --

Crnt_Instrn[2] in 0.0000 0.0000 -- -- --

Crnt_Instrn[3] in 0.0000 0.0000 -- -- --

Crnt_Instrn[4] in 0.0000 0.0000 -- -- --

Crnt_Instrn[5] in 0.0000 0.0000 -- -- --

Crnt_Instrn[6] in 0.0000 0.0000 -- -- --

Crnt_Instrn[7] in 0.0000 0.0000 -- -- --

Crnt_Instrn[8] in 0.0000 0.0000 -- -- --

Crnt_Instrn[9] in 0.0000 0.0000 -- -- --

Crnt_Instrn[10]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[11]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[12]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[13]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[14]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[15]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[16]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[17]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[18]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[19]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[20]

in 0.0000 0.0000 -- -- --

34

Crnt_Instrn[21]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[22]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[23]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[24]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[25]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[26]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[27]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[28]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[29]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[30]

in 0.0000 0.0000 -- -- --

Crnt_Instrn[31]

in 0.0000 0.0000 -- -- --

Neg_Flag in 0.0000 0.0000 -- -- --

Reset in 0.0000 0.0000 -- -- --

Return_Addr[0] in 0.0000 0.0000 -- -- --

Return_Addr[1] in 0.0000 0.0000 -- -- --

Return_Addr[2] in 0.0000 0.0000 -- -- --

Return_Addr[3] in 0.0000 0.0000 -- -- --

Return_Addr[4] in 0.0000 0.0000 -- -- --

Return_Addr[5] in 0.0000 0.0000 -- -- --

Return_Addr[6] in 0.0000 0.0000 -- -- --

Return_Addr[7] in 0.0000 0.0000 -- -- --

Zro_Flag in 0.0000 0.0000 -- -- --

Current_State[0]

out 0.0000 0.0000 -- -- --

Current_State[1]

out 0.0000 0.0000 -- -- --

Current_State[2]

out 0.0000 0.0000 -- -- --

PC[0] out 0.0000 0.0000 -- -- --

PC[1] out 0.0000 0.0000 -- -- --

PC[2] out 0.0000 0.0000 -- -- --

PC[3] out 0.0000 0.0000 -- -- --

PC[4] out 0.0000 0.0000 -- -- --

PC[5] out 0.0000 0.0000 -- -- --

PC[6] out 0.0000 0.0000 -- -- --

PC[7] out 0.0000 0.0000 -- -- --

External Max Min Min Min

35

Number Wireload Wireload Pin Wire

Port Points Model Model Load Load

--------------------------------------------------------------------------------

Carry_Flag 1 -- -- -- --

Clk 1 -- -- -- --

Crnt_Instrn[0]

1 -- -- -- --

Crnt_Instrn[1]

1 -- -- -- --

Crnt_Instrn[2]

1 -- -- -- --

Crnt_Instrn[3]

1 -- -- -- --

Crnt_Instrn[4]

1 -- -- -- --

Crnt_Instrn[5]

1 -- -- -- --

Crnt_Instrn[6]

1 -- -- -- --

Crnt_Instrn[7]

1 -- -- -- --

Crnt_Instrn[8]

1 -- -- -- --

Crnt_Instrn[9]

1 -- -- -- --

Crnt_Instrn[10]

1 -- -- -- --

Crnt_Instrn[11]

1 -- -- -- --

Crnt_Instrn[12]

1 -- -- -- --

Crnt_Instrn[13]

1 -- -- -- --

Crnt_Instrn[14]

1 -- -- -- --

Crnt_Instrn[15]

1 -- -- -- --

Crnt_Instrn[16]

1 -- -- -- --

Crnt_Instrn[17]

1 -- -- -- --

Crnt_Instrn[18]

1 -- -- -- --

Crnt_Instrn[19]

1 -- -- -- --

Crnt_Instrn[20]

1 -- -- -- --

Crnt_Instrn[21]

1 -- -- -- --

Crnt_Instrn[22]

36

1 -- -- -- --

Crnt_Instrn[23]

1 -- -- -- --

Crnt_Instrn[24]

1 -- -- -- --

Crnt_Instrn[25]

1 -- -- -- --

Crnt_Instrn[26]

1 -- -- -- --

Crnt_Instrn[27]

1 -- -- -- --

Crnt_Instrn[28]

1 -- -- -- --

Crnt_Instrn[29]

1 -- -- -- --

Crnt_Instrn[30]

1 -- -- -- --

Crnt_Instrn[31]

1 -- -- -- --

Neg_Flag 1 -- -- -- --

Reset 1 -- -- -- --

Return_Addr[0]

1 -- -- -- --

Return_Addr[1]

1 -- -- -- --

Return_Addr[2]

1 -- -- -- --

Return_Addr[3]

1 -- -- -- --

Return_Addr[4]

1 -- -- -- --

Return_Addr[5]

1 -- -- -- --

Return_Addr[6]

1 -- -- -- --

Return_Addr[7]

1 -- -- -- --

Zro_Flag 1 -- -- -- --

Current_State[0]

1 -- -- -- --

Current_State[1]

1 -- -- -- --

Current_State[2]

1 -- -- -- --

PC[0] 1 -- -- -- --

PC[1] 1 -- -- -- --

PC[2] 1 -- -- -- --

PC[3] 1 -- -- -- --

PC[4] 1 -- -- -- --

PC[5] 1 -- -- -- --

37

PC[6] 1 -- -- -- --

PC[7] 1 -- -- -- --

Input Delay

Min Max Related Max

Input Port Rise Fall Rise Fall Clock Fanout

--------------------------------------------------------------------------------

Carry_Flag -- -- 1.00 1.00 my_clk --

Clk -- -- -- -- -- --

Crnt_Instrn[0]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[1]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[2]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[3]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[4]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[5]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[6]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[7]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[8]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[9]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[10]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[11]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[12]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[13]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[14]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[15]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[16]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[17]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[18]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[19]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[20]

38

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[21]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[22]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[23]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[24]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[25]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[26]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[27]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[28]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[29]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[30]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[31]

-- -- 1.00 1.00 my_clk --

Neg_Flag -- -- 1.00 1.00 my_clk --

Reset -- -- 1.00 1.00 my_clk --

Return_Addr[0]

-- -- 1.00 1.00 my_clk --

Return_Addr[1]

-- -- 1.00 1.00 my_clk --

Return_Addr[2]

-- -- 1.00 1.00 my_clk --

Return_Addr[3]

-- -- 1.00 1.00 my_clk --

Return_Addr[4]

-- -- 1.00 1.00 my_clk --

Return_Addr[5]

-- -- 1.00 1.00 my_clk --

Return_Addr[6]

-- -- 1.00 1.00 my_clk --

Return_Addr[7]

-- -- 1.00 1.00 my_clk --

Zro_Flag -- -- 1.00 1.00 my_clk --

Max Drive Min Drive Resistance Min Min Cell

Input Port Rise Fall Rise Fall Max Min Cap Fanout Deg

--------------------------------------------------------------------------------

Carry_Flag -- -- -- -- -- -- -- -- --

Clk -- -- -- -- -- -- -- -- --

Crnt_Instrn[0]

39

-- -- -- -- -- -- -- -- --

Crnt_Instrn[1]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[2]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[3]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[4]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[5]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[6]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[7]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[8]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[9]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[10]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[11]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[12]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[13]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[14]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[15]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[16]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[17]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[18]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[19]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[20]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[21]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[22]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[23]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[24]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[25]

40

-- -- -- -- -- -- -- -- --

Crnt_Instrn[26]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[27]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[28]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[29]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[30]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[31]

-- -- -- -- -- -- -- -- --

Neg_Flag -- -- -- -- -- -- -- -- --

Reset -- -- -- -- -- -- -- -- --

Return_Addr[0]

-- -- -- -- -- -- -- -- --

Return_Addr[1]

-- -- -- -- -- -- -- -- --

Return_Addr[2]

-- -- -- -- -- -- -- -- --

Return_Addr[3]

-- -- -- -- -- -- -- -- --

Return_Addr[4]

-- -- -- -- -- -- -- -- --

Return_Addr[5]

-- -- -- -- -- -- -- -- --

Return_Addr[6]

-- -- -- -- -- -- -- -- --

Return_Addr[7]

-- -- -- -- -- -- -- -- --

Zro_Flag -- -- -- -- -- -- -- -- --

Max Tran Min Tran

Input Port Rise Fall Rise Fall

--------------------------------------------------------------------------------

Carry_Flag -- -- -- --

Clk -- -- -- --

Crnt_Instrn[0]

-- -- -- --

Crnt_Instrn[1]

-- -- -- --

Crnt_Instrn[2]

-- -- -- --

Crnt_Instrn[3]

-- -- -- --

Crnt_Instrn[4]

-- -- -- --

Crnt_Instrn[5]

41

-- -- -- --

Crnt_Instrn[6]

-- -- -- --

Crnt_Instrn[7]

-- -- -- --

Crnt_Instrn[8]

-- -- -- --

Crnt_Instrn[9]

-- -- -- --

Crnt_Instrn[10]

-- -- -- --

Crnt_Instrn[11]

-- -- -- --

Crnt_Instrn[12]

-- -- -- --

Crnt_Instrn[13]

-- -- -- --

Crnt_Instrn[14]

-- -- -- --

Crnt_Instrn[15]

-- -- -- --

Crnt_Instrn[16]

-- -- -- --

Crnt_Instrn[17]

-- -- -- --

Crnt_Instrn[18]

-- -- -- --

Crnt_Instrn[19]

-- -- -- --

Crnt_Instrn[20]

-- -- -- --

Crnt_Instrn[21]

-- -- -- --

Crnt_Instrn[22]

-- -- -- --

Crnt_Instrn[23]

-- -- -- --

Crnt_Instrn[24]

-- -- -- --

Crnt_Instrn[25]

-- -- -- --

Crnt_Instrn[26]

-- -- -- --

Crnt_Instrn[27]

-- -- -- --

Crnt_Instrn[28]

-- -- -- --

Crnt_Instrn[29]

-- -- -- --

Crnt_Instrn[30]

42

-- -- -- --

Crnt_Instrn[31]

-- -- -- --

Neg_Flag -- -- -- --

Reset -- -- -- --

Return_Addr[0]

-- -- -- --

Return_Addr[1]

-- -- -- --

Return_Addr[2]

-- -- -- --

Return_Addr[3]

-- -- -- --

Return_Addr[4]

-- -- -- --

Return_Addr[5]

-- -- -- --

Return_Addr[6]

-- -- -- --

Return_Addr[7]

-- -- -- --

Zro_Flag -- -- -- --

Output Delay

Min Max Related Fanout

Output Port Rise Fall Rise Fall Clock Load

--------------------------------------------------------------------------------

Current_State[0]

-- -- 3.00 3.00 my_clk 0.00

Current_State[1]

-- -- 3.00 3.00 my_clk 0.00

Current_State[2]

-- -- 3.00 3.00 my_clk 0.00

PC[0] -- -- 3.00 3.00 my_clk 0.00

PC[1] -- -- 3.00 3.00 my_clk 0.00

PC[2] -- -- 3.00 3.00 my_clk 0.00

PC[3] -- -- 3.00 3.00 my_clk 0.00

PC[4] -- -- 3.00 3.00 my_clk 0.00

PC[5] -- -- 3.00 3.00 my_clk 0.00

PC[6] -- -- 3.00 3.00 my_clk 0.00

PC[7] -- -- 3.00 3.00 my_clk 0.00

12.2 Lab6 Task2 Report

****************************************

Report : port



Date : Sat Apr 18 17:22:38 2009

43

****************************************



--------------------------------------------------------------------------------

Carry_Flag in 0.0000 0.0000 0.98 0.01 --

Clk in 0.0000 0.0000 -- -- --

Crnt_Instrn[0] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[1] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[2] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[3] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[4] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[5] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[6] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[7] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[8] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[9] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[10]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[11]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[12]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[13]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[14]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[15]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[16]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[17]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[18]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[19]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[20]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[21]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[22]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[23]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[24]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[25]

in 0.0000 0.0000 0.98 0.01 --

44

Crnt_Instrn[26]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[27]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[28]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[29]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[30]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[31]

in 0.0000 0.0000 0.98 0.01 --

Neg_Flag in 0.0000 0.0000 0.98 0.01 --

Reset in 0.0000 0.0000 0.98 0.01 --

Return_Addr[0] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[1] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[2] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[3] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[4] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[5] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[6] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[7] in 0.0000 0.0000 0.98 0.01 --

Zro_Flag in 0.0000 0.0000 0.98 0.01 --

Current_State[0]

out 0.0300 0.0000 -- -- --

Current_State[1]

out 0.0300 0.0000 -- -- --

Current_State[2]

out 0.0300 0.0000 -- -- --

PC[0] out 0.0300 0.0000 -- -- --

PC[1] out 0.0300 0.0000 -- -- --

PC[2] out 0.0300 0.0000 -- -- --

PC[3] out 0.0300 0.0000 -- -- --

PC[4] out 0.0300 0.0000 -- -- --

PC[5] out 0.0300 0.0000 -- -- --

PC[6] out 0.0300 0.0000 -- -- --

PC[7] out 0.0300 0.0000 -- -- --

12.3 Lab6 Task2 Report2

****************************************

Report : port

-verbose



Date : Sat Apr 18 17:23:16 2009

****************************************


45


--------------------------------------------------------------------------------

Carry_Flag in 0.0000 0.0000 0.98 0.01 --

Clk in 0.0000 0.0000 -- -- --

Crnt_Instrn[0] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[1] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[2] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[3] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[4] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[5] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[6] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[7] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[8] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[9] in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[10]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[11]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[12]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[13]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[14]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[15]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[16]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[17]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[18]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[19]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[20]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[21]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[22]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[23]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[24]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[25]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[26]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[27]

in 0.0000 0.0000 0.98 0.01 --

46

Crnt_Instrn[28]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[29]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[30]

in 0.0000 0.0000 0.98 0.01 --

Crnt_Instrn[31]

in 0.0000 0.0000 0.98 0.01 --

Neg_Flag in 0.0000 0.0000 0.98 0.01 --

Reset in 0.0000 0.0000 0.98 0.01 --

Return_Addr[0] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[1] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[2] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[3] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[4] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[5] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[6] in 0.0000 0.0000 0.98 0.01 --

Return_Addr[7] in 0.0000 0.0000 0.98 0.01 --

Zro_Flag in 0.0000 0.0000 0.98 0.01 --

Current_State[0]

out 0.0300 0.0000 -- -- --

Current_State[1]

out 0.0300 0.0000 -- -- --

Current_State[2]

out 0.0300 0.0000 -- -- --

PC[0] out 0.0300 0.0000 -- -- --

PC[1] out 0.0300 0.0000 -- -- --

PC[2] out 0.0300 0.0000 -- -- --

PC[3] out 0.0300 0.0000 -- -- --

PC[4] out 0.0300 0.0000 -- -- --

PC[5] out 0.0300 0.0000 -- -- --

PC[6] out 0.0300 0.0000 -- -- --

PC[7] out 0.0300 0.0000 -- -- --

External Max Min Min Min

Number Wireload Wireload Pin Wire

Port Points Model Model Load Load

--------------------------------------------------------------------------------

Carry_Flag 1 -- -- -- --

Clk 1 -- -- -- --

Crnt_Instrn[0]

1 -- -- -- --

Crnt_Instrn[1]

1 -- -- -- --

Crnt_Instrn[2]

1 -- -- -- --

Crnt_Instrn[3]

1 -- -- -- --

Crnt_Instrn[4]

47

1 -- -- -- --

Crnt_Instrn[5]

1 -- -- -- --

Crnt_Instrn[6]

1 -- -- -- --

Crnt_Instrn[7]

1 -- -- -- --

Crnt_Instrn[8]

1 -- -- -- --

Crnt_Instrn[9]

1 -- -- -- --

Crnt_Instrn[10]

1 -- -- -- --

Crnt_Instrn[11]

1 -- -- -- --

Crnt_Instrn[12]

1 -- -- -- --

Crnt_Instrn[13]

1 -- -- -- --

Crnt_Instrn[14]

1 -- -- -- --

Crnt_Instrn[15]

1 -- -- -- --

Crnt_Instrn[16]

1 -- -- -- --

Crnt_Instrn[17]

1 -- -- -- --

Crnt_Instrn[18]

1 -- -- -- --

Crnt_Instrn[19]

1 -- -- -- --

Crnt_Instrn[20]

1 -- -- -- --

Crnt_Instrn[21]

1 -- -- -- --

Crnt_Instrn[22]

1 -- -- -- --

Crnt_Instrn[23]

1 -- -- -- --

Crnt_Instrn[24]

1 -- -- -- --

Crnt_Instrn[25]

1 -- -- -- --

Crnt_Instrn[26]

1 -- -- -- --

Crnt_Instrn[27]

1 -- -- -- --

Crnt_Instrn[28]

1 -- -- -- --

Crnt_Instrn[29]

48

1 -- -- -- --

Crnt_Instrn[30]

1 -- -- -- --

Crnt_Instrn[31]

1 -- -- -- --

Neg_Flag 1 -- -- -- --

Reset 1 -- -- -- --

Return_Addr[0]

1 -- -- -- --

Return_Addr[1]

1 -- -- -- --

Return_Addr[2]

1 -- -- -- --

Return_Addr[3]

1 -- -- -- --

Return_Addr[4]

1 -- -- -- --

Return_Addr[5]

1 -- -- -- --

Return_Addr[6]

1 -- -- -- --

Return_Addr[7]

1 -- -- -- --

Zro_Flag 1 -- -- -- --

Current_State[0]

1 -- -- -- --

Current_State[1]

1 -- -- -- --

Current_State[2]

1 -- -- -- --

PC[0] 1 -- -- -- --

PC[1] 1 -- -- -- --

PC[2] 1 -- -- -- --

PC[3] 1 -- -- -- --

PC[4] 1 -- -- -- --

PC[5] 1 -- -- -- --

PC[6] 1 -- -- -- --

PC[7] 1 -- -- -- --

Input Delay

Min Max Related Max

Input Port Rise Fall Rise Fall Clock Fanout

--------------------------------------------------------------------------------

Carry_Flag -- -- 1.00 1.00 my_clk --

Clk -- -- -- -- -- --

Crnt_Instrn[0]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[1]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[2]

49

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[3]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[4]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[5]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[6]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[7]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[8]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[9]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[10]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[11]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[12]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[13]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[14]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[15]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[16]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[17]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[18]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[19]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[20]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[21]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[22]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[23]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[24]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[25]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[26]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[27]

50

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[28]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[29]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[30]

-- -- 1.00 1.00 my_clk --

Crnt_Instrn[31]

-- -- 1.00 1.00 my_clk --

Neg_Flag -- -- 1.00 1.00 my_clk --

Reset -- -- 1.00 1.00 my_clk --

Return_Addr[0]

-- -- 1.00 1.00 my_clk --

Return_Addr[1]

-- -- 1.00 1.00 my_clk --

Return_Addr[2]

-- -- 1.00 1.00 my_clk --

Return_Addr[3]

-- -- 1.00 1.00 my_clk --

Return_Addr[4]

-- -- 1.00 1.00 my_clk --

Return_Addr[5]

-- -- 1.00 1.00 my_clk --

Return_Addr[6]

-- -- 1.00 1.00 my_clk --

Return_Addr[7]

-- -- 1.00 1.00 my_clk --

Zro_Flag -- -- 1.00 1.00 my_clk --

Driving Cell

Input Port Rise Fall Mult Attrs

--------------------------------------------------------------------------------

Carry_Flag fdef1a1/Q fdef1a1/Q --

Crnt_Instrn[0]

fdef1a1/Q fdef1a1/Q --

Crnt_Instrn[1]


Crnt_Instrn[2]


Crnt_Instrn[3]


Crnt_Instrn[4]


Crnt_Instrn[5]


Crnt_Instrn[6]


Crnt_Instrn[7]


51

Crnt_Instrn[8]


Crnt_Instrn[9]


Crnt_Instrn[10]


Crnt_Instrn[11]


Crnt_Instrn[12]


Crnt_Instrn[13]


Crnt_Instrn[14]


Crnt_Instrn[15]


Crnt_Instrn[16]


Crnt_Instrn[17]


Crnt_Instrn[18]


Crnt_Instrn[19]


Crnt_Instrn[20]


Crnt_Instrn[21]


Crnt_Instrn[22]


Crnt_Instrn[23]


Crnt_Instrn[24]


Crnt_Instrn[25]


Crnt_Instrn[26]


Crnt_Instrn[27]


Crnt_Instrn[28]


Crnt_Instrn[29]


Crnt_Instrn[30]


Crnt_Instrn[31]


Neg_Flag fdef1a1/Q fdef1a1/Q --

Reset fdef1a1/Q fdef1a1/Q --

52

Return_Addr[0]


Return_Addr[1]


Return_Addr[2]


Return_Addr[3]


Return_Addr[4]


Return_Addr[5]


Return_Addr[6]


Return_Addr[7]


Zro_Flag fdef1a1/Q fdef1a1/Q --

Max Drive Min Drive Resistance Min Min Cell

Input Port Rise Fall Rise Fall Max Min Cap Fanout Deg

--------------------------------------------------------------------------------

Carry_Flag -- -- -- -- -- -- -- -- --

Clk -- -- -- -- -- -- -- -- --

Crnt_Instrn[0]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[1]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[2]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[3]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[4]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[5]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[6]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[7]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[8]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[9]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[10]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[11]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[12]

-- -- -- -- -- -- -- -- --

53

Crnt_Instrn[13]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[14]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[15]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[16]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[17]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[18]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[19]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[20]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[21]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[22]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[23]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[24]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[25]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[26]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[27]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[28]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[29]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[30]

-- -- -- -- -- -- -- -- --

Crnt_Instrn[31]

-- -- -- -- -- -- -- -- --

Neg_Flag -- -- -- -- -- -- -- -- --

Reset -- -- -- -- -- -- -- -- --

Return_Addr[0]

-- -- -- -- -- -- -- -- --

Return_Addr[1]

-- -- -- -- -- -- -- -- --

Return_Addr[2]

-- -- -- -- -- -- -- -- --

Return_Addr[3]

-- -- -- -- -- -- -- -- --

Return_Addr[4]

-- -- -- -- -- -- -- -- --

54

Return_Addr[5]

-- -- -- -- -- -- -- -- --

Return_Addr[6]

-- -- -- -- -- -- -- -- --

Return_Addr[7]

-- -- -- -- -- -- -- -- --

Zro_Flag -- -- -- -- -- -- -- -- --

Max Tran Min Tran

Input Port Rise Fall Rise Fall

--------------------------------------------------------------------------------

Carry_Flag -- -- -- --

Clk -- -- -- --

Crnt_Instrn[0]

-- -- -- --

Crnt_Instrn[1]

-- -- -- --

Crnt_Instrn[2]

-- -- -- --

Crnt_Instrn[3]

-- -- -- --

Crnt_Instrn[4]

-- -- -- --

Crnt_Instrn[5]

-- -- -- --

Crnt_Instrn[6]

-- -- -- --

Crnt_Instrn[7]

-- -- -- --

Crnt_Instrn[8]

-- -- -- --

Crnt_Instrn[9]

-- -- -- --

Crnt_Instrn[10]

-- -- -- --

Crnt_Instrn[11]

-- -- -- --

Crnt_Instrn[12]

-- -- -- --

Crnt_Instrn[13]

-- -- -- --

Crnt_Instrn[14]

-- -- -- --

Crnt_Instrn[15]

-- -- -- --

Crnt_Instrn[16]

-- -- -- --

Crnt_Instrn[17]

-- -- -- --

55

Crnt_Instrn[18]

-- -- -- --

Crnt_Instrn[19]

-- -- -- --

Crnt_Instrn[20]

-- -- -- --

Crnt_Instrn[21]

-- -- -- --

Crnt_Instrn[22]

-- -- -- --

Crnt_Instrn[23]

-- -- -- --

Crnt_Instrn[24]

-- -- -- --

Crnt_Instrn[25]

-- -- -- --

Crnt_Instrn[26]

-- -- -- --

Crnt_Instrn[27]

-- -- -- --

Crnt_Instrn[28]

-- -- -- --

Crnt_Instrn[29]

-- -- -- --

Crnt_Instrn[30]

-- -- -- --

Crnt_Instrn[31]

-- -- -- --

Neg_Flag -- -- -- --

Reset -- -- -- --

Return_Addr[0]

-- -- -- --

Return_Addr[1]

-- -- -- --

Return_Addr[2]

-- -- -- --

Return_Addr[3]

-- -- -- --

Return_Addr[4]

-- -- -- --

Return_Addr[5]

-- -- -- --

Return_Addr[6]

-- -- -- --

Return_Addr[7]

-- -- -- --

Zro_Flag -- -- -- --

Output Delay

56

Min Max Related Fanout

Output Port Rise Fall Rise Fall Clock Load

--------------------------------------------------------------------------------

Current_State[0]

-- -- 3.00 3.00 my_clk 0.00

Current_State[1]

-- -- 3.00 3.00 my_clk 0.00

Current_State[2]

-- -- 3.00 3.00 my_clk 0.00

PC[0] -- -- 3.00 3.00 my_clk 0.00

PC[1] -- -- 3.00 3.00 my_clk 0.00

PC[2] -- -- 3.00 3.00 my_clk 0.00

PC[3] -- -- 3.00 3.00 my_clk 0.00

PC[4] -- -- 3.00 3.00 my_clk 0.00

PC[5] -- -- 3.00 3.00 my_clk 0.00

PC[6] -- -- 3.00 3.00 my_clk 0.00

PC[7] -- -- 3.00 3.00 my_clk 0.00

12.4 Lab6 Report Library

****************************************

Report : library

Library: ssc_core_slow


Date : Sat Mar 21 16:50:38 2009

****************************************

Library Type : Technology

Tool Created : 2000.11-SP1

Date Created : May 22 2000 10:44:10

Library Version : SC_SCB971_strap

Comments : Operating condition (125.00 C, 1.62 V, slow)

Time Unit : 1ns

Capacitive Load Unit : 1.000000pf

Pulling Resistance Unit : 1kilo-ohm

Voltage Unit : 1V

Current Unit : 1mA

Dynamic Energy Unit : 1.000000pJ (derived from V,C units)

Leakage Power Unit : Not specified.

Bus Naming Style : %s[%d] (default)

Operating Conditions:

Operating Condition Name : slow_125_1.62


Process : 1.00


Voltage : 1.62

57

Interconnect Model : balanced_tree

Operating Condition Name : slow_125_1.62_WCT


Process : 1.00


Voltage : 1.62

Interconnect Model : worst_case_tree

Input Voltages:

No input_voltage groups specified.

Output Voltages:

No output_voltage groups specified.

default_wire_load_capacitance: 0.000170

default_wire_load_resistance: 0.000271

Wire Loading Model:

Name : 5KGATES




Area : 0

Slope : 29.4005


--------------------------------------------------------------

1 18.38

2 47.78

3 77.18

4 106.58

5 135.98

Name : 10KGATES




Area : 0

Slope : 33.9956


--------------------------------------------------------------

1 21.25

2 55.24

3 89.24

4 123.23

5 157.23

58

Name : 20KGATES




Area : 0

Slope : 37.3965


--------------------------------------------------------------

1 23.37

2 60.77

3 98.17

4 135.56

5 172.96

Name : 40KGATES




Area : 0

Slope : 41.2229


--------------------------------------------------------------

1 25.76

2 66.99

3 108.21

4 149.43

5 190.66

Name : 80KGATES




Area : 0

Slope : 45.5129


--------------------------------------------------------------

1 28.45

2 73.96

3 119.47

4 164.98

5 210.50

Name : 160KGATES




Area : 0

Slope : 50.3104


59

--------------------------------------------------------------

1 31.44

2 81.75

3 132.07

4 182.38

5 232.68

Name : 320KGATES




Area : 0

Slope : 55.6653


--------------------------------------------------------------

1 34.79

2 90.46

3 146.12

4 201.79

5 257.45

Wire Loading Model Selection Group:

Name : AreaBasedWireLoadSelection

Selection Wire load name

min area max area

-------------------------------------------

0.00 43478.00 5KGATES

43478.00 86956.00 10KGATES

86956.00 173913.00 20KGATES

173913.00 347826.00 40KGATES

347826.00 695652.00 80KGATES

695652.00 1391304.00 160KGATES

1391304.00 2782608.00 320KGATES

Wire Loading Model Mode: enclosed.

Wire Loading Model Selection Group: AreaBasedWireLoadSelection.

Porosity information:

No porosity information specified.

Default Connection Class: default

In_place optimization mode: match_footprint

60

Timing Ranges:

No timing ranges specified.

Delay Threshold Trip-Points:

input_threshold_pct_rise: 50

output_threshold_pct_rise: 50

input_threshold_pct_fall: 50

output_threshold_pct_fall: 50

Slew Threshold Trip-Points:

slew_lower_threshold_pct_rise: 10

slew_upper_threshold_pct_rise: 90

slew_lower_threshold_pct_fall: 10

slew_upper_threshold_pct_fall: 90

slew_derate_from_library: 1

Components:

Attributes:

af - active falling

ah - active high

al - active low

ar - active rising

b - black box (function unknown)

ce - clock enable

cg - clock gating integrated cell

ctl - has CTL test model

d - dont_touch

iso - isolation cell

ls - level shifter

mo - map_only

p - preferred

pwrg - power gating cell

r - removable

s - statetable

sa0 - dont_fault stuck-at-0

sa1 - dont_fault stuck-at-1

sa01 - dont_fault both stuck-at-0 and stuck-at-1

sz - use_for_size_only

t - test cell. t(scan_type) as

t(mux_ff) - muxed flip-flop

t(mux_ld) - muxed latch

61

t(clk_scan) - clocked scan

t(clk_scan_ld) - clocked scan latch

t(lssd_dld) - double latch LSSD

t(lssd_sld) - single latch LSSD

t(lssd_clk) - clocked LSSD

t(lssd_auxclk) - auxiliary clock LSSD

u - dont_use

udp - usable for datapath generators

ufc - user_function_class. ufc(type) as

ufc(u) - user-defined

ufc(a) - automatically generated

Cell Footprint Attributes

-------------------------------------------

and2a1 "fp_2800_4480"

and2a2 "fp_2800_4480"

and2a3 "fp_2800_4480"

and2a6 "fp_3920_4480"

and2a9 "fp_4480_4480"

and2a15 "fp_7280_4480"

and2b1 "fp_2800_4480"

and2b2 "fp_2800_4480"

and2b3 "fp_3920_4480"

and2b6 "fp_4480_4480"

and2b9 "fp_6720_4480"

and2b15 "fp_8400_4480"

and2c1 "fp_1680_4480"

and2c2 "fp_2240_4480"

and2c3 "fp_2240_4480"

and2c6 "fp_3920_4480"

and2c9 "fp_5600_4480"

and2c15 "fp_8400_4480"

and3a1 "fp_3360_4480"

and3a2 "fp_3360_4480"

and3a3 "fp_3920_4480"

and3a6 "fp_4480_4480"

and3a9 "fp_5040_4480"

and3a15 "fp_8400_4480"

and3b1 "fp_5040_4480"

and3b2 "fp_5040_4480"

and3b3 "fp_5040_4480"

and3b6 "fp_5040_4480"

and3b9 "fp_6160_4480"

and3b15 "fp_9520_4480"

and3c1 "fp_3360_4480"

and3c2 "fp_3920_4480"

and3c3 "fp_5600_4480"

and3c6 "fp_6160_4480"

and3c9 "fp_7280_4480"

and3c15 "fp_9520_4480"

62

and3d1 "fp_2800_4480"

and3d2 "fp_2800_4480"

and3d3 "fp_3360_4480"

and3d6 "fp_5600_4480"

and3d9 "fp_7840_4480"

and3d15 "fp_11760_4480"

and4a3 "fp_5600_4480"

and4a6 "fp_6720_4480"

and4a9 "fp_8960_4480"

and4a15 "fp_11200_4480"

and4e3 "fp_6160_4480"

and4e6 "fp_7280_4480"

and4e9 "fp_7840_4480"

and4e15 "fp_11200_4480"

and6a3 "fp_6720_4480"

and6a6 "fp_7840_4480"

and6a9 "fp_10080_4480"

and6a15 "fp_11760_4480"

ao1a1 "fp_4480_4480"

ao1a2 "fp_4480_4480"

ao1a3 "fp_4480_4480"

ao1a6 "fp_5040_4480"

ao1a9 "fp_5600_4480"

ao1a15 "fp_9520_4480"

ao1b1 "fp_5040_4480"

ao1b2 "fp_5040_4480"

ao1b3 "fp_5040_4480"

ao1b6 "fp_5600_4480"

ao1b9 "fp_6720_4480"

ao1b15 "fp_10080_4480"

ao1c1 "fp_4480_4480"

ao1c2 "fp_4480_4480"

ao1c3 "fp_4480_4480"

ao1c6 "fp_6720_4480"

ao1c9 "fp_6720_4480"

ao1c15 "fp_7840_4480"

ao1d1 "fp_3360_4480"

ao1d2 "fp_3360_4480"

ao1d3 "fp_3920_4480"

ao1d6 "fp_5040_4480"

ao1d9 "fp_6160_4480"

ao1d15 "fp_10080_4480"

ao1e1 "fp_4480_4480"

ao1e2 "fp_4480_4480"

ao1e3 "fp_4480_4480"

ao1e6 "fp_6720_4480"

ao1e9 "fp_6720_4480"

ao1e15 "fp_7840_4480"

ao1f1 "fp_2800_4480"

ao1f2 "fp_2800_4480"

63

ao1f3 "fp_3360_4480"

ao1f6 "fp_5600_4480"

ao1f9 "fp_5600_4480"

ao1f15 "fp_6720_4480"

ao2a1 "fp_4480_4480"

ao2a2 "fp_4480_4480"

ao2a3 "fp_5040_4480"

ao2a6 "fp_5600_4480"

ao2a9 "fp_7840_4480"

ao2a15 "fp_10080_4480"

ao2e1 "fp_5600_4480"

ao2e2 "fp_5600_4480"

ao2e3 "fp_5600_4480"

ao2e6 "fp_8400_4480"

ao2e9 "fp_9520_4480"

ao2e15 "fp_11200_4480"

ao2h1 "fp_4480_4480"

ao2h2 "fp_4480_4480"

ao2h3 "fp_5040_4480"

ao2h6 "fp_7280_4480"

ao2h9 "fp_8400_4480"

ao2h15 "fp_10080_4480"

ao2i1 "fp_3360_4480"

ao2i2 "fp_3360_4480"

ao2i3 "fp_3360_4480"

ao2i6 "fp_6160_4480"

ao2i9 "fp_7280_4480"

ao2i15 "fp_8960_4480"

ao4a1 "fp_5040_4480"

ao4a2 "fp_5040_4480"

ao4a3 "fp_5040_4480"

ao4a6 "fp_5600_4480"

ao4a9 "fp_6160_4480"

ao4a15 "fp_11760_4480"

ao4b1 "fp_5600_4480"

ao4b2 "fp_5600_4480"

ao4b3 "fp_5600_4480"

ao4b6 "fp_6160_4480"

ao4b9 "fp_7840_4480"

ao4b15 "fp_11760_4480"

ao4c1 "fp_5600_4480"

ao4c2 "fp_5600_4480"

ao4c3 "fp_6160_4480"

ao4c6 "fp_8960_4480"

ao4c9 "fp_12320_4480"

ao4c15 "fp_12880_4480"

ao4d1 "fp_5600_4480"

ao4d2 "fp_5600_4480"

ao4d3 "fp_6160_4480"

ao4d6 "fp_8960_4480"

64

ao4d9 "fp_10080_4480"

ao4d15 "fp_11760_4480"

ao4e1 "fp_5040_4480"

ao4e2 "fp_5040_4480"

ao4e3 "fp_5040_4480"

ao4e6 "fp_7280_4480"

ao4e9 "fp_7280_4480"

ao4e15 "fp_8400_4480"

ao4f1 "fp_3920_4480"

ao4f2 "fp_3920_4480"

ao4f3 "fp_3920_4480"

ao4f6 "fp_5600_4480"

ao4f9 "fp_6160_4480"

ao4f15 "fp_7280_4480"

buf1a1 "fp_2240_4480"

buf1a2 "fp_2240_4480"

buf1a3 "fp_2800_4480"

buf1a6 "fp_3360_4480"

buf1a9 "fp_3920_4480"

buf1a15 "fp_6160_4480"

buf1a27 "fp_10080_4480"

clk1a2 "fp_2240_4480"

clk1a3 "fp_2240_4480"

clk1a6 "fp_3360_4480"

clk1a9 "fp_3920_4480"

clk1a15 "fp_6160_4480"

clk1a27 "fp_11760_4480"

clk1a54 "fp_24640_4480"

clk1b2 "fp_1680_4480"

clk1b3 "fp_1680_4480"

clk1b6 "fp_2240_4480"

clk1b9 "fp_5040_4480"

clk1b15 "fp_7280_4480"

clk1b27 "fp_10640_4480"

clk1b54 "fp_19040_4480"

fa1a1 "fp_11200_4480" r

fa1a2 "fp_11200_4480" r

fa1a3 "fp_11200_4480" r

fa1b1 "fp_12320_4480" r, udp

fa1b2 "fp_12320_4480" r, udp

fa1b3 "fp_12320_4480" r, udp

fa2a1 "fp_10640_4480" r

fa2a2 "fp_12320_4480" r

fa2a3 "fp_12320_4480" r

fac1b1 "fp_6160_4480"

fac1b2 "fp_6160_4480"

fac1b3 "fp_6160_4480"

fac2a1 "fp_3920_4480"

fac2a2 "fp_6720_4480"

fac2a3 "fp_6720_4480"

65

faccs1b1 "fp_11760_4480" r

faccs1b2 "fp_11760_4480" r

faccs1b3 "fp_11760_4480" r

faccs2a1 "fp_11760_4480" r, udp

faccs2a2 "fp_11760_4480" r, udp

faccs2a3 "fp_11760_4480" r, udp

faccs3a1 "fp_3360_4480" r

faccs3a2 "fp_3360_4480" r

faccs3a3 "fp_3920_4480" r

facs1b1 "fp_21840_4480" r

facs1b2 "fp_21840_4480" r

facs1b3 "fp_21840_4480" r

facs2a1 "fp_21840_4480" r, udp

facs2a2 "fp_21280_4480" r, udp

facs2a3 "fp_21280_4480" r, udp

facs3a1 "fp_11760_4480" r, udp

facs3a2 "fp_11760_4480" r, udp

facs3a3 "fp_12320_4480" r, udp

facs4a1 "fp_11200_4480" r, udp

facs4a2 "fp_11200_4480" r, udp

facs4a3 "fp_12320_4480" r, udp

facsf1b1 "fp_20160_4480" r

facsf1b2 "fp_20160_4480" r

facsf1b3 "fp_20720_4480" r

facsf2a1 "fp_23520_4480" r, udp

facsf2a2 "fp_23520_4480" r, udp

facsf2a3 "fp_23520_4480" r, udp

fdef1a1 "fp_12880_4480" s

fdef1a2 "fp_12880_4480" s

fdef1a3 "fp_12880_4480" s

fdef1a6 "fp_14000_4480" s

fdef1a9 "fp_15120_4480" s

fdef1a15 "fp_17920_4480" s

fdef2a1 "fp_15120_4480" s

fdef2a2 "fp_15120_4480" s

fdef2a3 "fp_15120_4480" s

fdef2a6 "fp_16800_4480" s

fdef2a9 "fp_17920_4480" s

fdef2a15 "fp_21280_4480" s

fdef2c1 "fp_16240_4480" s

fdef2c2 "fp_16240_4480" s

fdef2c3 "fp_16240_4480" s

fdef2c6 "fp_17360_4480" s

fdef2c9 "fp_17920_4480" s

fdef2c15 "fp_21840_4480" s

fdef3a1 "fp_16240_4480" s

fdef3a2 "fp_16240_4480" s

fdef3a3 "fp_16240_4480" s

fdef3a6 "fp_17360_4480" s

fdef3a9 "fp_18480_4480" s

66

fdef3a15 "fp_21840_4480" s

fdesf1a1 "fp_16800_4480" s, t(mux_ff)












fdesf2c1 "fp_20160_4480" s, t(mux_ff)












fdf1a1 "fp_9520_4480" s

fdf1a2 "fp_9520_4480" s

fdf1a3 "fp_9520_4480" s

fdf1a6 "fp_11200_4480" s

fdf1a9 "fp_11200_4480" s

fdf1a15 "fp_14000_4480" s

fdf1b1 "fp_10080_4480" s

fdf1b2 "fp_10080_4480" s

fdf1b3 "fp_10080_4480" s

fdf1b6 "fp_10640_4480" s

fdf1b9 "fp_11760_4480" s

fdf1b15 "fp_13440_4480" s

fdf1c1 "fp_8400_4480" s

fdf1c2 "fp_8400_4480" s

fdf1c3 "fp_8400_4480" s

fdf1c6 "fp_8960_4480" s

fdf1c9 "fp_12880_4480" s

fdf1c15 "fp_14560_4480" s

fdf1d1 "fp_8960_4480" s

fdf1d2 "fp_8960_4480" s

fdf1d3 "fp_8960_4480" s

fdf1d6 "fp_8960_4480" s

fdf1d9 "fp_12320_4480" s

fdf1d15 "fp_15120_4480" s

fdf2a1 "fp_11760_4480" s

67

fdf2a2 "fp_12320_4480" s

fdf2a3 "fp_11760_4480" s

fdf2a6 "fp_12320_4480" s

fdf2a9 "fp_15120_4480" s

fdf2a15 "fp_16800_4480" s

fdf2b1 "fp_11760_4480" s

fdf2b2 "fp_11760_4480" s

fdf2b3 "fp_11760_4480" s

fdf2b6 "fp_12320_4480" s

fdf2b9 "fp_15120_4480" s

fdf2b15 "fp_16800_4480" s

fdf2c1 "fp_12880_4480" s

fdf2c2 "fp_12880_4480" s

fdf2c3 "fp_12880_4480" s

fdf2c6 "fp_13440_4480" s

fdf2c9 "fp_14560_4480" s

fdf2c15 "fp_17360_4480" s

fdf3a1 "fp_12880_4480" s

fdf3a2 "fp_12880_4480" s

fdf3a3 "fp_12880_4480" s

fdf3a6 "fp_14000_4480" s

fdf3a9 "fp_14560_4480" s

fdf3a15 "fp_17360_4480" s

fdf3b1 "fp_12880_4480" s

fdf3b2 "fp_12880_4480" s

fdf3b3 "fp_12880_4480" s

fdf3b6 "fp_14000_4480" s

fdf3b9 "fp_14560_4480" s

fdf3b15 "fp_17360_4480" s

fdmf1a1 "fp_14000_4480" s, t(mux_ff)

fdmf1a2 "fp_14000_4480" s, t(mux_ff)

fdmf1a3 "fp_14000_4480" s, t(mux_ff)

fdmf1a6 "fp_14560_4480" s, t(mux_ff)

fdmf1a9 "fp_15680_4480" s, t(mux_ff)

fdmf1a15 "fp_17920_4480" s, t(mux_ff)

fdmf1b1 "fp_13440_4480" s, t(mux_ff)

fdmf1b2 "fp_13440_4480" s, t(mux_ff)

fdmf1b3 "fp_13440_4480" s, t(mux_ff)

fdmf1b6 "fp_13440_4480" s, t(mux_ff)

fdmf1b9 "fp_15680_4480" s, t(mux_ff)

fdmf1b15 "fp_18480_4480" s, t(mux_ff)

fdmf1c1 "fp_11760_4480" s, t(mux_ff)

fdmf1c2 "fp_11760_4480" s, t(mux_ff)

fdmf1c3 "fp_12320_4480" s, t(mux_ff)

fdmf1c6 "fp_15120_4480" s, t(mux_ff)

fdmf1c9 "fp_15680_4480" s, t(mux_ff)

fdmf1c15 "fp_18480_4480" s, t(mux_ff)

fdmf1d1 "fp_12880_4480" s, t(mux_ff)

fdmf1d2 "fp_12880_4480" s, t(mux_ff)

fdmf1d3 "fp_12880_4480" s, t(mux_ff)

68

fdmf1d6 "fp_15120_4480" s, t(mux_ff)

fdmf1d9 "fp_16240_4480" s, t(mux_ff)

fdmf1d15 "fp_17920_4480" s, t(mux_ff)

fdmf2a1 "fp_15680_4480" s, t(mux_ff)

fdmf2a2 "fp_15680_4480" s, t(mux_ff)

fdmf2a3 "fp_15120_4480" s, t(mux_ff)

fdmf2a6 "fp_15680_4480" s, t(mux_ff)

fdmf2a9 "fp_18480_4480" s, t(mux_ff)

fdmf2a15 "fp_20720_4480" s, t(mux_ff)

fdmf2b1 "fp_15680_4480" s, t(mux_ff)

fdmf2b2 "fp_16240_4480" s, t(mux_ff)

fdmf2b3 "fp_16240_4480" s, t(mux_ff)

fdmf2b6 "fp_15680_4480" s, t(mux_ff)

fdmf2b9 "fp_18480_4480" s, t(mux_ff)

fdmf2b15 "fp_20160_4480" s, t(mux_ff)

fdmf2c1 "fp_16800_4480" s, t(mux_ff)

fdmf2c2 "fp_16800_4480" s, t(mux_ff)

fdmf2c3 "fp_16800_4480" s, t(mux_ff)

fdmf2c6 "fp_17360_4480" s, t(mux_ff)

fdmf2c9 "fp_17920_4480" s, t(mux_ff)

fdmf2c15 "fp_21280_4480" s, t(mux_ff)

fdmf3a1 "fp_15120_4480" s, t(mux_ff)

fdmf3a2 "fp_15120_4480" s, t(mux_ff)

fdmf3a3 "fp_15120_4480" s, t(mux_ff)

fdmf3a6 "fp_16240_4480" s, t(mux_ff)

fdmf3a9 "fp_17360_4480" s, t(mux_ff)

fdmf3a15 "fp_20160_4480" s, t(mux_ff)

fdmf3b1 "fp_15120_4480" s, t(mux_ff)

fdmf3b2 "fp_15120_4480" s, t(mux_ff)

fdmf3b3 "fp_15120_4480" s, t(mux_ff)

fdmf3b6 "fp_15680_4480" s, t(mux_ff)

fdmf3b9 "fp_16800_4480" s, t(mux_ff)

fdmf3b15 "fp_19040_4480" s, t(mux_ff)

fill1 "fp_560_4480" b, d, u

fill2 "fp_1120_4480" b, d, u

fill4 "fp_2240_4480" b, d, u

fill8 "fp_4480_4480" b, d, u

ha1a1 "fp_6720_4480" r

ha1a2 "fp_6720_4480" r

ha1a3 "fp_6720_4480" r

ha1b1 "fp_6720_4480" r, udp

ha1b2 "fp_6720_4480" r, udp

ha1b3 "fp_6720_4480" r, udp

ha2a1 "fp_6160_4480" r

ha2a2 "fp_6720_4480" r

ha2a3 "fp_6720_4480" r

hacs1b1 "fp_10640_4480" r, udp

hacs1b2 "fp_10640_4480" r, udp

hacs1b3 "fp_10640_4480" r, udp

hacs2a1 "fp_11200_4480" r, udp

69

hacs2a2 "fp_11200_4480" r, udp

hacs2a3 "fp_11200_4480" r, udp

hacs3a1 "fp_5040_4480" r, udp

hacs3a2 "fp_5600_4480" r, udp

hacs3a3 "fp_5600_4480" r, udp

hld1a0 "fp_3920_4480" b, d, u

inv1a1 "fp_1120_4480"

inv1a2 "fp_1680_4480"

inv1a3 "fp_1680_4480"

inv1a6 "fp_2240_4480"

inv1a9 "fp_3360_4480"

inv1a15 "fp_4480_4480"

inv1a27 "fp_7840_4480"

ldf1a1 "fp_6160_4480" s

ldf1a2 "fp_6160_4480" s

ldf1a3 "fp_6160_4480" s

ldf1a6 "fp_6720_4480" s

ldf1a9 "fp_7840_4480" s

ldf1a15 "fp_9520_4480" s

ldf1b1 "fp_6160_4480" s

ldf1b2 "fp_6160_4480" s

ldf1b3 "fp_6160_4480" s

ldf1b6 "fp_6720_4480" s

ldf1b9 "fp_7280_4480" s

ldf1b15 "fp_9520_4480" s

ldf2a1 "fp_7280_4480" s

ldf2a2 "fp_7840_4480" s

ldf2a3 "fp_7280_4480" s

ldf2a6 "fp_8400_4480" s

ldf2a9 "fp_10640_4480" s

ldf2a15 "fp_12320_4480" s

ldmf1a1 "fp_10080_4480" s

ldmf1a2 "fp_10080_4480" s

ldmf1a3 "fp_10080_4480" s

ldmf1a6 "fp_10080_4480" s

ldmf1a9 "fp_10640_4480" s

ldmf1a15 "fp_13440_4480" s

ldmf1b1 "fp_9520_4480" s

ldmf1b2 "fp_10080_4480" s

ldmf1b3 "fp_10080_4480" s

ldmf1b6 "fp_10080_4480" s

ldmf1b9 "fp_11760_4480" s

ldmf1b15 "fp_12880_4480" s

ldmf2a1 "fp_11200_4480" s

ldmf2a2 "fp_11200_4480" s

ldmf2a3 "fp_11200_4480" s

ldmf2a6 "fp_12320_4480" s

ldmf2a9 "fp_14000_4480" s

ldmf2a15 "fp_15680_4480" s

mule2a1 "fp_11200_4480" r

70

mule2a2 "fp_11200_4480" r

mule2a3 "fp_11760_4480" r

mulpa1b1 "fp_7840_4480"

mulpa1b2 "fp_8400_4480"

mulpa1b3 "fp_8400_4480"

mulpa2b1 "fp_8960_4480"

mulpa2b2 "fp_8960_4480"

mulpa2b3 "fp_8960_4480"

mulpa3b1 "fp_7840_4480"

mulpa3b2 "fp_7840_4480"

mulpa3b3 "fp_7840_4480"

mulpa4b1 "fp_8960_4480"

mulpa4b2 "fp_8960_4480"

mulpa4b3 "fp_8960_4480"

mx2a1 "fp_4480_4480"

mx2a2 "fp_5040_4480"

mx2a3 "fp_5040_4480"

mx2a6 "fp_6720_4480"

mx2a9 "fp_7840_4480"

mx2a15 "fp_8960_4480"

mx2d1 "fp_4480_4480"

mx2d2 "fp_4480_4480"

mx2d3 "fp_4480_4480"

mx2d6 "fp_5040_4480"

mx2d9 "fp_8400_4480"

mx2d15 "fp_10080_4480"

mx3a1 "fp_8960_4480"

mx3a2 "fp_8960_4480"

mx3a3 "fp_8960_4480"

mx3a6 "fp_10080_4480"

mx3a9 "fp_11200_4480"

mx3a15 "fp_13440_4480"

mx3d1 "fp_7840_4480"

mx3d2 "fp_7840_4480"

mx3d3 "fp_8400_4480"

mx3d6 "fp_8960_4480"

mx3d9 "fp_12320_4480"

mx3d15 "fp_13440_4480"

mx4a1 "fp_11760_4480"

mx4a2 "fp_11760_4480"

mx4a3 "fp_11760_4480"

mx4a6 "fp_12320_4480"

mx4a9 "fp_13440_4480"

mx4a15 "fp_15680_4480"

mx4e1 "fp_10640_4480"

mx4e2 "fp_10640_4480"

mx4e3 "fp_10640_4480"

mx4e6 "fp_11200_4480"

mx4e9 "fp_12320_4480"

mx4e15 "fp_14560_4480"

71

oa1a1 "fp_4480_4480"

oa1a2 "fp_4480_4480"

oa1a3 "fp_4480_4480"

oa1a6 "fp_5600_4480"

oa1a9 "fp_6160_4480"

oa1a15 "fp_8960_4480"

oa1b1 "fp_5040_4480"

oa1b2 "fp_5040_4480"

oa1b3 "fp_5040_4480"

oa1b6 "fp_5600_4480"

oa1b9 "fp_7280_4480"

oa1b15 "fp_10080_4480"

oa1c1 "fp_4480_4480"

oa1c2 "fp_4480_4480"

oa1c3 "fp_4480_4480"

oa1c6 "fp_6160_4480"

oa1c9 "fp_8400_4480"

oa1c15 "fp_11760_4480"

oa1d1 "fp_3360_4480"

oa1d2 "fp_3360_4480"

oa1d3 "fp_3920_4480"

oa1d6 "fp_5040_4480"

oa1d9 "fp_6720_4480"

oa1d15 "fp_10640_4480"

oa1e1 "fp_4480_4480"

oa1e2 "fp_4480_4480"

oa1e3 "fp_4480_4480"

oa1e6 "fp_6720_4480"

oa1e9 "fp_8400_4480"

oa1e15 "fp_11760_4480"

oa1f1 "fp_2800_4480"

oa1f2 "fp_2800_4480"

oa1f3 "fp_2800_4480"

oa1f6 "fp_5600_4480"

oa1f9 "fp_5600_4480"

oa1f15 "fp_6720_4480"

oa2a1 "fp_5040_4480"

oa2a2 "fp_5040_4480"

oa2a3 "fp_5040_4480"

oa2a6 "fp_5600_4480"

oa2a9 "fp_6720_4480"

oa2a15 "fp_11200_4480"

oa2c1 "fp_5600_4480"

oa2c2 "fp_5600_4480"

oa2c3 "fp_6160_4480"

oa2c6 "fp_8400_4480"

oa2c9 "fp_9520_4480"

oa2c15 "fp_11200_4480"

oa2i1 "fp_3360_4480"

oa2i2 "fp_3360_4480"

72

oa2i3 "fp_3920_4480"

oa2i6 "fp_6160_4480"

oa2i9 "fp_7280_4480"

oa2i15 "fp_8960_4480"

oa4a1 "fp_4480_4480"

oa4a2 "fp_4480_4480"

oa4a3 "fp_5600_4480"

oa4a6 "fp_6160_4480"

oa4a9 "fp_6720_4480"

oa4a15 "fp_11760_4480"

oa4b1 "fp_5600_4480"

oa4b2 "fp_5600_4480"

oa4b3 "fp_6160_4480"

oa4b6 "fp_6720_4480"

oa4b9 "fp_7840_4480"

oa4b15 "fp_12320_4480"

oa4c1 "fp_5600_4480"

oa4c2 "fp_5600_4480"

oa4c3 "fp_5600_4480"

oa4c6 "fp_7840_4480"

oa4c9 "fp_8400_4480"

oa4c15 "fp_8960_4480"

oa4d1 "fp_5040_4480"

oa4d2 "fp_5600_4480"

oa4d3 "fp_5600_4480"

oa4d6 "fp_6720_4480"

oa4d9 "fp_7840_4480"

oa4d15 "fp_10080_4480"

oa4e1 "fp_5040_4480"

oa4e2 "fp_5040_4480"

oa4e3 "fp_5040_4480"

oa4e6 "fp_7280_4480"

oa4e9 "fp_6720_4480"

oa4e15 "fp_8400_4480"

oa4f1 "fp_3920_4480"

oa4f2 "fp_3920_4480"

oa4f3 "fp_3920_4480"

oa4f6 "fp_5600_4480"

oa4f9 "fp_6160_4480"

oa4f15 "fp_7280_4480"

or2a1 "fp_2800_4480"

or2a2 "fp_2800_4480"

or2a3 "fp_3360_4480"

or2a6 "fp_3920_4480"

or2a9 "fp_5040_4480"

or2a15 "fp_7840_4480"

or2b1 "fp_2800_4480"

or2b2 "fp_2800_4480"

or2b3 "fp_3920_4480"

or2b6 "fp_4480_4480"

73

or2b9 "fp_6160_4480"

or2b15 "fp_8960_4480"

or2c1 "fp_1680_4480"

or2c2 "fp_2240_4480"

or2c3 "fp_2240_4480"

or2c6 "fp_3920_4480"

or2c9 "fp_5040_4480"

or2c15 "fp_7840_4480"

or3a1 "fp_3920_4480"

or3a2 "fp_3920_4480"

or3a3 "fp_3920_4480"

or3a6 "fp_4480_4480"

or3a9 "fp_5600_4480"

or3a15 "fp_9520_4480"

or3c1 "fp_3920_4480"

or3c2 "fp_3920_4480"

or3c3 "fp_5600_4480"

or3c6 "fp_6720_4480"

or3c9 "fp_7280_4480"

or3c15 "fp_9520_4480"

or3d1 "fp_2240_4480"

or3d2 "fp_2800_4480"

or3d3 "fp_2800_4480"

or3d6 "fp_5040_4480"

or3d9 "fp_7280_4480"

or3d15 "fp_12320_4480"

or4a3 "fp_6160_4480"

or4a6 "fp_6720_4480"

or4a9 "fp_8960_4480"

or4a15 "fp_10640_4480"

or4e3 "fp_6720_4480"

or4e6 "fp_6720_4480"

or4e9 "fp_7840_4480"

or4e15 "fp_10640_4480"

or6a3 "fp_7280_4480"

or6a6 "fp_7840_4480"

or6a9 "fp_11200_4480"

or6a15 "fp_12880_4480"

tri1a1 "fp_5600_4480"

tri1a2 "fp_5600_4480"

tri1a3 "fp_6720_4480"

tri1a6 "fp_6720_4480"

tri1a9 "fp_7840_4480"

tri1a15 "fp_9520_4480"

tri1a27 "fp_16240_4480"

tri1b1 "fp_3360_4480"

tri1b2 "fp_4480_4480"

tri1b3 "fp_4480_4480"

tri1b6 "fp_8400_4480"

tri1b9 "fp_11760_4480"

74

tri1b15 "fp_13440_4480"

tri1b27 "fp_19040_4480"

xor2a1 "fp_5040_4480"

xor2a2 "fp_5040_4480"

xor2a3 "fp_5600_4480"

xor2a6 "fp_6160_4480"

xor2a9 "fp_7840_4480"

xor2a15 "fp_9520_4480"

xor2b1 "fp_5040_4480"

xor2b2 "fp_5040_4480"

xor2b3 "fp_5600_4480"

xor2b6 "fp_6160_4480"

xor2b9 "fp_7840_4480"

xor2b15 "fp_10640_4480"

xor3a1 "fp_10640_4480"

xor3a2 "fp_11760_4480"

xor3a3 "fp_11200_4480"

xor3a6 "fp_11760_4480"

xor3a9 "fp_14000_4480"

xor3a15 "fp_15120_4480"

xor3b1 "fp_8400_4480"

xor3b2 "fp_8400_4480"

xor3b3 "fp_8400_4480"

xor3b6 "fp_10640_4480"

xor3b9 "fp_11760_4480"

xor3b15 "fp_13440_4480"

12.5 Lab6 Task2 Generated Script

###################################################################

# Created by write_script -format dctcl on Sat Mar 21 18:51:16 2009

###################################################################

# Set the current_design #

current_design PRGRM_CNT_TOP

remove_wire_load_model

set_driving_cell -lib_cell fdef1a1 -pin Q [get_ports Reset]

set_driving_cell -lib_cell fdef1a1 -pin Q [get_ports {Crnt_Instrn[31]}]










75























set_driving_cell -lib_cell fdef1a1 -pin Q [get_ports Zro_Flag]

set_driving_cell -lib_cell fdef1a1 -pin Q [get_ports Carry_Flag]

set_driving_cell -lib_cell fdef1a1 -pin Q [get_ports Neg_Flag]

set_driving_cell -lib_cell fdef1a1 -pin Q [get_ports {Return_Addr[7]}]








set_load -pin_load 0.03 [get_ports {Current_State[2]}]



set_load -pin_load 0.03 [get_ports {PC[7]}]








set_max_capacitance 0.01 [get_ports Reset]

set_max_capacitance 0.01 [get_ports {Crnt_Instrn[31]}]





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set_max_capacitance 0.01 [get_ports Zro_Flag]

set_max_capacitance 0.01 [get_ports Carry_Flag]

set_max_capacitance 0.01 [get_ports Neg_Flag]

set_max_capacitance 0.01 [get_ports {Return_Addr[7]}]








create_clock [get_ports Clk] -name my_clk -period 4 -waveform {0 2}


set_input_delay -clock my_clk -max 1 [get_ports Reset]

set_input_delay -clock my_clk -max 1 [get_ports {Crnt_Instrn[31]}]









77
























set_input_delay -clock my_clk -max 1 [get_ports Zro_Flag]

set_input_delay -clock my_clk -max 1 [get_ports Carry_Flag]

set_input_delay -clock my_clk -max 1 [get_ports Neg_Flag]

set_input_delay -clock my_clk -max 1 [get_ports {Return_Addr[7]}]








set_output_delay -clock my_clk -max 3 [get_ports {Current_State[2]}]



set_output_delay -clock my_clk -max 3 [get_ports {PC[7]}]








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