Lab 05 Sen Ma. What is a Register ? “In computer architecture, a register is a small amount of...

Lab 05

Sen Ma

What is a Register ?

“In computer architecture, a register is a small amount of

storage available as part of a CPU. ”--Wikipedia

What is Register ?



Data in the Random-access memory (RAM)

What is Register ?



Data in the Random-access memory (RAM)

Registers are stored in a structure called a register file which impalement by using RAM.

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0000

R3 0x0000

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File

AssumeAssume we have 10 registers.R0 ~ R9

Each register has 16bits.

Another assumptionAnother assumptionR0 = 0 and R1 = 1 (forever)

Register File’s name

What is Register ?Oh Yeah, we have registers!

We can design our own instructions

R0 0x0000

R1 0x0001

R2 0x0000

R3 0x0000

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

How about this:R2 = R0 + R1

Reg_File



R0 0x0000

R1 0x0001

R2 0x0000

R3 0x0000

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000


R2 = R0 + R1

Reg_File



R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0000

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000


R2 = R0 + R1

Reg_File



R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0000

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000


R2 = R0 + R1

We have already know the assembly language:

R2 = R0 + R1

add R2, R0, R1

Reg_File

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0000

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

One more!add R3, R1, R2

Reg_File

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

One more!add R3, R1, R2

Reg_File

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Behind the scene:You can think about the

Reg_File is an Array.When you read from or write

in the register, it is same operation on an array which

you have already know.

Reg_File

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File

Same Example:add R3, R1, R2

1 step, Read R1: Reg_File[1]

Register File’s name(array’s name)

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File




What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File




3 step Add Reg_File[1] + Reg_File[2]

What is Register ?

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File




3 step Add Reg_File[1] + Reg_File[2]

4 step, Write R3:Reg_File[3] = Reg_File[1] + Reg_File[2]

Register in VHDL

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File

Define an array in VHDL:type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);

Register in VHDL

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_FileDefine a type named

“ram_type” which is a array with 16 item. Each item is a 16bits vector

Define an array in VHDL:type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);

Register in VHDL

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File

Define an array in VHDL:type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);signal Reg_File : ram_type;

Using the “ram_type” to define a signal

named “Reg_File”.

Register in VHDL

R0 0x0000

R1 0x0001

R2 0x0001

R3 0x0002

R4 0x0000

R5 0x0000

R6 0x0000

R7 0x0000

R8 0x0000

R9 0x0000

Reg_File

Define an array in VHDL:type ram_type is array (15 downto 0) of std_logic_vector(15 downto 0);signal Reg_File : ram_type;


Reg_File(3) <= Reg_File(1) + Reg_File(2);

Register

clk

clear

A_addr

A_data

load

b_addr

c_addr

b_data

c_data

RegisterEntity Register is port(

clk: in std_logic; -- positive edge triggered clockclear: in std_logic; -- asynchronous reset

a_addr: in std_logic_vector( 3 downto 0); -- input data porta_data: in std_logic_vector(15 downto 0); -- register select for input aload: in std_logic; -- load enable

b_addr: in std_logic_vector( 3 downto 0); -- register select for output bc_addr: in std_logic_vector( 3 downto 0); -- register select for output c

b_data: out std_logic_vector(15 downto 0); -- first output data portc_data: out std_logic_vector(15 downto 0) -- second output data port

);End Register;

RegisterRequirements:•Create a register file. •It should have 16 registers, each being sixteen bits wide.

•When the load signal is asserted, a rising edge on clk cause the data on a_data to be stored in the register identified by a_addr.

•If the load signal is not asserted, a rising clock edge has no effect. •The data on b_data should be the contents of the register identified by b_addr. •The data on c_data should be the contents of the register identified by c_addr. •Register 0 always contains the value 0. Writing to register 0 is ignored. •Register 1 always contains the value 1. Writing to register 1 is ignored. •When the clear signal is 0, all registers (other than register 1) are reset to 0. Note that this is asynchronous. •Follow the instruction on page 129~130 in Xilinx XST User Guide, reference the example code to implement your own register file.

Lab 05 Sen Ma. What is a Register ? “In computer architecture, a register is a small amount of...

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