L6 - Latches, The D Flip-Flop and Counter Design

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Transcript of L6 - Latches, The D Flip-Flop and Counter Design

Latches, the D Flip-Flop & Counter DesignECE 152A Summer 2009

Reading AssignmentBrown and Vranesic7 Flip-Flops, Registers, Counters and a Simple Processor7.1 Basic Latch 7.2 Gated SR Latch7.2.1 Gated SR Latch with NAND Gates

7.3 Gated D Latch7.3.1 Effects of Propagation Delays

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Reading AssignmentBrown and Vranesic (cont)7 Flip-Flops, Registers, Counters and a Simple Processor (cont)7.4 Master-Slave and Edge-Triggered D Flip-Flops7.4.1 Master-Slave D Flip-Flop 7.4.2 Edge-Triggered D Flip-Flop 7.4.3 D Flip-Flop with Clear and Preset 7.4.4 Flip-Flop Timing Parameters (2nd edition)

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Reading AssignmentRoth11 Latches and Flip-Flops11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop

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Reading AssignmentRoth (cont)12 Registers and Counters12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other Sequences

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Combinational vs. Sequential LogicCombinational logicFunction of present inputs onlyOutput is known if inputs (some or all) are known

Sequential logicFunction of past and present inputsMemory or state Output known if present input and present state are knownInitial conditions often unknown (or undefined)

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Gate DelaysRecall from earlier lectureWhen gate inputs change, outputs dont change instantaneously

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FeedbackOutputs connected to inputsSingle inverter feedbackIf propagation delay is long enough, output will oscillate

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FeedbackIf the propagation delay is not long enough, the output will settle somewhere in the middleVin = Vout

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FeedbackRing OscillatorAny odd number of inverters will oscillate period = total prop delay of chain

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FeedbackWhat about an even number of inversions?Two inverter feedbackMemory (or State) Static 1 or 0 stored in memory

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The LatchReplace inverters with NOR gates

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The Set-Reset (SR) LatchNOR implementationInverted feedback

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The SR LatchR = Reset (clear)Q 0, Q* 1

S = Set (preset)Q 1, Q* 0

NOR gate implementationEither input = 1 forces an output to 0

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The SR Latch (cont)TerminologyPresent state, QCurrent value of Q and Q*

Next state, Q+Final value of Q and Q* after input changes

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The SR Latch (cont)OperationS=1, R=0 : set to 1, Q+ = 1 S=0, R=1 : reset to 0, Q+ = 0 S=0, R=0 : hold state, Q+ = Q S=1, R=1 : not allowedQ+ = Q*+ = 0, lose state

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The SR Latch (cont)Timing DiagramRS inputs are pulsesTemporarily high, but normally low

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The SR Latch (cont)Characteristic EquationAlgebraic expression of flip-flop behavior Plot characteristic table on map, find Q+Q+ = S + RQ (S = R = 1 not allowed)

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The SR Latch (cont)Characteristic EquationQ+ = S + RQ (S = R = 1 not allowed)Q becomes 1 when S = 1, R = 0 Stays Q when S = R = 0 Q becomes 0 when S = 0, R = 1

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The SR Latch (cont)State Table

NS (Q+) PS (Q) 0 1 SR=00 0 1 01 0 0 10 1 1 11 X X

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The SR Latch (cont)State DiagramSR = 01

SR = X0

1

0

SR = 0X

SR = 10

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The SR Latch with NANDSNAND Based SR LatchS = R = 0 not allowed Either input = 0 forces output to 1

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The Gated SR LatchAlso known as transparent latchOutput follows input (transparent) when enabled

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The Gated SR Latch (cont)Timing Diagram

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The Gated SR Latch (cont)NAND Implementation

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The Gated Data (D) LatchNAND Implementation of transparent D latch

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The Gated D LatchTiming Diagram

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The Edge Triggered D Flip-FlopThe D Flip-FlopInput D, latched and passed to Q on clock edge Rising edge triggered or falling edge triggeredCharacteristic table and function

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The Edge Triggered D Flip-FlopMost commonly used flip-flop Output follows input after clock edgeQ and Q* change only on clock edge Timing diagram for negative edge triggered flip-flop

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The D Flip-FlopState Table

NS (Q+) PS (Q) 0 1 D=0 0 0 D=1 1 1

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The D Flip-Flop (cont)State DiagramD=0

D=1

1

0

D=0

D=1

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The Master-Slave D Flip-FlopConstruct edge triggered flip-flop from 2 transparent latchesMany other topologies for edge triggered flip-flops Falling edge triggered (below)

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The Master-Slave D Flip-Flop (cont)Timing DiagramFalling edge triggered

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The Master-Slave D Flip-Flop (cont)A Second Timing DiagramRising edge triggered

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The Edge Triggered D Flip-FlopTrue Edge Triggered D Flip-FlopNever transparent (unlike Master Slave)

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The Edge Triggered D Flip-FlopOperation of Flip-Flop

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Types of D Flip-FlopsGated, Positive Edge and Negative Edge

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Timing ParametersCLK QDelay from clock edge (CLK) to valid (Q, Q*) output

Setup time tsuStable, valid data (D) before clock edge (CLK)

Hold time tholdStable, valid data (D) after clock edge (CLK)

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Maximum FrequencyMaximum frequency (minimum clock period) for a digital systemCLK Q + propagation delay + tsu

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Counter Design with D Flip-FlopsDesign Example #1: Modulo 3 counter00 01 10

Requires 2 flip-flopsOne for each state variable

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Counter Design with D Flip-FlopsState Diagram

00

01

Transitions on clock edge

10

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Counter Design with D Flip-FlopsState TablePS A 0 0 1 1 NS B 0 1 0 1 A+ 0 1 0 X B+ 1 0 0 X

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Counter Design with D Flip-FlopsNext State MapsB A 0 1 0 0 0 B A 0 1 0 1 0

1 1 X

1 0 X

A+ = B

B+ = AB

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Counter Design with D Flip-FlopsImplementation with D Flip-Flops What are the D inputs to flip-flops A and B?Recall characteristic equation for D flip-flopQ+ = D Therefore, and A+ = B DA = B + = AB D = AB B B

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Counter Design with D Flip-FlopsImplementation with positive edge triggered flip-flops

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Counter Design with D Flip-FlopsImplementation with positive edge triggered flip-flopsTiming diagram

00

01

10

00

01

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Counter Design with D Flip-FlopsDesign Example #2:Modulo 3 counter with up/down* inputCounter counts up with input = 1 and down with input = 0

Implement with D flip-flops

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