TP4: S TATE M ACHINE D ESIGN P ATTERN Definition Infrastructure Transition Code Conclusion.
L EAKAGE and T AMPER Resilient R andom A ccess M achine ( LTRAM )
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LEAKAGE and TAMPER Resilient Random Access Machine (LTRAM) Pratyay Mukherjee Aarhus University Joint work with Sebastian Faust, Jesper Buus Nielsen and Daniele Venturi
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L EAKAGE and T AMPER Resilient R andom A ccess M achine ( LTRAM ). Pratyay Mukherjee Aarhus University Joint work with Sebastian Faust, Jesper Buus Nielsen and Daniele Venturi. Provable security breaks down!. Because…. The Model. Reality. Provable security breaks down!. - PowerPoint PPT Presentation
Transcript of L EAKAGE and T AMPER Resilient R andom A ccess M achine ( LTRAM )
LEAKAGE and TAMPER Resilient Random Access Machine (LTRAM)
Pratyay MukherjeeAarhus University
Joint work with
Sebastian Faust, Jesper Buus Nielsen and Daniele Venturi
Provable security breaks down! Because….
The Model Reality
Provable security breaks down! Because….
The Model Reality
More seriousl
y !Side channel attacks: Leakage/ Tampering
Blakcbox
Our main
focus
Models of Tampering
Tamper “only memory”Tamper “whole computation”
Models of Tampering
Tamper “only memory”Tamper “whole computation”In the beginning….
We are STRONGERrrr !!!
Models of Tampering
Tamper “only memory”Tamper “whole computation”
Existing results suffer from limitation e.g. can tamper
upto 1/poly(n)
A number of strong positive results e.g. split-state
tampering
…..after a few years….
[IPSW 06, ….., DK 14] [GLMMR 04, ……………………………..,DPW 10,…..]
I have better RESULTS !!!
Our approachCan we protect against more Tampering with computation if we consider RAM ?
Instead of
Protect me !
Our Result: RAM + NMC => TRAM
TRAM
TCC 2014
Idea: Encode locations with NMC.
Note: The computation is stored as a program.
In fact we can get LTRAM
LTRAM
Caveat: We assume tamper-proof CPU.
But, the CPU is small and universal i.e.independent of the functionality.
Our LTRAM
CPU
Secret Disk-1
Secret Disk-2
Public disk
