Knowm Inc. | Santa Fe, New Mexico, µUS | Founded in 2015 | www.knowm.org | contact@knowm.org

The Knowm Memristor devices operate primarily through the mechanism of electric field induced generation andmovement of metal ions through a multilayer chalcogenide material stack. A secondary mechanism of operation isphase-change, which can be selected as the primary mode of operation depending upon the operating conditions.

Knowm Memristor Material Stack

The material stack is based on mobile metal ion conduction through a chalcogenide material. The devices arefabricated with a layer of metal that is easily oxidizable, located near one electrode. When a voltage is appliedacross the device with the more positive potential on the electrode near this metal layer, the metal is oxidized toform ions. Once formed, the ions move through the device towards the lower potential electrode. The ions movethrough a layer of amorphous chalcogenide material (the active layer) to reach the lower potential electrode wherethey are reduced to their metallic form and eventually form a conductive pathway between both electrodes thatspans the active material layer, lowering the device resistance. Reversing the direction of the applied potentialcauses the conductive channel to dissolve and the device resistance to increase. The devices are bipolar, cyclingbetween high and low resistance values by switching the polarity of the applied potential. The resistance is relatedat any time to the amount of metal located within the active layer.

The Knowm Memristors come in three variants: W, Sn and Cr, which refers to the metal introduced in the activelayer during fabrication. Each device is available in both raw die and packaged devices.

In the following video, Alex Nugent, explains what a memristor is, some facts and misconceptions and introducesKnowm Inc.’s commercially available memristors.

Knowm Memristors

What Is A Memristor? from Knowm on Vimeo.

Eight (8) discrete memristors in 16 Pin Ceramic DIP (Dual Inline Package) with wafer batch and serial number. Theyare available for research and development at the following URL: http://knowm.org/memristors.

Packaged Chips

Knowm Memristor 16 Pin DIP Package

DIP Package Diagram

The research die were created to allow study of device operation over a wide range of device sizes. The die are7860 μm by 5760 μm and consists of 9 columns of devices, each corresponding to a different device size. The sizeis listed at the bottom of each column. Each column contains 20 rows of each device size per column, for a total of

Raw Research Die

180 devices. The row number is listed at the left of each row. The top row, not numbered, is a metal continuity rowthat is used as a diagnostic tool for checking probe station functionality. There are no devices in this row. Instead therow consists of two shorted top electrode bond pads and two shorted bottom electrode bond pads above eachcolumn. Note that the outer ring around the die shows the alignment structures for the photolithography mask layersused during fabrication.

Raw Die

The row number is listed at the left of each row. The top row, not numbered, is a metal continuity row that is used asa diagnostic tool for checking probe station functionality. There are no devices in this row. Instead the row consistsof two shorted top electrode bond pads and two shorted bottom electrode bond pads above each column. Note thatthe outer ring around the die shows the alignment structures for the photolithography mask layers used duringfabrication.

Mask

Mask

The top and bottom electrodes for each device are denoted by the purple and blue squares, respectively. The toprow in the die, not numbered, consists only of metal continuity structures: two bond pads corresponding to the topelectrode shorted together, and two bond pads corresponding to the bottom electrode shorted together. Thesestructures are used to check probe station functionality.

An optical image of a section of the research die (taken through a microscope) is shown below. Two devices areshown in the image. The device via and the top and bottom electrodes are annotated.

Device Close-up

The device via confines the device material between the top and bottom electrodes and defines the size of thedevice. The device via is located at the intersection of the top and bottom electrodes. This is the region where thetop electrode metal and bottom electrode metal intersect. The device sizes included in the research die are 1μm,2μm, 3μm, 4μm, 5μm, 6μm, 10μm, 20μm, and 30μm and refer to the dimension of the device via. For devices ofsize 6 μm or less, the device via is round and the size refers to the nominal via diameter. For devices of sizes 10μm, 20 μm, and 30 μm, the device via shape is square and the size corresponds to the nominal length of a side.

There are three different memristor material types available in the research die:

1. GeSeW (the ‘W’ device)2. GeSeSn (the ‘Sn’ device)3. GeSeCr (the ‘Cr’ device)

Each memristor type has the same basic material structure, but they differ in the active metal added to thechalcogenide active layer.

Characteristic Value

Die Width 7860 μm

Die Height 5760 μm

Bonding Pad Width 80 μm

Bonding Pad Height 80 μm

Device Sizes(Quantity)

1 μm(20), 2 μm(20), 3 μm(20), 4 μm(20), 5 μm(20), 6 μm(20), 10 μm(20), 20 μm(20),30 μm(20)

Total Devices perDie

180

The preferred method of handling the die is by hand or with an air wand or other soft contact method. If you usetweezers, touch only the sides of the die, not the top surface as you will likely damage devices. Wear gloves whentouching the die by hand.

The devices are static sensitive and not protected. use the proper ESD protection when handling the die.

A micro-probe station is recommended for hand-probing die. An example micro-probe station is shown below.Commonly used micromanipulator probe tip is a Micromanipulator 7A or 7B tungsten probe tip, or the equivalent.

Probe Station

Handling

Device Probing

DC Electrical Characteristics of the Raw Die Devices

Note: These results are unique to the initial forming method and entire history of the device leading up to the datacollection. Different forming procedures and histories will result in different characteristics. Shown below are someDC response statisics from the raw die devices after the following forming procedure was used. Also note that thepackaged memristor devices cannot be exactly represented by these statistics, as they were made during a differentwafer run and the packaging and internal wire bonding contributing to different bahavior.

For the Cr wafer, the forming procedure is:1) Apply a sinewave with 0.6 V peak amplitude, 100 Hz, for 20 cycles to condition the devices.2) Apply a read - erase - read pulse sequence with the read pulses 500 ns width, and the amplitude of 200 mV; theerase pulse is 5 µs width, –1.5 V amplitude.3) Apply three consecutive cycles of R-W-R-E with all pulse widths 1 µs, write amplitude 900 mV, erase amplitude –1.2 V and read amplitudes of 200 mV.4) Apply a R-Wx20-R sequence with a reduced write amplitude (700 mV, 1 µs pulsewidth).5) Apply a R-Ex20-R with –1V, 1usec amplitude.6) Repeat 4.7) Repeat 5.

DC Response

Cr (Chromium) Raw Die

Characteristic Condition Min Typ Max Std

Forward AdaptationThreshold

DC / quasi-static 0.220 V 0.332 V 0.560 V 0.089 V

Reverse AdaptationThreshold

DC / quasi-static–0.660V

–0.189V

–0.040V

0.154 V

Cycle Endurance1.5 Vpp, 500 Hz sine wave, 50kΩ Series resistor

1M 50M 100M

Low ResistanceState

100nA Write Compliance Current5.48E6Ω

2.62E7Ω

4.33E7Ω

1.25E7Ω

High ResistanceState

100nA Write Compliance Current1.07E11Ω

1.59E12Ω

9.00E12Ω

2.62E12Ω

Low ResistanceState

1uA Write Compliance Current1.51E5Ω

1.90E6Ω

1.04E7Ω

2.87E6Ω

High ResistanceState

1uA Write Compliance Current7.41E7Ω

1.88E11Ω

7.63E11Ω

2.51E11Ω

Low ResistanceState

10uA Write Compliance Current3.29E4Ω

5.67E4Ω

9.90E4Ω

2.23E4Ω

High ResistanceState

10uA Write Compliance Current2.53E7Ω

1.14E11Ω

1.00E12Ω

2.96E11Ω

Low ResistanceState

100uA Write Compliance Current2.65E3Ω

4.82E3Ω

1.05E4Ω

2.09E3Ω

High ResistanceState

100uA Write Compliance Current3.40E5Ω

9.54E6Ω

6.17E7Ω

1.80E7Ω

Low ResistanceState

1mA Write Compliance Current3.86E2Ω

6.63E2Ω

9.59E2Ω

1.81E2Ω

High ResistanceState

1mA Write Compliance Current3.63E4Ω

7.49E4Ω

1.49E5Ω

4.04E4Ω

Sn (Tin) Raw Die

Characteristic Condition Min Typ Max Std

Forward AdaptationThreshold

DC / quasi-static0.150V

0.259 V 0.340 V 0.042 V

Reverse AdaptationThreshold

DC / quasi-static–0.230V

–0.094V

–0.030V

0.053 V

Cycle Endurance1.5 Vpp, 500 Hz sine wave, 50kΩ Series resistor

50M 100M 5B

Low ResistanceState

100nA Write Compliance Current7.41E5Ω

7.17E6Ω

3.56E7Ω

9.87E6Ω

High ResistanceState

100nA Write Compliance Current1.64E9Ω

9.81E11Ω

8.00E12Ω

2.35E12Ω

Low ResistanceState

1uA Write Compliance Current2.50E5Ω

1.58E7Ω

3.79E7Ω

1.53E7Ω

High ResistanceState

1uA Write Compliance Current7.60E6Ω

2.23E11Ω

1.43E12Ω

4.10E11Ω

Low ResistanceState

10uA Write Compliance Current3.14E4Ω

1.57E5Ω

1.16E6Ω

3.33E5Ω

High ResistanceState

10uA Write Compliance Current3.26E6Ω

5.21E10Ω

3.16E11Ω

1.04E11Ω

Low ResistanceState

100uA Write Compliance Current1.75E3Ω

4.62E3Ω

1.05E4Ω

2.90E3Ω

High ResistanceState

100uA Write Compliance Current5.64E5Ω

5.80E10Ω

2.50E11Ω

8.22E10Ω

Low ResistanceState

1mA Write Compliance Current2.58E2Ω

3.04E2Ω

3.44E2Ω

2.67E1Ω

High ResistanceState

1mA Write Compliance Current2.02E4Ω

9.08E4Ω

2.97E5Ω

7.89E4Ω

W (Tungsten) Raw Die

Characteristic Condition Min Typ Max Std

Forward AdaptationThreshold

DC / quasi-static0.150V

0.258V

0.350V

0.049V

Reverse AdaptationThreshold

DC / quasi-static–0.270V

–0.108V

–0.050V

0.057V

Cycle Endurance1.5 Vpp, 500 Hz sine wave, 50 kΩSeries resistor

50M 100M 5B

Low Resistance State 100nA Write Compliance Current1.04E6Ω

1.38E6Ω

2.16E6Ω

3.01E5Ω

High Resistance State 100nA Write Compliance Current4.01E6Ω

8.17E6Ω

1.72E7Ω

3.77E6Ω

Low Resistance State 1uA Write Compliance Current1.50E5Ω

4.67E5Ω

1.30E6Ω

3.09E5Ω

High Resistance State 1uA Write Compliance Current5.39E6Ω

1.40E7Ω

5.40E7Ω

1.40E7Ω

Low Resistance State 10uA Write Compliance Current2.66E4Ω

6.74E4Ω

1.72E5Ω

4.62E4Ω

High Resistance State 10uA Write Compliance Current2.36E6Ω

9.19E6Ω

2.04E7Ω

5.70E6Ω

Low Resistance State 100uA Write Compliance Current1.93E3Ω

7.86E3Ω

4.63E4Ω

1.30E4Ω

High Resistance State 100uA Write Compliance Current1.99E5Ω

2.71E6Ω

1.60E7Ω

4.70E6Ω

Low Resistance State 1mA Write Compliance Current2.65E2Ω

2.94E2Ω

3.53E2Ω

2.44E1Ω

High Resistance State 1mA Write Compliance Current1.50E4Ω

5.60E4Ω

1.13E5Ω

2.84E4Ω

Note:

1. Higher potentials can lead to phase-change operation. See Warnings section.2. High and low resistance states were measured from a DC erase sweep following a DC write sweep set to the

stated compliance current.3. We currently have limited data on cycling endurace. Higher voltages will reduce device lifespace.

AC Response of the Raw Die Devices

Memristor I-V CW Responses

Devices are sensitive to electrostatic discharge. Please use accepted methods for handling static-sensitive devicesincluding anti-static packaging, work-surfaces, wrist straps, etc. Do not touch the package leads without takingprecautions against electrostatic discharge. Devices will be irreversibly damaged if these precautions are notobserved.

Due to high open-circuit voltages, multi-meters will damage the devices.

Set a compliance current or use series resistance. A forward applied voltage will cause devices to enter a very low-resistance state and consequently burn out.

Warnings

Static Sensitive

Do not measure resistance with a multi-meter

Limit Device Current

Limit Applied Voltage

Formed devices typically change resistance between 0.1 and 0.75 Volts and are intended to be normally operatedunder 1V. High voltages may induce (reversible) phase-change or (non-reversible) damage.

The shipped raw die devices have not been formed. Packaged die may or may not have been completely formedwhen delivered, as only enough sinusoidal voltage was applied for quality control to make sure the internal wirebonding was successful or not. Forming entails applying a gradually increasing voltage, while limiting current, untilthe necessary conductive pathways have formed. There in no single correct way to form the devices, many differentprocedures will work, but may have different outcomes for device behavior.

Apply a sine wave input and gradually increase the amplitude of the sine wave until the device responds. To applythe sine wave to the device safely, build a circuit as shown below with the memristor in series with a current-limitingresistor greater than 1 kΩ. As shown in the following figure, use an oscilloscope to measure at points Px and Pyand place oscilloscope into “xy” mode. Apply a 1 to 100 Hz sine wave with an amplitude of 0.25 V amplitude.Gradually increase the voltage until a hysteresis loop is visible. You may need to continue on with higher voltagedepending on your current-limiting resistor to get the device to completely form even after the initial hysteresis loopappears. Decrease the voltage until the hysteresis loop disappears and then gradually increase the voltage againuntil a hysteresis loop re-appears. If the device had not previously been formed for you, the voltage at which thehysteresis loop reappears will be less than the voltage needed for forming.

Forming Method 2 Setup

An example of the type of waveform you can expect on Px and Py is shown in the figure below. Since the device isoperating in ion-conduction mode only, the voltage across the load responds by following the input waveform duringthe positive cycle, and during the negative-going erase cycle until the erase threshold causes the device resistanceto increase (the ‘spike’ in the negative portion of Py waveform).

Device Forming

Forming Method 1

Ion-Conduction Mode

Ion-conduction mode cycling. The Py waveform allows observation of the device response to the input. The positiveportion of the input sine wave causes the device resistance to drop. The negative portion causes the deviceresistance to increase once the erase threshold is reached (shown by the ‘spike’ in the Py trace).

Watch online video here: https://vimeo.com/knowm/formingaknowmbs-af-wmemristor

As presented above in the DC Electrical Characteristics of the Raw Die Devices section and copied below, thefollowing precisely controlled forming procedure is the one we used for the raw die devices. You might come up witha similar procedure after testing various options and finding the best method. Note that this procedure may or maynot be optimal for the packaged devices.

1) Apply a sine wave with 0.6 V peak amplitude, 100 Hz, for 20 cycles to condition the devices.2) Apply a read - erase - read pulse sequence with the read pulses 500 ns width, and the amplitude of 200 mV; theerase pulse is 5 µs width, –1.5 V amplitude.3) Apply three consecutive cycles of R-W-R-E with all pulse widths 1 µs, write amplitude 900 mV, erase amplitude –1.2 V and read amplitudes of 200 mV.4) Apply a R-Wx20-R sequence with a reduced write amplitude (700 mV, 1 µs pulsewidth).5) Apply a R-Ex20-R with –1V, 1 µs amplitude.6) Repeat 4.7) Repeat 5.

Forming Method 2

Phase-Change Response

The memristor device has two main modes of operation: ion-conducting and phase-change and it can be put into astate that consists of a combination of the two modes. The hysteresis and incremental response will vary dependingon which mode the memristor is currently in.

Phase-change operation can only occur after the device has previously been operated at least once in the ionconduction mode because there is a permanent material change in the active layers that occurs upon ionconduction. To achieve phase change operation, the device is operated under higher voltage and current conditions.Typical phase-change device melt-quench operating procedures should be used to increase resistance when in thismode. Additionally, this mode allows single polarity operation, if desired. To get the device out of phase-changemode apply a short, higher voltage, melt and quench pulse.

The following figure is showing a phase-change response at the higher applied voltage on the erase side. The eraseside is typically where these devices do that the easiest. Sometimes on the positive V side, you may see somethingthat could be misinterpreted as the S-shape, but it is the ion motion and snap back due to formation of a conductionpathway via mass movement.

Device Response Current vs. Voltage

A word of caution when switching between phase-change and ion-conducting operational modes: the device can‘switch’ polarity in the ion conducting mode when the operational mode goes from phase-change back to ionconduction. This means that the voltage polarities needed at the electrodes in order to increase the resistance areopposite from what they were initially. The ion conduction polarity switch occurs especially if the phase changeoperation applied a positive potential pulse to the device top electrode. In this case, the ion-conducting mode willoperate as if the excess silver layer has moved towards the original bottom electrode. Application of pulses or a DCsweep to drive the silver back towards the top electrode will return the device to its original operating polarity.

This symbol is used internally at Knowm as it is easier to draw by hand and more accurately represents thedefinition of a memristor. As Leon Chua, the theoretical inventor of the memristor, has said:

“If it’s pinched its a memristor”-Dr. Leon Chua

Symbology

The bar signifies the electrode adjacent to the active chalcogenide layers. In the pristine device, this is the layerfurthest away from the original Ag layer. While in ion-conduction mode, a voltage applied across the device with thelower-potential end on the side of the bar, will drive the device into a high conductance state.

Device Symbol

We believe the natural direction for conductance change in a memristor should defined as increasing, as this is howmost adaptive dissipative systems in Nature evolve over time. By convention, a bar signifies the lower potential endin other devices like diodes. Furthermore, from an electro-chemistry merged with a semiconductor devicesperspective, we believe having the bar on the cathode makes the most since this is where reduction occurs.

Watch online video here: https://vimeo.com/knowm/knowmmemristorsymbolconventions

Knowm Memristor Symbol Conventions from Knowm on Vimeo.

Memristor symbol files can be downloaded here:

1. Memristor Symbol Knowm 400 px (png)2. Memristor Symbol Knowm 200 px (png)3. Memristor Symbol Knowm 100 px (png)4. Memristor Symbol Knowm 64 px (png)5. Memristor Symbol Knowm (svg)

Kris Campbell is both a scientist and an engineer, with a passion for creating and building new device technologies.She loves everything about chemistry and believes that a solid foundation in chemistry is one of the best things astudent in any science or engineering discipline can give to themselves. With it comes an appreciation for all thingsin nature and in the science surrounding technology. As both a chemist and an electrical engineer, she has had a

Dr. Kris Campbell at Boise State University

Device Inventor

range of professional experiences from electro-optic circuit design, and nonvolatile memory device technologydevelopment and fabrication, to teaching. She is currently an Associate Professor in the electrical and computerengineering department at Boise State University. Kris Campbell has over 10 years of electrical engineering industryexperience in the areas of microfabrication and optoelectronic circuit design. Kris has published over 20 papers inpeer reviewed journals, 2 book chapters, and several conference proceedings. Her current research interests are inthe areas of reconfigurable electronics based on ion-conducting chalcogenide glasses, and new electronic memorytechnologies based on ion-conduction and electron spin zero-field splitting.

University of California, Davis Physical Chemistry Ph.D.University of Nevada, Las Vegas Electrical Engineering B.S.E.E.

I have been asked a number of times how the memristors I designed for Knowm Inc. differ from HP’s memristor. Forevery comment I make, I have to stress that I have not personally tested HP’s memristors. Their actualelectrical properties could deviate from my own experience fabricating similar devices and from what I’ve read andheard from others. The problem with relying on second-hand reports is that the electrical properties of a memristorcan be significantly altered by how the device was previously tested or handled. I don’t know how sensitive HP’sdevices are or how easily they can be damaged. Sometimes one can observe erratic behavior due to previousmishandling of the device, so without knowing the exact history you can never be 100% sure. Given the above, myobservations from similar devices that I have fabricated are congruent with what others, who have tested HP’smemristors, also claim.

They have been described as erratic, with high switching voltages, high forming voltages, and non-repeatability fromdevice-to-device. The published literature for HP’s devices claim it is comprised of a metal oxide material that relieson the migration of oxygen vacancies to alter the resistance of the device. This oxygen vacancy migration is relatedto the volume of the device active layer and is thus considered a ‘bulk’ migration, not necessarily a filament throughthe device.

However, that being said, there are also patents (by other companies researching metal-oxide resistive RAM) thatsupport the development of a device structure using oxygen vacancies that form a filamentary conduction path orpercolation path (e.g., US8648418, US9012881B2,US20130341584A1). I do not know if HP is implementing any ofthese types of designs, or even perhaps something new. Other types of metal-oxide devices are described in thepatent literature to address the erratic switching issues, and the high forming voltages (US8062918B2,US20140054531A1, US8441838). Even more patents address molecular control of the oxygen vacancies throughmaterial design and device structure (e.g., US8420478B2). There are hundreds of patents that address theseissues, and what we reference above can serve to get anyone that is really interested in digging deeper a startingpoint

From my own experience with some of the metal-oxide devices, such as HfOx, I have found that oxides are verydifficult to design a stable device with. First, it is very difficult to control the concentration of oxygen within a film.Fabrication techniques become complicated every step of the way. Keeping oxygen out of the device afterfabrication is also challenging. I have first hand observed device-to-device variation in metal oxide devices that I’vefabricated, with high switching voltages, erratic behavior within the same device, and poor state retention.

The Trouble with Oxide-Based Memristors

By Kris Campbell

My opinion is that it is difficult to fabricate devices with metal-oxides since it is difficult to control or regulate theconcentration of oxygen in the device. This means that every time one tries to fabricate devices, they may getdifferent results due to any small change in the way the wafers were processed. This is an exercise in frustration.Different film deposition methods will produce devices with drastically different electrical characteristics. I do not useoxides for this reason.

Benefits that I’ve heard attributed to oxide-based memristors include that they would be compatible with CMOSprocessing or that they can withstand higher temperatures during fabrication. I disagree with the compatibilityanalogy since the metals of the metal oxides may still pose a problem as a contaminant in a clean room, especiallyif the materials have been specially designed to address a particular problem. Compatibility can be addressedthrough circuit designs that place the memristor fabrication as a back-end-of-line (final) processing step. The higherprocessing temperatures could certainly be true, but through back-end-of-line processing, this isn’t an issue.

The Knowm memristor devices do not use oxygen vacancy migration to change the device resistance. The Knowmmemristor uses layers of chalcogenide materials. Due to the amorphous nature of the materials–meaning they aredisordered and not affected by impurities due to Fermi level pinning, they can take on impurities such as oxygenwith little to no observable effect on the electrical properties. The devices rely on both a phase-change and afilamentary conduction mechanism, with the filamentary conduction mechanism dominating during “normal” low-voltage operation. The active layers do not have a need for precise thicknesses and they can be deposited in avariety of ways, including the simple technique of sputtering. Even with fabrication in the university clean roomwhere pieces of equipment are in constant flux, even with unexperienced undergraduate students fabricating thedevices, they still behave with similar electrical properties every time. The switching voltages are low, the formingvoltage is low, device switching is consistent, and fabrication is simple.

Via Knowm’s collaboration with Boise State University, we offer the world’s first CMOS Back End Of Line (BEOL)Memristor service. We are offering this service to lower the barriers to memristive technology and help jump-startthe memristor-based computing era. Multiple memristor types are possible covering a range of threshold voltages,resistance ranges, switching speeds, data retention, and cycling durability. Services includes layout design, allmicrofabrication steps for device fabrication, BEOL processing on CMOS die or wafers, wire bonding andpackaging. Device electrical characterization possible over a frequency range of DC – 40 GHz, a temperature rangeof 4.2 K to 400 K, an optical excitation range of 190 nm to 1000 nm, and applied magnetic field from 0 to 5000 G.Please contact us for more information.

BEOL Process

Please contact us for design kits for Cadence, Electric, Lasi, etc. to integrate the memristors with your designs.

CMOS+Memristor BEOL Service

NOTE: If you would like to use this model and/or further develop it, please feel free to do so. First appearance articlesource: AHaH Computing–From Metastable Switches to Attractors to Machine Learning, Nugent MA, Molter TW(2014) AHaH Computing–From Metastable Switches to Attractors to Machine Learning. PLoSONE9(2):e85175.doi:10.1371/journal.pone.0085175

Many memristive materials have recently been reported, and the trend continues. Memristor models are also beingdeveloped and incrementally improved upon. Our generalized metastable switch (MSS) memristor model is anaccurate model that captures the behavior of memristors at a level of abstraction sufficient to enable efficient circuitsimulations while simultaneously describing a wide a range of possible devices. A MSS is an idealized two-stateelement that switches probabilistically between its two states as a function of applied voltage bias and temperature.A memristor is modeled by a collection of MSSs evolving in time, which captures the memory-enabling hysteresisbehavior. In our semi-empirical model, the total current through the device comes from both a memory-dependent(MSS) current component, , and a Schottky diode current, in parallel:

, where . A value of represents a device that contains no Schottky diode effects. The Schottkydiode effect accounts for the exponential behavior found in many devices and allows for the accurate modeling ofthat effect, which the MSS component cannot capture alone. The MSS model can be made more complex toaccount for failure modes, for example by making the MSS state potentials temporally variable. Multiple MSSmodels with different state potentials can be combined in parallel or series to model increasingly more complex statesystems.

Frankly, existing memristor models weren’t all that great for the type of devices we are interested in using to buildThermodynamic-RAM, a neuromorphic co-processor based on the principles of AHaH Computing. We also werefaced with the problem that most memristors we have seen display some measure of stochastic behavior, and manymodel assume a deterministic device. We felt that a stochastic model was a more natural fit to actual deviceproperties. An effective memristive device model for our use case should satisfy several requirements. It shouldaccurately model the device behavior, it should be computationally efficient, and it should model as manydifferent devices as possible.

By adjusting the free variables in the generalized memristive device model and comparing the subsequent current-voltage hysteresis loops to four real world memristive device I–V data, matching model parameters were determinedas shown in Table 1. The devices include the Knowm Ag-chalcogenide, , , and devices, and they represent a wide spectrum of incremental memristive devices found in recent publicationsexhibiting diverse characteristics.

General memristive device model parameters fit to various devices. The devices used to test our generalmemristive device model include the Knowm Ag-chalcogenide 1 and 2, , , and devices. The parameters in this table were determined by comparing the model response to a simulated sinusoidalor triangle-wave voltage to real I–V data of physical devices.

MSS Model

Im Is

I = ϕ (V , t) + (1 − ϕ) (V)Im Is

ϕ ∈ [0, 1] ϕ = 1

Why Another Memristor Model?

A I S Tg5 n5 b60 e30 G S Te2 b2 e5 WOx

A I S Tg5 n5 b60 e30 G S Te2 b2 e5 WOx

Device[ms] [mS] [mS] [V] [V]

Knowm 1 0.06 3.0 0.01 0.40 0.30 1 - - - -

Knowm 2 0.1 1.125 0.67 0.27 0.37 1 - - - -

0.15 40 10 .23 .25 1 - - - -

0.42 .12 1.2 .9 0.6 0.7 3.0 3.0

0.80 .025 0.004 0.8 1.0 .55 .85 6.2

Knowm 1 and 2

Sine Triangle Triangle Triangle

Zhang 2014 Li 2013 Chang 2011

The model can be used in basic circuit simulations as shown in the following table.

t GA GB VA VB ϕ α f βf αr β

A I S Tg5 n5 b60 e30

G S Te2 b2 e55× 10−3

5× 10−3

WOx1× 10−9

22× 10−9

A I S Tg5 n5 b60 e30 G S Te2 b2 e5 WOx

The Model in Action

Pulse ResponseResistance

Pulse ResponseCurrent

Resistance vs. SineVoltage

Two Memristors inSeries

The AHaH rule naturally forms decision boundaries that maximize the margin between data distributions. Weightspace plots show the initial weight coordinate (green circle), the final weight coordinate (red circle) and the pathbetween (blue line). Evolution of weights from a random normal initialization to attractor basins can be clearly seenfor the circuit model.

AHaH Node Circuit Circuit Simulation x 50

Generalized Metastable Switch Memristive Device Model

In our proposed semi-empirical model, the total current through the device comes from both a memory-dependentcurrent component, , and a Schottky diode current, in parallel:

, where . A value of represents a device that contains no Schottky diode effects.

Im Is

I = ϕ (V , t) + (1 − ϕ) (V)Im Is

ϕ ∈ [0, 1] ϕ = 1

The Schottky component, , follows from the fact that many memristive devices contain a Schottky barrierformed at a metal–semiconductor junction. The Schottky component is modeled by forward bias and reverse biascomponents as follows:

, where , , , and are positive valued parameters setting the exponential behavior of the forward andreverse biases exponential current flow across the Schottky barrier.

The memory component of our model, , arises from the notion that memristors can be represented as acollection of conducting channels that switch between states of differing resistance. The channels could beformed from molecular switches, atoms, ions, nanoparticles or more complex composite structures. Modification ofdevice resistance is attained through the application of an external voltage gradient that causes the channels totransition between conducting and non-conducting states. As the number of channels increases, the memristor willbecome more incremental as it acquires the ability to access more states. By modifying the number of channels wemay cover a range of devices from binary to incremental. We treat each channel as a metastable switch (MSS)and the conductance of a collection of metastable switches capture the memory effect of the memristor. An MSSpossesses two states, and , separated by a potential energy barrier as shown below.

(V)Is

= −Is αf e Vβ f αr e− Vβ r

αf βf αr βr

Im

A B

Let the barrier potential be the reference potential . The probability that a single MSS will transition from the Bstate to the A state is given by , while the probability that the MSS will transition from the state to the state isgiven by . The transition probabilities are modeled as:

and

, where . Here, is the thermal voltage and is equal to approximately at , is the ratio of the time step period to the characteristic time scale of the device, , and

is the voltage across the switch. The probability is defined as the positive-going direction, so that a positiveapplied voltage increases the chances of occupying the A state. An MSS possesses utility in an electrical circuit asan adaptive element so long as these conductances differ. Each state has an intrinsic electrical conductance givenby and . The convention is that . Note that the logistic function is similar to thehyperbolic-sign function used in other memristive device models including the nonlinear ion-drift, theSimmons tunnel barrier, the threshold adaptive models, and physics-based models. Our use of the logisticfunction follows simply from the requirement that probabilities must be bounded between 0 and 1.

V = 0PA A B

PB

= α = αΓ (V , )PA1

1 + eβ(V− )VAVA

= α (1 − Γ (V , − ))PB VB

β = = (qkT VT )−1 VT 26 mV−1

T = 300 K α = Δttc

Δt tc VPA

GA GB >GB GA1

1+e−x

It’s worth reiterating at this point that the logistics function gives the probability between 0 and 1 of a MSS switchingstates and is dependent on the instantaneous voltage, , the time step, , of the simulation and the temperature,

, of the device.

Up until this point we have only considered a single MSS being in the or state and its probability of it changingstates given external stimuli. We now model a memristor as a collection of MSSs evolving in discrete time steps,

. The total memristor conductance is given by the sum over each MSS:

, where is the number of MSSs in the A state, is the number of MSSs in the state and are theintrinsic conductances of the MSSs respectively. At each time step some subpopulation of the MSSs in the statewill transition to the state, while some subpopulation in the B state will transition to the A state. Intuitively, a MSSis most likely to switch its state when the electrical field applied across it is near and above it’s switching thresholds

and . Since all MSSs are acting in parallel to model the entire memristor, it’s this combined populationstate that determine the device’s overall conductance at any given point in time. The memristor’s memory state isthus the collection of the individual states of all the MSSs. Since the model keeps track of the state that each MSS isin, it can easily determine the entire device’s conductance by a sum of products. The current through the deviceis thus the instantaneous voltage times the conductance, a.k.a Ohm’s Law.

V ΔtT

A BN

Δt

= +Gm NA GA NB GB

NA NB B ,GA GB

AB

VA VB N

The probability that MSSs will transition out of a population of MSSs is given by the binomial distribution:

, where is the probability a MSS will transition states given above by and , N is the number currently in the and state , and K is the value we’re solving for. You always are doing this twice, one for each pool of switches - and . As becomes large we may approximate the binomial distribution with a normal distribution:

, where and . Therefore at each time step we have two normal distributions defined by , , and , which is a function of instantaneous voltage, , the time step, , of the simulation and the

temperature, , of the device. These two distributions can be sampled to get a random number of MSSs switchingtheir states. Because the normal distribution is continuous, we round it to the nearest discrete value.

k n

B (k, n, p) =n!

k! (n − k)!pk (1 − p)n−k

p PA PBA BA B n

(μ, ) =σ 2e− (x−μ) 2

2σ 2

2πσ 2‾ ‾‾‾‾√

μ = np = np (1 − p)σ 2

NA NB PA PB V ΔtT

The change in the number of MSSs in each state is given by the contribution from the two random variables pickedfrom the two normal distributions:

, where and are the number of switches transitioning from the state to the state and vice versa.At each time step, we are calculating the state of the memristor given by the number of meta stable switches in the

and state, which was a function of the instantaneous voltage and the time step since the last simulated update.

The change in the memristor conductance is thus given by:

, and the memory-dependent current is thus:

, where is the voltage across the memristor during the time-step.

Reducing the number of MSSs in the model will reduce the averaging effects and cause the memristor to behave ina more stochastic way. Note that as the number of MSSs becomes small, the normal approximation to the binomialdistribution also breaks down. In this case, one could use the binomial distribution directly if so desired.

Δ = −NB NA→B NB→A

NA→B NB→A A B

A B

Δ = Δ ( − )Gm NB GB GA

= V ( + Δ )Im Gm Gm

V

Code

Memristor Device with Set Parameters

publicclassAgChalcBSAF2015extendsMSSMemristor

/**characteristictimescaleofthedevice*/privatestaticfinaldoubleTC=0.00006;

/**thenumberofMSS's*/privatestaticfinaldoubleN=1E6;privatestaticfinaldoubleG_OFF=.1E-5;privatestaticfinaldoubleG_ON=3E-3;

/**barrierpotentials*/privatestaticfinaldoubleVA=.4;privatestaticfinaldoubleVB=.3;

finalstaticdoubleschottkeyAlpha=0;//N/AfinalstaticdoubleschottkeyBeta=0;//N/Afinalstaticdoublephi=1;

/***Constructor**@parammemristance*/publicAgChalcBSAF2015(doublememristance)

super(memristance,TC,N,G_OFF,G_ON,VA,VB,phi,schottkeyAlpha,schottkeyBeta,schottkeyAlpha,schottkeyBeta);

for(inti=0;i<numTimeSteps;i++)

time[i]=(i+1)*timeStep;voltage[i]=amplitude*Math.sin(time[i]*2*Math.PI*frequency);current[i]=memristor.getCurrent(voltage[i])*1000;//inmAmemristor.dG(voltage[i],timeStep);resistance[i]=voltage[i]/current[i]*1000;//inOhm

publicclassMSSMemristor

privatefinalstaticRandomRANDOM=newRandom();

//CONSTANTS

/**Boltzman'sconstant*/privatestaticfinaldoubleK=1.3806503E-23;

/**electroncharge*/privatestaticfinaldoubleQ=1.60217646E-19;

Hysteresis

MSS Model

/**temperatureinKelvin*/privatestaticdoubleTEMP=298.0;

privatestaticdoubleBETA=Q/(K*TEMP);

/**thermalvoltage*/privatestaticdoubleVT=1.0/BETA;

//DEVICEPARAMETERS

/**characteristictimescaleofthedevice*/privatefinaldoubletc;

/**thenumberofMSS's*/privatefinaldoublen;

/**conductancecontributedfromeachMSS*/privatefinaldoubleGa;privatefinaldoubleGb;

/**between0and1,whatpercentageofthecurrentcomesfromtheMSSmodel?therestcomesfromschottkeybarrierexponentialcurrent*/privatefinaldoublephi;

privatefinaldoubleschottkeyAlpha;privatefinaldoubleschottkeyBeta;privatefinaldoubleschottkeyReverseAlpha;privatefinaldoubleschottkeyReverseBeta;

/**barrierpotentials*/privatefinaldoublevA;privatefinaldoublevB;

//DEVICEDYNAMICVARIABLES

/***NbisthenumberofMSS'sintheBstate,*thestateofthememristor,containedinthisonevariable*/privatedoubleNb;

/***Constructor*/publicMSSMemristor(doublememristance,doubletc,doublen,doublegOff,doublegOn,doublevA,doublevB,doublephi,doubleschottkeyAlpha,doubleschottkeyBeta,doubleschottkeyReverseAlpha,doubleschottkeyReverseBeta)

if(memristance>1.0||memristance<0.0)thrownewIllegalArgumentException("Memristancemustbebetween0and1,inclusive!!!");//initthedeviceinacertainstateNb=(1-memristance)*n;//note:(1-memristance)sothatamemristanceof1giveahigherresistancethanmemristanceof0.

this.tc=tc;this.n=n;this.Ga=gOff/n;this.Gb=gOn/n;this.vA=vA;this.vB=vB;this.phi=phi;this.schottkeyAlpha=schottkeyAlpha;this.schottkeyBeta=schottkeyBeta;this.schottkeyReverseAlpha=schottkeyReverseAlpha;

this.schottkeyReverseBeta=schottkeyReverseBeta;

/***updatedeviceconductance**@paramvoltage-theinstantaneousvoltage*@paramdt-howmuchtimepassedsincethelastupdate*/publicvoiddG(doublevoltage,doubledt)

//ProbabilitiesdoublePa=Pa(voltage,dt);doublePb=Pb(voltage,dt);

//Gaussianmeandoubleu_a=(n-Nb)*Pa;//Na*Padoubleu_b=(Nb)*Pb;

//Gaussianstandarddeviationdoublestdv_a=Math.sqrt((n-Nb)*Pa*(1-Pa));doublestdv_b=Math.sqrt((Nb)*Pb*(1-Pb));

//NumberofswitchesmakingatransistiondoubleNab=Math.round(normal(u_a,stdv_a));doubleNba=Math.round(normal(u_b,stdv_b));

//updatethestateofthememristor,containedinthisonevariableNb+=(Nab-Nba);if(Nb>n)Nb=n;elseif(Nb<0)Nb=0;

/***Equation21.TheprobabilitythattheMSSwilltransitionfromtheAstatetotheBstate**@paramvoltage-thevoltageacrossthedevice*@paramdt*@return*/publicdoublePa(doublev,doubledt)

doubleexponent=-1*(v-vA)/VT;doublealpha=dt/tc;doublePa=alpha/(1.0+Math.exp(exponent));

if(Pa>1.0)Pa=1.0;elseif(Pa<0.0)Pa=0.0;

returnPa;

/***Equation22.TheprobabilitythattheMSSwilltransitionfromtheBstatetotheAstate**@paramv*@paramdt

*@return*/publicdoublePb(doublev,doubledt)

doubleexponent=-1*(v+vB)/VT;doublealpha=dt/tc;doublePb=alpha*(1.0-1.0/(1.0+Math.exp(exponent)));

if(Pb>1.0)Pb=1.0;elseif(Pb<0.0)Pb=0.0;

returnPb;

/***Gaussian/normaldistribnution**@paramu*@paramstdv*@return*/privatedoublenormal(doubleu,doublestdv)

returnstdv*RANDOM.nextGaussian()+u;

/***Equation23.allvariablesareconstantexceptNb**@return*/publicdoublegetConductance()

returnNb*(Gb-Ga)+n*Ga;

publicdoublegetResistance()

return1.0/getConductance();

/***Getthecurrentthruthismemristor**@returnthecombinedMSSandSchottkeycurrent*/publicdoublegetCurrent(doublevoltage)

doublemssCurrent=voltage*getConductance();doubleschottkeyCurrent=getSchottkeyCurrent(voltage);

returnphi*mssCurrent+(1-phi)*schottkeyCurrent;

publicdoublegetSchottkeyCurrent(doublevoltage)

returnschottkeyReverseAlpha*(-1*Math.exp(-1*schottkeyReverseBeta*voltage))+schottkeyAlpha*(Math.exp(schottkeyBeta*voltage));

publicdoublegetSchottkeyCurrentWithPhi(doublevoltage)

return(1-phi)*schottkeyReverseAlpha*(-1*Math.exp(-1*schottkeyReverseBeta*voltage))+schottkeyAlpha*(Math.exp(schottkeyBeta*voltage));

publicvoidsetTemperature(doubletemperatureInKelvin)

TEMP=temperatureInKelvin;BETA=Q/(K*TEMP);VT=1.0/BETA;

The generalized metastable switch memristor model presented above does an excellent job at modeling thebehavior of a wide range of devices (Knowm Ag-chalcogenide, , , and ) undera diverse set of simulation conditions: sinusoidal and triangle drive waveforms, pulses, positive and negativevoltages, and two devices connected in series. The total current through the device comes from both a memory-dependent (MSS) current component, , and a Schottky diode current, in parallel, which allows for conciselyand intuitively capturing both the memory-dependent hysteresis and Schottky diode current behavior of a diverse setof devices. Furthermore, the model is computationally efficient and has served well in accurately describing devicebehavior and forming the basis for memristor-based neuromorphic hardware circuit simulations.

The above introduction is a modified excerpt from our 2014 PLoS One paper. To learn more about the theory ofAHaH computing and how memristive+CMOS circuits can be turned into self-learning computer architecture usingAHaH plasticity, download the paper at: AHaH Computing–From Metastable Switches to Attractors to MachineLearning.

Machine learning (ML) systems are composed of (usually large) numbers of adaptive weights. The goal of ML is toadapt the values of these weights based on exposure to data to optimize a function. This foundational objective ofML creates friction with modern methods of computing because every adaptation event must reduce to acommunication procedure between memory and processing separated by a distance. The power required tosimulate adaptive weights grows impractically large as the number of weights increases owing to the tremendousenergy consumed shuttling information back and forth. This is commonly knowm as the von Neumann Bottleneckand leads to what we call the The Adaptive Power Problem.

If current computing methods give us the (remarkable) ability to simulate any possible interaction or “adaptation”,why pursue any other method of computing? The answer is simple: Energy. Nature does not separate memory andprocessing. Rather, the act of memory access is the act of computing is the act of learning. As the memoryprocessing distance goes to zero, as the case in Nature and proposed neuromemristive architectures, the powerefficiency improves by orders of magnitude compared to von Neumann computers. If we want ML systems that areas powerful and efficient as Nature’s examples, then we must create a new type of hardware that is intrinsicallyadaptive. One could think of it as “Soft-Hardware”.

Model Conclusion

A I S Tg5 n5 b60 e30 G S Te2 b2 e5 WOx

Im Is

AHaH Computing

Neurobiological research has unearthed dozens of plasticity methods, and they all appear to be important to brainfunction. The more one digs into the literature, the more complex and confusing it becomes. How do we choose amethod, or combination of methods, to include in our soft-hardware? It is often said that problems cannot be solvedat the same level of thinking that created them. When we step back a level from the brain and we look at all ofNature, we find a viable solution. It is all around us in both biological and non-biological form.The solution is simple,ubiquitous, and it is provably universal.

We find it in rivers, trees, lighting and fungus, but we also find it deep within us. The air that we breath is coupled toour blood through thousands of bifurcating flow channels that form our lungs. Our brain is coupled to our bloodthrough thousands of bifurcating flow channels that form our circulatory system. The neurons in our brains arecoupled to each other through thousands of bifurcating flow channels that form our axons and dendrites. Notice apattern? It is in rivers, lightening, plants, mycelium networks, and even multi-cellular bacteria.

Nature’s Adaptive Building Block

At all scales of organization we see the same patterns built from the same building block. All of these processes arefundamentally related and can be described as free energy dissipating through adaptive containers or, moregenerally, as energy dissipation pathways competing for conducting resources. We call this mechanism or processAnti-Hebbian and Hebbian (AHaH) plasticity. It is computationally universal, but perhaps more importantly, it leads togeneral-purpose solutions in machine learning.

In the open-access peer-reviewed paper titled AHaH Computing–From Metastable Switches to Attractors toMachine Learning we detailed how the attractor points of a plasticity rule we call Anti-Hebbian and Hebbian(AHaH) plasticity are computationally complete logic functions as well as building blocks for machine learning

functions. We further demonstrate that AHaH plasticity can be attained from simple memristive circuitry attemptingto maximize circuit power dissipation in accordance with ideas in non-equilibrium Thermodynamics. Our goal is tolay a foundation for a new type of practical computing based on the configuration and repair of volatile switchingelements. We have traversed a large gap from volatile memristive devices to demonstrations of computationaluniversality and machine learning. In short, it has been demonstrated that:

1. AHaH plasticity emerges from the interaction of volatile competing energy dissipating pathways.2. AHaH plasticity leads to attractor states that can be used for universal computation and advanced machine

learning3. Neural nodes operating AHaH plasticity can be constructed from simple memristive circuits.

If you have any questions, please don’t hesitate to contact us via email at contact@knowm.org!

Knowm Inc. | Santa Fe, New Mexico, USA | Founded in 2015 | www.knowm.org | contact@knowm.org

Happy Memristing!