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KLM ElectronicsCDR ReviewCDR Review

16‐MAR‐2012

Gary Varner

16 MAR 2012

University of Hawai’i

OutlineOutline

• System requirements• Performance requirements (DAQ & trigger)Performance requirements (DAQ & trigger)• Technical implementation (readout)• Technical implementation (trigger)• Development statusDevelopment status• Summary and Schedule

3/16/2012 2Gary Varner, CDR Review – Scint. KLM Electronics

System Requirements (1)y q ( )• Operate within Belle‐II Trigger/DAQ environment

• >= 30kHz L1• >= 30kHz L1• Gbps fiber Tx/Rx• COPPER backend• Muon trigger• Muon trigger• Super‐KEKB clock/timing

SuperKEKB RF clock


System Requirements (2)y q• Belle2link for KLM


System Requirements (3)y q• Belle‐like timing primitives for GDL (trigger)

New KLMNew KLM trigger elements


Performance R i t (d )

h

Al Requirements (daq)• a/k/a “Si‐PMs”, MPPCs, SPADs

R 50

Al

DepletionRegion2 m

• Relatively inexpensive (standard silicon processing)

• Insensitive to magnetic fieldsUbias

2 m Substrate

• Insensitive to magnetic fields

• Noise is 500kHz − 2MHz not a problem: 5 p e threshold reduces rate to < 1kHz5 p.e. threshold reduces rate to < 1kHz while maintaining ~ 99% MIP efficiency

Results withResults with prototype ASIC

(TARGET)

Resolve individual p.e.


σ ~ 38.4ps

Performance Requirements (daq)• Waveform sampling to tune gain and MPPC response

q ( q)p g g p

after neutron damage (eKLM 14‐40Gy/10 yrs)

MPPC+preAmp+TARGET readout


Performance Requirements (daq)• High efficiency triggering, ns‐level timing

q ( q)

Setting threshold at 7.5 pixels: SiPMnoise neutron bg rate even after 10 years of SiPM irradiation

A small degradation of the MIP detection efficiency (99% 97% at 10 Belle-II years) isefficiency (99% 97% at 10 Belle II years) is due to smearing of the threshold by noise co-additon. Can be recovered by fitting the signal shape to waveform data in SRM FPGA.


p

Performance Requirements (trigger)• Merge streams to reduce # of links• Implement algorithms in a common triggerImplement algorithms in a common trigger module (UT3)

l h f d k( ) h• Trigger algorithm finds 2D track(s) in each projection


Design Constraints• Pre‐amps inside module

4x iterations of Carrier Card design

Temp sensor for each 15 ch.


Technical Status: architecture

112+32 DAQ fiber 36 FINESSE9 COPPER

transceivers

20k h l20k channels1.25k 16‐channel

Waveform sampling(TARGET) ASICs112+32 SRM

FTSW for programming/ i i / i

Trigger is common with RPC/barrel :Use a common


timing/trigger merge board

Technical Status: Pre‐amplifiers will be installed inside the detector will be installed inside the detector were tested for radiation hardness at ITEP proton (200 MeV) beam.

Photo-electron peaksobtained with

irradiated amplifier

A lifi i d i d

No effect was observed with radiation doses 5

Amplifiers gain and noise measured before (blue) and after (red) irradiation


No effect was observed with radiation doses 5 times higher than expected at Belle II.

Technical Status: ASIC (1)Initial TARGET design BLAB architecture

Die Overview

Pre‐production TARGET specifications

• 16 channels• 1‐2 GSa/s (cosmic, beam ~2.5GSa/s)12 bit di iti ti

p p

TSMC 0 25 CMOS

• 12‐bit digitization• Samples stored, digitized in groups of 32• 16k samples per channel (8us at 2GSa/s)


TSMC 0.25m CMOS process• Event sequencing/timing off‐chip [firmware]

Technical Status: ASIC (2)

• Sampling: 128 R di i t 64Sampling: 128 (2x 64) separate transfer lanes

Recording in one set 64, transferring other (“ping‐pong”)

Very similar to BLAB:• 2x more channels

• Storage: 64 x 512 (32k per ch )

• No precision timing requirement

Storage: 64 x 512 (32k per ch.)• Wilkinson ADC (64 at once)

6 / h l ( i ll l)3/16/2012 14Gary Varner, CDR Review – Scint. KLM Electronics

• 64 conv/channel (512 in parallel)

Technical Status: SRM (1)

Though looks very different, same frameworksame framework as iTOP readout


Technical Status: SRM (2)• Readout module prototype

DAC_MON(10x)

TARGET DC(10x – to merge (10x) ( gDACmon & TARGET DC)

SCROD

Re-package card as9U form factor


Technical Status: back‐end (1)Schem atic D raw ing of the C O PPER

F IF OF IF O

Local B us PC I B us

ctor

Sig

nals

F IN ESSEF IN ESSE B ridgeB ridge

M ezzanine C ards

F IF OF IF O

F IF OF IF O

F IF OF IF O

M em oryM em ory

C P UC P U

B ridgeDet

ec

F IN ESSEF IN ESSE

F IN ESSEF IN ESSE

F IN ESSEF IN ESSE

PC I M ezzanine C ards

U d d f

mDvwwsDlvOqcCmDvwwsDlvOCsDDcqC

C ontrolC ontrol B ridgeB ridge

Upgraded forBelle II

• COPPER (COmmon Pipelined Platform for Electronics Readout)• COPPER (COmmon Pipelined Platform for Electronics Readout)

• Used in Belle, J-PARC experiments

•FINESSE (Front-end Instrumentation Entity for Subdetector Specific Electronics)


N SS ( o t e d st u e tat o t ty o Subdetecto Spec c ect o cs)

Technical Status: back‐end (2)Belle2link

18

Technical Status: TriggerTrigger time‐stamping same as iTOP

A wide variety of established FPGA‐based TDCs with few ns resolution

Trigger 1-shot Width Adjust

100

T_1_TRGPower (T_1_TRG)

resolution

Need anyway for readout hit‐matching

10

Out

put W

idth

[ns]

19

matching 1

0 20 40 60 80 100 120

Discharge Current [uA]

Development Statusp• SRM firmware lagging (KEK/ITEP)

Some experience in Fermilab test beam– Some experience in Fermilab test beam– Operation of eKLM quadrant at KEKP i d d f d i• Pre‐amps, carrier cards ready for production (testing @ Virginia Tech)

• (pre‐)Production TARGET ASIC (Hawaii)• TARGET DAC daughtercard (Hawaii)TARGET_DAC daughtercard (Hawaii)• 9U VME version of SRM (Hawaii)

/f b b d ( d )• Trigger/fiber merge board (Indiana)• Trigger firmware (Virginia Tech)


gg ( g )

Summary and ScheduleSummary and Schedule

• Same basic infrastructure common to all• Same basic infrastructure common to all subdetector upgrades: common DAQ system

• Waveform sampling ASICs (“oscilloscope on a chip”) to set/monitor efficiencychip ) to set/monitor efficiency

• Prototypes under test (pre‐amps critical path)• Pre‐production prototypes end of 2012• Production in 2013‐2014Production in 2013 2014


Back‐up


Test assembly

Module-0 assembly Assembly and geometrical/

mechanical compatibility were tested in J l 2011 ith th fi t f ll i d l

yat KEKJuly 2011 with the first full size module

Assembly is really easy and fast: even two professors can assemble one module during ½ hour; cabling takes another 30 minutes


will be installed inside the detector

EKLM electronics Preamplifiers will be installed inside the detector were tested for radiation hardness at ITEP proton (200 MeV) beam.

Photo-electron peaksobtained with

irradiated amplifier

No effect was observed with radiation doses 5

Amplifiers gain and noise measured before (blue) and after (red) irradiation

No effect was observed with radiation doses 5 times higher than expected at Belle II.

DAQ motherboardMultiple ASICs readout checked during beam tests in Fermilab.Firmware development (to fit SiPM signals time, amplitude) was started.

Trigger/Timing Distribution (FTSW)gg gFrom Nakao‐san’s documentation:


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