Kit Thuc Tap PIC

NHN XT CA GIO VIN HNG DN ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. .................................................................................................Ngy ..thng.nm 2008 Gio vin hng dn

Thc s : L NH KHA

NHN XT CA GIO VIN PHN BIN ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. ................................................................................................. .................................................................................................Ngy ..thng.nm 2008 Gio vin phn bin

Thy : PHAN DUY ANH

Li cm nSau nhng nm hc ti trng,chng em c hc v tip thu nhiu kin thc mi t s ch bo tn tnh ca Qu Thy C, s gip ca bn b. y l khong thi gian y ngha. n tt nghip ra trng l nn tng quan trng v nh du mt bc ngoc mi trong cuc i ca chng em. Chng em xin gi li cm n chn thnh n Thy L nh Kha. Thy hng dn ti thc hin n tt nghip v cung cp cho ti nhiu kinh nghim qu bu. Chng em xin chn thnh cm n Qu Thy c khoa in T - Tin Hc v cc Cn b Cng nhn vin Trng Cao ng K Thut Cao Thng, to iu kin thun li ti c th hon thnh tt n tt nghip ny..

Sinh vin thc hin Trn Thnh Tm Nguyn Tin Ngha

LI NI U

Ngy nay Khoa hc K thut pht trin mnh m, cng vi s pht trin khng ngng ca cc ngnh k thut ni chung v k thut in t ni ring. Chng i su vo mi mc i sng hng ngy ca ngi dn. c bit s dng vi iu khin iu khin cc thit b dn dng v cc thit b cng nghip. Nm c tm quan trng , nhm chng em lm ti: KIT THC TP PIC cho cc bn sinh vin c cng c hc tp v thc hnh mn vi iu khin Pic. Nhng kin thc v nng lc t c trong qu trnh hc tp ti trng s c nh gi qua t bo v n tt nghip. V chng em c gng tn dng tt c nhng kin thc hc trng cng vi s tm ti nghin cu, c th hon thnh tt n tt nghip ny. Nhng kt qu nhng sn phm t c trong ngy hm nay tuy khng ln lao nhng n l thnh qu ca ba nm hc tp ti trng. L thnh cng u tin ca chng em trc khi ra trng. Do khong thi gian v kin thc cn hn hp, mc d chng em c gng hon thnh n tt nghip ny ng thi hn. Nn khng trnh khi nhng thiu xt mong Qu thy c thng cm. Chng em mong nhn c nhng kin ng gp tn tnh ca qu thy c v cc bn. Cui cng em xin chn thnh cm n qu thy c v cc bn .

n Tt Nghip Kha 2005 2008

GVHD:Thc s L nh Kha

MC LCCHNG 0 DN NHP11

PHN I KHO ST VI IU KHIN PIC 16F877A .............. 12CHNG I CU TRC PHN CNG CA 16F877A.................................... 13 1.1. S lt v vi iu khin PIC 16F877A .................................................................... 13 1.2. S lt v cc chn ca PIC 16F877A ..................................................................... 13 1.3.Mt s im c bit ca CPU ............................................................................ 18 1.3.1. Dao ng ..................................................................................................... 18 1.3.2. Reset ............................................................................................................ 19 1.3.3.MCLR(Master clear) .................................................................................... 19 1.3.4. Interrupts ..................................................................................................... 20 1.3.5. Ch ngun thp Sleep(Power down Mode) ........................................... 20 1.3.6. B nh thi gim st (Watch Dog Timer WDT) .................................... 21 1.4.T chc b nh ............................................................................................................. 22 1.4.1. B nh chng trnh ................................................................................... 22 1.4.2. B nh d liu ............................................................................................. 23 1.4.2.2. Vng thanh ghi chc nng t bit....................................................... 24 1.4.3. Cc thanh ghi chc nng c bit................................................................ 27 1.4.3.1.Thanh ghi trng thi(Status register): .................................................... 27 1.4.3.2. Thanh ghi ty chn (Option Reg_Register) ......................................... 28 1.4.3.3. Thanh ghi iu khin ngt INTCON .................................................... 29 1.4.3.4. Thanh ghi cho php ngt ngoi vi 1 ..................................................... 30 1.4.3.5. Thanh ghi c ca cc ngt ngoi vi 1 ................................................... 31 1.4.3.6. Thanh ghi cho php ngt ngoi vi 2 ..................................................... 32 1.4.3.7. Thanh ghi c ca cc ngt ngoi vi 2 ................................................... 33 1.4.4. PCL v PCLATH ........................................................................................ 33 1.4.5. Ngn xp Stack............................................................................................ 34 1.4.6. nh a ch trc tip v a ch gin tip, thanh ghi INF v FSR.............. 34 1.5. I/O port ............................................................................................................................ 35 1.5.1. Port B v thanh ghi TRIS B ........................................................................ 35 1.5.2. Port B v thanh ghi TRIS B ........................................................................ 37 1.5.3. Port C v thanh ghi TRIS C ........................................................................ 38 1.5.4. Port D v thanh ghi TRIS D ........................................................................ 40 1.5.5. Port E v thanh ghi TRIS E......................................................................... 40SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 4


GVHD:Thc s L nh Kha

CHNG II B NH THI................................................................................ 43 2.1. B nh thi timer 0 .................................................................................................... 43 2.1.1. Gii thiu..................................................................................................... 43 2.1.2. Hot ng ca b nh thi ......................................................................... 43 2.1.3. Ngt Timer 0 ............................................................................................... 43 2.1.4. S dng Timer 0 vi ngun xung clock ngoi............................................ 44 2.1.5. B tin nh t l 8 bit ca Timer 0 ............................................................. 44 2.2. B nh thi Timer 1................................................................................................... 44 2.2.1. Gii thiu..................................................................................................... 44 2.2.2. Thanh ghi iu khin Timer 1 ..................................................................... 45 2.2.3. Ch nh thi trong hot ng ca Timer 1 ........................................... 45 2.2.4. Ch m ................................................................................................. 45 2.2.5. Giao ng ring ca Timer 1....................................................................... 46 2.2.6. Ngt Timer 1 ............................................................................................... 46 2.3. B nh thi Timer 2................................................................................................... 46 2.3.1. Gii thiu .................................................................................................... 46 2.3.2. Thanh ghi iu khin T2CON..................................................................... 47 2.3.3. Xa cc b t l............................................................................................ 47 2.3.4. Ngun xung clock cho Timer 2................................................................... 47 2.3.5. Thanh ghi TMR2 v PR2 ............................................................................ 47 2.3.6. Tn hiu bo trng thi cn bng ................................................................. 47 2.3.7. Ch ng .................................................................................................. 48 CHNG III MODULE CCP ................................................................................. 49 3.1. Gii thiu ...................................................................................................................... 49 3.2. Thanh ghi iu khin module CCP ........................................................................... 49 3.3. Ch Capture ............................................................................................................ 50 3.3.1. B nh t l ca CCP.................................................................................. 50 3.4. Ch Compare .......................................................................................................... 51 3.5. Ch iu bin xung PWM..................................................................................... 51 3.5.1. Chu k PWM............................................................................................... 51 3.5.2.Chu k nhim v ca PWM ......................................................................... 52 3.5.3. Ci t hot ng cho PWM ....................................................................... 52 3.5.4. Module MSSP ............................................................................................. 54

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

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GVHD:Thc s L nh Kha

CHNG IV B BIN I ADC 10 BIT............................................................. 55 4.1. Gii thiu module ADC 10 bit .................................................................................. 55 4.2. Cc thanh ghi iu khin ............................................................................................ 55 4.3. Hot ng ca Module ADC ..................................................................................... 57 4.4.Thi gian ly mu......................................................................................................... 58 4.5. La chn xung clock cho bin i ADC .................................................................. 58 4.6. Cu hnh cc chn Analog.......................................................................................... 59 4.7. Chuyn i ADC ......................................................................................................... 59 4.8. Hot ng ca module ADC trong ch ng ....................................................... 60 4.9. nh hng ca Reset .................................................................................................. 60 CHNG V IN TH THAM CHIU V CC B SO SNH IN ......... 61 5.1. Module Comparator .................................................................................................... 61 5.1.1. Gii thiu v module comparator................................................................ 61 5.1.2. Ci t ch cho b so snh ..................................................................... 61 5.1.3. Ngun tham chiu ca b so snh............................................................... 63 5.1.3.1. Tn hiu in p tham chiu ngoi ....................................................... 63 5.1.3.2. Tn hiu in p tham chiu ni ........................................................... 63 5.1.4. Thi gian p ng ...................................................................................... 63 5.1.5. Tn hiu ng ra ca b so snh.................................................................... 63 5.1.6. Ngt ca cc b so snh .............................................................................. 64 5.1.7. Hot ng ca cc b so snh trong ch ng ......................................... 64 5.1.8. nh hng ca Reset................................................................................... 64 5.2. Module in p tham chiu ........................................................................................ 64 5.2.1. Gii thiu module in p tham chiu ........................................................ 64 5.2.2. Thanh ghi iu khin CVRCON ................................................................. 65 5.2.3. chnh xc ca in p tham chiu ......................................................... 66 5.2.4. Hot ng ca module VREF trong ch ng ......................................... 66 5.2.5. Trng thi ca module khi Reset................................................................. 66 5.2.6. S dng module vi cc mch ngoi .......................................................... 66

PHN II CC THNH PHN CA KIT THC TP PIC 16F877A ................................................................................... 67


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GVHD:Thc s L nh Kha

CHNG I

HIN TH LED N....................................................................... 68

1.1. Gii thiu chung ......................................................................................................... 68 1.2. Mch nguyn l ........................................................................................................... 69 CHNG II HIN TH LED 7 ON................................................................. 70 2.1. Cc khi nim c bn ................................................................................................. 70 2.2. Kt ni vi vi iu khin ............................................................................................ 71 2.3. Giao tip vi iu khin vi nhiu led 7 on ........................................................... 72 2.4. Lu gii thut ......................................................................................................... 74 2.5.Mch nguyn l ............................................................................................................ 75 CHNG III N GIAO THNG ........................................................................ 76 3.1. Gii thiu ..................................................................................................................... 76 3.2. S nguyn l ........................................................................................................... 77 3.3. Lu gii thut ......................................................................................................... 78 CHNG IV LED MA TRN ................................................................................ 79 4.1. Hin th led ma trn ..................................................................................................... 79 4.1.1. Gii thiu..................................................................................................... 79 5.1.2. Led ma trn 8x8........................................................................................... 79 4.2. Phng php hin th bng IC cht........................................................................... 80 4.2.1. Cht hng .................................................................................................... 81 4.2.2. Cht ct ....................................................................................................... 81 4.3. Phng php dng thanh ghi dch............................................................................. 82 4.3.1. Qut hng .................................................................................................... 82 4.3.1.1. Gii thiu chung v phng php qut hng..................................... 82 4.3.1.2. Qu trnh thc hin qut hng ........................................................... 83 4.3.1.3. V d .................................................................................................. 83 4.3.2. Qut ct ....................................................................................................... 84 4.3.2.1. Gii thiu chung v phng php qut ct........................................ 84 4.3.2.2. Qu trnh thc hin qut ct .............................................................. 83 4.3.2.3. V d ........................................................................................................... 84 4.4. Mch nguyn l ........................................................................................................... 86 CHNG V LCD .................................................................................................... 87


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GVHD:Thc s L nh Kha

5.1. Gii thiu chung v LCD .......................................................................................... 87 5.1.1. Cc thanh ghi............................................................................................... 89 5.1.2. C bo bn BF............................................................................................. 90 5.1.3. B m a ch AC ...................................................................................... 90 5.1.4. Vng RAM hin th DDRAM..................................................................... 90 5.1.5. Vng ROM cha k t CGROM ................................................................ 91 5.1.6. Vng RAM cha k t ha CGRAM .................................................... 92 5.2. Tp lnh ca LCD ....................................................................................................... 94 5.3. Khi to LCD .............................................................................................................. 97 5.3.1. Mch khi to bn trong chip HD44780..................................................... 97 5.3.2. Khi to bng lnh ...................................................................................... 97 5.4. Lu gii thut ......................................................................................................... 99 5.5. Mch nguyn l ......................................................................................................... 100 CHNG VI ADC.................................................................................................. 101 6.1. Gii thiu v module ADC ...................................................................................... 101 6.1.1. C bn v ADC ........................................................................................ 101 6.1.2. ADC trong PIC 16F877A.......................................................................... 102 6.2. S nguyn l ......................................................................................................... 103 CHNG VII BN PHM GIAO TIP LCD.................................................... 104 7.1. Keypad v nguyn l hot ng ............................................................................. 104 7.2. Keypad giao tip vi LCD ....................................................................................... 104 7.3. S gii thut ......................................................................................................... 106 CHNG VIII GIAO TIP I2C........................................................................ 107

8.1. Gii thiu chung v I2C .......................................................................................... 107 8.1.1. c im giao tip I2C.............................................................................. 107 8.1.2. START and STOP conditions................................................................... 109 8.1.3. nh dng d liu truyn........................................................................... 109 8.1.4. nh dng a ch thit b .......................................................................... 111 8.1.5. Truyn d liu trn bus I2C ...................................................................... 112 8.1.6. Ch Multi-Master ................................................................................. 113 8.2. Module I2C Trong Vi iu Khin PIC ....................................................................... 113 8.2.1. c im phn cng ca PIC16F877A.................................................... 113 8.2.2. Cch thc s dng Module I2C trong CCS .............................................. 114


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GVHD:Thc s L nh Kha

8.2.3. EEPROM 24C04 ....................................................................................... 115 8.2.3.1. Hnh dng......................................................................................... 115 8.2.3.2. S cu to.................................................................................... 115 8.2.3.3. S chn .............................................................................................. 115 8.3. Mch nguyn l ........................................................................................................ 117 CHNG IX O NHIT DNG LM35 ...................................................... 118 9.1. Gii thiu .................................................................................................................... 118 9.2. Mt s c tnh c bn ca LM35........................................................................... 118 9.3. Mch nguyn l ....................................................................................................... 119

PHN III CC BI TP THC HNH .................................. 120BI 1 HIN TH TRNG THI PORT TRN LED N .............................. 121 BI 2 HIN TH TRNG THI CC PORT V THAY I THI GIAN DELAY..123 BI 3 HIN TH NGY THNG NM SINH TRN LED 7 ........................... 125 BI 4 HIN TH NG H TRN LED 7 ........................................................ 127 BI 5 CHNG TRNH N GIAO THNG.................................................. 129 BI 6 CHY CH LED MA TRN.................................................................... 131 BI 7 HIN TH K T TRN LCD ................................................................. 133 BI 8 GIAO TIP BN PHM S HEX HIN TH LCD.135 BI 9 IU CHNH ADC HIN TH LED N .............................................. 137 BI 10 O NHIT .......................................................................................... 139

PHN VI GII CC BI TP THC HNH ........................ 141BI 1 HIN TH TRNG THI PORT TRN LED N .............................. 142 BI 2 HIN TH TRNG THI CC PORT V THAY I THI GIAN DELAY..144 BI 3 HIN TH NGY THNG NM SINH TRN LED 7 ........................... 146 BI 4 HIN TH NG H TRN LED 7 ..148 BI 5 CHNG TRNH N GIAO THNG.................................................. 150 BI 6 CHY CH LED MA TRN.................................................................... 152 BI 7 HIN TH K T TRN LCD ................................................................ 155 BI 8 GIAO TIP BN PHM S HEX HIN TH LCD.158 BI 9 IU CHNH ADC HIN TH LED N .............................................. 162


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GVHD:Thc s L nh Kha

BI 10 O NHIT .......................................................................................... 163

PHN VI

PH LC ............................................................ 167

Ph lc 1 : 16F877A.................................................................................. 168 Ph lc 2 : DEFS_16F877A. .................................................................... 175


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GVHD:Thc s L nh Kha

Chng 0 : DN NHPI. t vn : Ngy nay vi s pht trin ca cng nghip vi in t, k thut s cc h thng iu khin dn c t ng ha.Vi cc k thut tin tin nh vi x l, vi mch sc ng dng vo lnh vc iu khin, th cc h thng iu khin c kh th s, vi tc x l chm chm t chnh xc c thay th bng cc h thng iu khin t ng vi cc lnh chng trnh c thit lp trc. c th hc tt mn vi iu khin chng ta phi c thit b hc tp mt trong nhng thit b l kit thc tp, v c s ng ca khoa in T - Tin Hc Trng Cao ng K Thut Cao Thng. Nhm chng em quyt nh lm ti tt nghip: Kit Thc Tp Vi iu Khin Pic. II. Gii hn ti: Vi thi gian gn nm tun thc hin ti cng nh trnh chuyn mn c hn, chng em c gng ht sc hon thnh n ny nhng ch gii quyt c nhng vn sau: Led n. Hin th Led 7 on. n giao thng . Chy ch led ma trn. Hin th LCD. ADC Giao tip bn phm. o nhit dng LM35. III. Mc ch nghin cu : Mc ch trc ht khi thc hin ti ny l hon tt chng trnh mn hc iu kin ra trng. C th khi nghin cu ti l chng em mun pht huy nhng thnh qu ng dng ca vi iu khin to ra nhng sn phm cho cc bn sinh vin kha sau. Khng nhng th n cn l tp ti liu cho cc bn sinh vin tham kho. Ngoi ra qu trnh thc hin ti l mt c hi chng em t kim tra li nhng kin thc hc trng. ng thi pht huy tnh sng to, kh nng gii quyt mt vn theo nhu cu t ra. V y cng l dp chng em khng nh mnh trc khi ra trng tham gia vo cc hot ng sn xut ca x hi.


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GVHD:Thc s L nh Kha

PHN I

KHO ST VI IU KHIN PIC 16F877A

CHNG I

: CU TRC PHN CNG CA PIC16F877A

CHNG II : B NH THI CHNG III : MODULE CCP (Capture Compare PWM) CHNG IV : B BIN I ADC 10 BIT CHNG V : IN TH THAM CHIU V CC B SO SNH IN


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GVHD:Thc s L nh Kha

CHNG I : CU TRC PHN CNG CA PIC16F877A1.1 S lc v vi iu khin PIC16F877A: PIC 16F877A l dng PIC ph bin nht hin nay ( mnh v tnh nng, 40 chn, b nh cho hu ht cc ng dng thng thng). Cu trc tng qut ca PIC 16F877A nh sau: - 8 K Flash ROM. - 368 Bytes RAM. - 256 Bytes EEPROM. - 5 ports (A, B, C, D, E) vo ra vi tn hiu iu khin c lp. - 2 b nh thi 8 bits (Timer 0 v Timer 2). - Mt b nh thi 16 bits (Timer 1) c th hot ng trong ch tit kim nng lng (SLEEP MODE) vi ngun xung Clock ngoi. - 2 b CCP( Capture / Compare/ PWM). - 1 b bin i AD 10 bits, 8 ng vo. - 2 b so snh tng t (Compartor). - 1 b nh thi gim st (WatchDog Timer). - Mt cng song song 8 bits vi cc tn hiu iu khin. - Mt cng ni tip. - 15 ngun ngt. - C ch tit kim nng lng. - Np chng trnh bng cng ni tip ICSP(In-Circuit Serial Programming) - c ch to bng cng ngh CMOS - 35 tp lnh c di 14 bits. - Tn s hot ng ti a 20MHz. 1.2 S lc v cc chn ca PIC16F877A:


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GVHD:Thc s L nh Kha


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GVHD:Thc s L nh Kha


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GVHD:Thc s L nh Kha

PIC16F877A l h vi iu khin c 40 chn, mi chn c mt chc nng khc nhau.Trong c mt s chn a cng dng: mi chn c th hot ng nh mt ng xut nhp hoc l mt chn chc nng c bit dng giao tip vi cc thit b ngoi vi.


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GVHD:Thc s L nh Kha

S khi PIC16F877A.


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GVHD:Thc s L nh Kha

1.3 Mt s im c bit ca CPU: 1.3.1 Dao ng: PIC16F877A c th hot ng trong bn ch dao ng khc nhau:

Trong cc ch LP, XT v HS chng ta s dng thch anh dao ng ni vo cc chn OSC1 v OSC2 to dao ng.

Vic la chn t trong dao ng thch anh da vo bng sau:

Lu : T c gi tr ln s tng tnh n nh ca dao ng nhng cng lm tng thi gian khi ng.

Ch dao ng RC c s dng nh mt gii php tit kim trong cc ng dng khng cn s chnh xc v thi gian.

* Cch tnh chu k my: V d ta s dng thch anh 10Mhz. Khi : Tn s dao ng ca thch anh l Fosc = 10Mhz Chu k dao ng ca thch anh l Tosc = 1/Tosc= 1/10*106 (s)


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GVHD:Thc s L nh Kha

Chu k my: T_instruction = 4*Tosc = 4/10*106(s) = 0.4 s = 400 ns 1.3.2 Reset: PIC16F877A c th b reset bi nhiu nguyn nhn khc nhau nh:

1.3.3 MCLR : PIC16F877A c mt b lc nhiu phn MCLR . B lc nhiu ny s pht hin v b qua cc tn hiu nhiu. Ng vo MCLR trn chn 4 ca PIC16F877A. Khi a chn ny xung thp th cc thanh ghi bn trong VK s c ti nhng gi tr thch hp khi ng li h thng. (Lu : Reset do WDT khng lm chn MCLR xung mc thp).


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GVHD:Thc s L nh Kha

1.3.4 Interrupts: PIC16F877A c nhiu ngun ngt khc nhau. y l mt s ngt tiu biu : - Ngt ngoi xy ra trn chn INT. - Ngt do Timer0. - Ngt do Timer1. - Ngt do Timer2. - Ngt do thay i trng thi trn cc chn PortB. - Ngt so snh in th. - Ngt do Port song song. - Ngt USART. - Ngt nhn d liu. - Ngt truyn d liu . - Ngt chuyn i ADC. - Ngt mn hnh LCD. - Ngt hon tt ghi EEPROM. - Ngt module CCP. - Ngt Module SSP. * Cc thanh ghi chc nng ngt: INTCON, PIE1, PIR1, PIE2, PIR2 (cc thanh ghi ny s c nghin cu cc phn sau).

1.3.5 Ch ngun thp Sleep (Power down Mode) : y l ch hot ng ca VK khi lnh sleep c thc thi. Khi nu c cho php hot ng, b m ca WDT s b xa nhng WDT vn tip tc hot ng bit PD (STATUS ) c reset v khng, bit TO c set, oscillator ngng hot ng v cc PORT gi nguyn trng thi nh trc khi lnh sleep c thc thi.


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GVHD:Thc s L nh Kha

Do khi ch sleep dng cung cp cho VK l rt nh nn ta cn thc hin cc bc sau trc khi VK thc thi lnh sleep. a tt c cc chn v trng thi VDD hoc VSS. Cn m bo rng khng c mch ngoi vi no c iu khin bi dng in ca VK v dng in nh khng kh nng cung cp cho cc mch ngoi vi hot ng. Tm ngng hot ng ca khi A/D v khng cho php cc xung clock bn ngoi tc dng vo VK. chc nng in tr ko ln ca PORTB. Pin MCLR phi mc logic cao. 1.3.6 B nh thi gim st (Watch Dog Timer -WDT): Gi s bn vit mt chng trnh, bn mong i chng trnh ny s chy nu khng c g trc trc xy ra th n s khng bao gi dng li, nh vy bn phi lm mt vng lp khi chng trnh chy n im cui th n li quay tr v im bt u. Nhng m hy xem mt trng hp: Gi s chng trnh kim tra mt chn input, nu n ln mc cao th con Pic s tip tc kim tra mt chn input th hai c ln mc cao hay khng, nu chn input th hai khng ln mc cao, con Pic s ngi ch v n s ch thot ra khi ch ngi ca n nu chn input th hai ln mc cao. By gi hy xem mt trng hp khc, gi s nh bn vit mt chng trnh, bn compiled n thnh cng, v ngay c bn cho chy m phng tng bc, tng bc mt trn my tnh, bng MPLAB chng hn, c v nh mi chuyn u tt, bn em np vo con Pic. Sau mt thi gian chy th, con Pic thnh lnh b kt vo ni no trong chng trnh m khng th thot ra c trng thi hin ti. iu g l cn thit gii quyt hai trng hp trn, reset li hay vn cho n b kt khng thot ra c, l mc ch ca mch Watchdog. Mch Watchdog th khng phi l mi m g, c rt nhiu microprocessors v microcontrollers c mch Watchdog, nhng m n lm vic ra sao ? Bn trong con Pic c mt mch RC, mch ny cung cp 1 xung Clock c lp vi bt k xung Clock no cung cp cho Pic. Khi Watchdog Timer (vit tt l WDT) c cho php (enabled), n s m bt u t 00 v tng ln 1 cho n FFh, khi n tng t FFh n 00 ( FFh+1) th con Pic s b Reset bt k ang lm g, ch c 1 cch l ngn khng cho WDT m ti 00. Khi con Pic b kt khng th thot ra khi tnh trng hin ti th WDT vn tip tc m m khng b bt k iu g ngn cm n m ti FF v n FF+1, v vy n s reset con Pic lm cho chng trnh phi khi ng li t u. s dng WDT chng ta cn lm 3 vic. Th nht, cn thi gian bao lu reset WDT ? Th hai, lm sao xo WDT ? Cui cng, chng ta phi ni cho con Pic bit chng trnh cho php WDT hot ng.


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GVHD:Thc s L nh Kha

1.4 T chc b nh: PIC16F877A c tt c 3 khi b nh ring bit bao gm: B nh chng trnh, b nh d liu v b nh EEPROM. 1.4.1 B nh chng trnh: PIC16F877A c b m chng trnh di 13 bits c th nh a ch cho khong khng gian nh 8K x 14bits. Khng gian b nh ny c chia lm 8 trang, c a ch t 0005h n 1FFFh. Mi s truy cp ngoi vng khng gian nh ny s khng c tc dng. Ngoi ra, b nh chng trnh cn bao gm mt ngn xp (Stack) 8 mc. Vector Reset c t ti a ch 0000h v vector ngt c t ti a ch 0004h.


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GVHD:Thc s L nh Kha

1.4.2 B nh d liu: Bng cu trc b nh d liu P16F877A


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GVHD:Thc s L nh Kha

B nh d liu bao gm 4 Bank: Bank 0, Bank1, Bank2 v Bank3. Mi bank c dung lng 128 Bytes, bao gm vng Ram a mc ch (GPR) v vng thanh ghi chc nng c bit (SFR). Cc Bank ny c la chn bng 2 bit thanh ghi STATUS l RP0(Status) v RP1(Status).

1.4.2.1 Vng Ram a mc ch: Vng RAM a mc ch c chiu rng 8 bit v c th c truy nhp trc tip hoc gin tip thng qua thanh ghi FSR. Vng RAM a mc ch c phn phi cc Bank nh sau: - Bank 0: 96 Bytes t a ch 20h n a ch 7Fh. - Bank 1: 80 Bytes t a ch A0h n a ch EFh. - Bank 2: 96 Bytes t a ch 110h n a ch 16Fh. - Bank 3: 96 Bytes t a ch 190h n a ch 1EFh. 1.4.2.2 Vng thanh ghi chc nng c bit: Cc thanh ghi chc nng c bit c s dng bi b x l trung tm CPU hoc cc module ngoi vi iu khin hot ng ca VK. Cc thanh ghi chc nng c bit ny c chia lm 2 loi: loi th nht dng cho cc chc nng ca CPU, loi th 2 dng cho cc chc nng ngoi vi.


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GVHD:Thc s L nh Kha

Bng tm tt cc thanh ghi chc nng c bit:


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GVHD:Thc s L nh Kha


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GVHD:Thc s L nh Kha

1.4.3 Cc thanh ghi chc nng c bit: 1.4.3.1 Thanh ghi trng thi ( Status Register): Thanh ghi trng thi cha cc trng thi s hc ca b ALU, trng thi Reset v cc bit chn Bank ca b nh d liu.


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GVHD:Thc s L nh Kha

Bit 7

IRP: Bit la chn bank thanh ghi (S dng cho nh a ch gin tip). 1 = Bank 2, 3 (100h 1FFh ) 0 = Bank 0, 1 (00h FFh)

Bit 6 5 RP1 RP0: Bit la chn bank thanh ghi (Dng trong nh i ch trc tip). 11 = Bank 3 ( 180h 1FFh) 10 = Bank 2 (100h 17Fh) 01 = Bank 1 (80h FFh) 00 = Bank 0 (00h 7Fh) Each bank is 128 bytes Bit 4 TO: Bit bo hiu hot ng ca WDT. 1: Lnh xa WDT hoc Sleep xy ra. 0: WDT hot ng. Bit 3 PD: Bit bo cng sut thp ( Power down bit). 1: Sau khi ngun tng hoc c lnh xa WDT. 0: Thc thi lnh Sleep. Bit 2 Z: bit Zero 1: Khi kt qu ca mt php ton bng 0. 0: Khi kt qu ca mt php ton khc 0. Bit 1 DC: Digit Carry 1: C mt s nh c sinh ra bi php cng hoc php tr 4 bit thp. 0: Khng c s nh sinh ra. Bit 0 C: c nh (Carry Flag) 1: C mt s nh sinh ra bi php cng hoc php tr. 0: Khng c s nh sinh ra. 1.4.3.2 Thanh ghi ty chn (Option _Reg Register): Thanh ghi ty chn cha cc bit iu khin cu hnh cho cc cha nng nh: ngt ngoi, Timer 0 chc nng ko ln Vdd ca cc chn Port B, v thi gian ch ca WDT

Bit 7

RBPU : Bit cho php PORTB c ko ln ngun.

1: Khng cho php PORTB ko ln ngun. 0: Cho php PORTB ko ln ngun.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 28


GVHD:Thc s L nh Kha

Bit 6 INTEDG: Bit la chn cnh tc ng ngt (INTERRUPT EDGE) 1: Ngt s c tc ng bi cnh ln ca chn RB0/INT 0: Ngt s c tc ng bi cnh xung ca chn RB0/INT Bit 5 T0CS: Bit la chn ngun xung Clock cho Timer 0 1: Xung Clock cung cp bi ngun ngoi qua chn RA4/T0CKI 0: Xung Clock cung cp bi ngun dao ng ni. Bit 4 T0SE: Bit la chn cnh no ca xung clock tc ng ln timer 0 1: Cnh xung 0: Cnh ln Bit 3 PSA: Bit quyt nh tc m PS2:PS0 s tc ng ln Timer 0 hay WDT 1: Tc m PS2:PS0 s tc ng ln WDT 0: Tc m PS2:PS0 s tc ng ln Timer 0

Bit 2-0 PS2:PS0: Dng la chn tc m ca timer hay WDT Thi gian trn WDT 18 ms 36ms 72ms 144ms 288ms 576ms 1.1s 2.2s

1.4.3.3 Thanh ghi iu khin ngt INTCON (Interrupt Control Register):

Bit 7 GIE: Bit cho php ngt ton cc 1: Cho php ngt ton cc 0: Khng cho php ngt Bit 6 PEIE: Bit cho php ngt khi ghi vo EEPROM hon tt. 1: Cho php ngt ghi vo EEPROM hot ng 0: Khng cho php ngt ghi vo EEPROM hot ng


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GVHD:Thc s L nh Kha

Bit 5 TMR0IE: Bit cho php ngt khi timer 0 trn 1: Cho php ngt khi timer 0 trn 0: Khng cho php ngt khi timer 0 trn Bit 4 INTE: Bit cho php ngt ngoi vi trn chn RB0/INT 1: Cho php ngt ngoi vi 0: Khng cho php ngt ngoi vi Bit 3 RBIE: Cho php ngt khi trng thi PORTB thay i 1: Cho php 0: Khng cho php Bit 2 TMR0IF: C bo ngt Timer 0 1: Timer 0 trn 0: Timer 0 cha trn Bit 1 INTF: C bo ngt ngoi RB0/INT 1: C ngt 0: Khng xy ra ngt. Bit 0 RBIF: C bo ngt khi c thay i trng thi PORTB 1: C thay i 0: Khng c thay i xy ra trn PORTB 1.4.3.4 Thanh ghi cho php ngt ngoi vi 1(PIE1 Register):

Ch : Bit PEIE (INTCON) phi c set cho php bt k ngt ngai vi no xy ra. Bit 7 PSPIE: Bit cho php ngt c/ ghi Port song song 1: Cho php 0: Khng cho php Bit 6 ADIE: Bit cho php ngt chuyn i A/D 1: Cho php 0: Khng cho php Bit 5 RCIE: Bit cho php ngt nhn USART 1: Cho php 0: Khng cho php Bit 4 TXIE: Bit cho php ngt truyn USART 1: Cho phpSVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 30


GVHD:Thc s L nh Kha

0: Khng cho php Bit 3 SSPIE: Bit cho php ngt Port ni tip ng b 1: Cho php 0: Khng cho php Bit 2 CCP1IE: Bit cho php ngt module CCP1 1: Cho php ngt 0: Khng cho php Bit 1 TMR2IE: Bit cho php ngt xy ra khi TMR2 bng thanh ghi PR2 1: Cho php 0: Khng cho php Bit 0 TMR1IE: Bit cho php ngt trn TMR1 1: Cho php 0: Khng cho php 1.4.3.5 Thanh ghi c ca cc ngt ngoi vi 1:

Bit 7 PSPIF: C ngt c/ ghi ca Port song song 1: Mt hot ng c/ghi din ra (phi xa bng phn mm) 0: Khng c hot ng c/ghi. Bit 6 ADIF: C bo ngt chuyn i A/D 1: Mt qu trnh chuyn i A/D hon thnh 0: Chuyn i A/D cha hon tt Bit 5 RCIF: C bo ngt nhn USART 1: Buffer nhn USART y 0: Buffer nhn USART trng. Bit 4 TXIF: C bo ngt pht USART 1: Buffer truyn USART trng 0: Buffer truyn USART y Bit 3 SSPIF: C bo ngt port ni tip ng b (ngt SSP) 1: Ngt SSP xy ra v phi c xa bng phn mm trc khi tr li chng trnh chnh t chng trnh phc v ngt. 0: Khng c ngt xy ra Bit 2 CCP1IF: C bo ngt CCP1SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 31


GVHD:Thc s L nh Kha

Ch Capture (Bt gi): 1: Mt Capture thanh ghi TMR1 xy ra( phi c xa bng phn mm) 0: Khng xy ra Capture thanh ghi TMR1 Ch Compare ( So snh): 1: Khi cc gi tr so snh trong thanh ghi TMR1 c tha ( phi c xa bng phn mm) 0: Khi cc gi tr so snh trong thanh ghi TMR1 khng c tha Ch PWM: Khng s dng trong ch ny Bit 1 TMR2IF: C bo ngt xy ra khi gi tr trong thanh ghi TMR2 bng trong thanh ghi PR2 1: Gi tr trong thanh ghi TMR2 bng thanh ghi PR2 (phi c xa bng phn mm) 0: Gi tr trong thanh ghi TMR2 cha bng thanh ghi PR2 Bit 0 TMR1IF: C bo trn thanh ghi TMR1 1: Thanh ghi TMR1 trn (phi c xa bng phn mm) 0: Thanh ghi TMR1 cha trn 1.4.3.6 Thanh ghi cho php ngt ngoi vi 2:

Ch : Bit PEIE (INTCON) phi c set cho php bt k ngt ngai vi no xy ra. Bit 7,5,2,1 Unimplemented : read as 0

Bit 6 CMIE: Bit cho php ngt do b so snh in th 1: Cho php 0: Khng cho php Bit 4 EEIE: Bit cho php ngt do ghi EEPROM 1: Cho php 0: Khng cho php Bit 3 BCLIE: Bit cho php ngt do xung t bus 1: Cho php 0: Khng cho php Bit 0 CCP2IE: Cho php ngt module CCP2 1: Cho php 0: Khng cho phpSVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 32


GVHD:Thc s L nh Kha

1.4.3.7 Thanh ghi c ca cc ngt ngoi vi 2:

Bit 7,5,2,1

Unimplemented : read as 0

Bit 6 CMIF: C bo ngt do b so snh 1: Ng vo b so snh thay i (phi c xa bng phn mm) 0: Ng vo b so snh khng thay i. Bit 4 EEIF: C bo ngt ghi EEPROM 1: Ghi EEPROM hon tt (phi c xa bng phn mm) 0: Ghi EEPROM cha hon tt. Bit 3 BCLIF: C bo ngt do xung t bus 1: Xung t bus xut hin trong ch SSP 0: Khng c xung t bus xy ra Bit 0 CCP2IF: C bo ngt CPP2 Ch Capture (bt gi): 1: Mt s bt gi thanh ghi TMR1 xy ra (phi c xa bng phn mm) 0: Khng xy ra Capture thanh ghi TMR1 Ch Compare (So snh): 1: Mt thut ton so snh trong thanh ghi TMR1 xy ra (phi c xa bng phn mm) 0: Khng xy ra thut ton so snh 1.4.4 PCL v PCLATH: B m chng trnh PC (program counter) c di 13 bit, c dng cha a ch ca lnh c thc thi k tip. Byte thp cha trong thanh ghi PCL c th c/ghi mt cch trc tip. Cc bit cao (bit 12:8) cha trong thanh ghi PCLATH, khng th c nhng c th ghi gin tip bng cch s dng thanh ghi PCLATH. Khi c bt k s Reset no xy ra, cc bit cao ca b m chng trnh PC s b xa. Xem thm hai v d sau y hiu thm v hot ng ca b m chng trnh PC.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 33


GVHD:Thc s L nh Kha

1.4.5 Ngn xp Stack: Stack cho php 8 lnh gi chng trnh con v ngt hot ng. Stack cha a ch m chng trnh chnh s quay v thc hin t sau chng trnh con hay ngt. i vi PIC16F877A Stack c su 8 lp. Stack khng nm trong c b nh chng trnh ln b nh d liu. 1.4.6 a ch trc tip v a ch gin tip, thanh ghi INF v thanh ghi FSR: Thanh ghi INF khng phi l mt thanh ghi vt l. N cha gi tr ca thanh ghi c a ch nm thanh ghi FSR. V d: Thanh ghi ti a ch 10h c gi tr 5Ah Nu ta a 10h vo thanh ghi FSR th khi c thanh ghi INF ta s c gi tr 5Ah.

Data EEPROM v Flash Program Memory: EEPROM l b nh c kh nng c v ghi trong iu kin lm vic bnh thng (khi ngun Vdd khng i). B nh ny khng c nh a ch trc tip trong bn b nh m c nh a ch gin tip thng qua cc thanh ghi chc nng c bit: - EECON1 - EECON2 - EEDATA - EEDATH - EEADR - EEADRH Trong thanh ghi EEDATA lu gi gi tr 8 bit s c ghi hoc c. Thanh ghi EEADR lu gi a ch m chng ta mun ghi hoc c, thanh ghi ny c kh nng nh a ch cho 256 byte EEPROM. Thanh ghi EECON1 cha cc bit iu khin cn thanh ghi EECON2 c s dng khi to qu trnh ghi/c.


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GVHD:Thc s L nh Kha

1.5 I/O ports: 1.5.1 Port A v thanh ghi TRISA: Port A gm 6 chn t RA0 n RA5. Vic ghi gi tr vo thanh ghi TRISA s qui nh cc chn ca Port A l input hay output (nu l 1 th l input, l output nu l 0). Vic c thanh ghi Port A s c trng thi ca cc chn Port A. Vic ghi gi tr vo thanh ghi Port A s thay i trng thi ca cc chn Port A. Ring chn RA4 c tch hp chc nng l chn cung cp xung clock ngoi cho Timer 0 (RA4/T0CKI). Nhng chn khc ca Port A c a hp vi cc chn ng vo Analog ca ADC v chn ng vo in th so snh ca b so snh Comparator. Hot ng ca nhng chn ny c quy nh bng nhng bit tng ng trong cc thanh ghi ADCCON1 v CMCON1. Khi cc chn ca Port A c s dng lm ng vo Analog th cc bit trong thanh ghi TRISA phi c set bng 1.


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GVHD:Thc s L nh Kha

Chc nng ca cc chn Port A


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GVHD:Thc s L nh Kha

Bng tm tt cc thanh ghi lin quan n Port A

1.5.2 Port B v thanh ghi TRISB: Port B gm 8 chn t chn RB0-RB7. Vic ghi gi tr vo thanh ghi TRISB s quy nh cc chn ca Port B l input hay output (1: input, 0: output). Vic c thanh ghi Port B s c trng thi ca cc chn Port B. Vic ghi gi tr vo thanh ghi Port B s thay i trng thi ca cc chn Port B. Ba chn ca Port B c a hp vi chc nng In-Circuit Debugger v Low Voltage Programming function: RB3/PGM, RB6/PGC, RB7/PGD. Mi chn Port B c mt transistor ko ln Vdd. Chc nng ny hot ng khi bit RBPU (Option ) c xa. Chc nng ny s t ng c xa khi Port B c quy nh l input. Bn chn ca Port B t RB7 n RB4 c chc nng ngt khi trng thi chn Port B thay i (Khi Port B c quy nh l output th chc nng ny khng hot ng. Gi tr chn ca Port c so snh vi gi tr c lu trc , khi c s sai lch gia 2 gi tr ny ngt s xy ra vi c ngt RBIF (INTCON C2Vin0: Nu C2Vin+ < C2VinKhi C2INV = 1: 1: Nu C2Vin+ < C2Vin0: Nu C2Vin+ > C2VinBit 6 C1OUT : Bit ng ra b so snh 1 Khi C1INV = 0: 1: Nu C1Vin+ > C1Vin0: Nu C1Vin+ < C1VinKhi C1INV = 1: 1: Nu C1Vin+ < C1Vin0: Nu C1Vin+ > C1VinBit 5 C2INV : Bit o ng ra b so snh 2 1: Ng ra C2 o 0: Ng ra C2 khng o Bit 4 C1INV: Bit o ng ra b so snh 1 1: Ng ra C1 o 0: Ng ra C1 khng o Bit 3 CIS: Bit chuyn i ng vo b so snh Khi CM2:CM0 = 110: 1: C1 Vin- ni vi chn RA3/AN3 C2 Vin- ni vi chn RA2/AN2 0: C1 Vin- ni vi chn RA0/AN0 C1 Vin- ni vi chn RA1/AN1 Bit 2-0 CM2:CM0: Bit chn ch hot ng ca b so snh. 5.1.2 Ci t ch cho b so snh: C 8 ch hot ng ca b so snh, thanh ghi CMCON c s dng la chn nhng ch ny. Thanh ghi TRIS iu khin cc chn I/O ca b so snh trong mi ch . Nu ch so snh b thay i, ng ra ca b so snh s khng cn chnh xc na.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 61


GVHD:Thc s L nh Kha

Lu : Cc ngt do b so snh sinh ra nn c cm trong sut qu trnh thay i ch hot ng, nu khng cc ngt ngoi mun c th sinh ra.

Mt b so snh n c trnh by trong hnh bn cnh y, n cho chng ta bit s thay i trng thi logic ng ra tng ng vi trng thi tn hiu Analog ng vo. Khi VIN+ > VIN- th ng ra ln mc cao v ngc li. Ti nhng cnh ny ng ra khng bit chc chn.


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GVHD:Thc s L nh Kha

5.1.3 Ngun tham chiu ca b so snh: Mt ngun tham chiu ni hoc ngoi c th c s dng. Vic la chn ngun ni hay ngoi ty thuc vo ch hot ng ca b so snh. 5.1.3.1 Tn hiu in th tham chiu ngoi: Khi s dng ngun tham chiu ngoi, module so snh c th c cu hnh hot ng t mt hoc 2 ngun so snh khc nhau. in th so snh phi nm trong khong t Vss n Vdd v in p ny c th c a vo bt c mt chn no ca b so snh. 5.1.3.2 Tn hiu in th tham chiu ni: Module so snh cng cho php la chn mt in th so snh ni dng cho cc b so snh. Tn hiu tham chiu ni c s dng trong ch so snh CM2:CM0 = 010. Trong ch ny tn hiu so snh ni c a vo chn VIN+ ca 2 b so snh. 5.1.4 Thi gian p ng: Thi gian p ng l thi gian tnh t khi la chn mt in th tham chiu hoc mt tn hiu ng vo cho n khi c mt gi tr in p hp l ng ra. 5.1.5 Tn hiu ng ra ca cc b so snh: Tn hiu ng ra ca cc b so snh c c thng qua thanh ghi CMCON khi cc bit ny sn sng. Ng ra ca cc b so snh c th c ni trc tip vi cc chn xut nhp RA4 v RA5, cc chn ny phi c cu hnh l ng ra trong ch ny. Ch : - Khi cc chn port c cu hnh l cc chn ng vo Analog, vic c cc thanh ghi port s cho gi tr l 0 S khi chn ng ra ca cc b so snh


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GVHD:Thc s L nh Kha

5.1.6 Ngt ca cc b so snh: C ngt CMIF ca cc b so snh c bt ln khi gi tr ng ra ca cc b so snh thay i so vi gi tr ca bit CMxOUT. C ngt ny phi c xa bng phn mm mt ngt k tip c th xy ra. Ngoi ra mt ngt c th xy ra chng ta cn phi set cc bit CMIE, PEIE, GIE ln 1 5.1.7 Hot ng ca cc b so snh trong ch ng: Cc b so snh vn hot ng trong ch ng v cc ngt vn c th xy ra nu c cho php. Do cc ngt ny s nh thc VK. 5.1.8 nh hng ca Reset: Khi mt Reset thit b xy ra, n s buc thanh ghi CMCON v trng thi reset ca n, lm cho module ri vo ch tt, CM2:CM0 = 111. Cc thanh ghi lin quan n module so snh:

5.2 Module in p tham chiu : 5.2.1 Gii thiu module in th tham chiu Module in p tham chiu so snh c s dng ch yu vi module so snh khi cn s dng ngun so snh l ngun ni. Module in p tham chiu bao gm mt h thng 16 in tr, h thng in tr ny s cung cp cho chng ta mt in p tham chiu c th lp trnh c . Dy in tr ny c chia nh ra cung cp cho chng ta cc in th tham chiu khc nhau. S khi ca module in th so snh


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GVHD:Thc s L nh Kha

5.2.2 Thanh ghi iu khin CVRCON:

Bit 7 CVREN: Bit cho php CVR hot ng. 1: Cung cp ngun cho CVR 0: Ngng cp ngun cho CVR. Bit 6 CVROE: Cho php ng ra CVR 1: in p CVREF l ng ra trn chn RA2 0: in p CVREF khng kt ni vi chn RA2 Bit 5 CVRR: Bit la chn di gi tr hot ng ca CVREF 1: 0 n 0.75 CVRSRC, vi kch thc mi buc l CVRSRC/24 0: 0.25 CVRSRC n 0.75 CVRSRC, vi kch thuc bc l CVRSRC/32 Bit 4 Khng s dng, gi tr l 0 Bit 3-0 CVR3:CVR0: Cc bit la chn gi tr VREF ( 0 25ln/1s, n y chng ta quan st c mt hnh nh lin tc hin th trn mn hnh Led ma trn. 4.3.1.3.V d: Hin th ch B ln mn hnh Led ma trn(hng c tch cc mc 1, ct c tch cc mc 0).


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GVHD:Thc s L nh Kha

Hng 1

Ct 8 Hnh 4.8: Hin th ch B trn led ma trn dng phng php qut hng. D liu th nht c ga tr: 11111111 c a ra ct tch cc hng th nht (iu khin hng th nht cho ra gi tr l 1); d liu th hai c gi tr: 00001111 a ra ct, tch cc hng th hai; d liu th 3 c gi tr: 01110111 a ra ct, tch cc hng th 3; d liu th 4 c gi tr: 01110111 a ra ct, tch cc hng th 4; tip tc d liu hng th 5 c gi tr: 00001111 a ra ct, tch cc hng th 5; k tip l d liu ca hng th 6 c gi tr: 01110111 c a ra ct, tch cc hng th 6 ; d liu ca hng th 7 c gi tr: 01110111 a ra ct, tch cc hng th 7; d liu th 8 c gi tr: 00001111 a ra ct, tch cc hng th 8. Nh vy ton b d liu ca ch B c a ra hin th trn mn hnh Led ma trn. Qu trnh trn c din ra rt nhanh > 24ln/ 1s nn chng ta c cm gic n din ra mt cch ng thi nh m chng ta quan st c trn mn hnh Led ma trn l mt ch B lin tc. 4.3.2 Qut Ct: 4.3.2.1 Gii thiu chung v phng php qut ct. Phng php qut ct l phng php m trong mt khong thi gian xc nh ch cho mt ct c tch cc hin th trong khi cc ct khc u tt, cc ct c qut (tch cc) tun t cc khong thi gian k tip nhau c lp li nhiu ln vi tc > 25hnh/1s s cho ta mt hnh nh lin tc cn hin th ln trn mn hnh Led ma trn. 4.3.2.2 Qu trnh thc hin qut ct. D liu ca ct th nht c a ra hng sau tch cc ct th nht nh vy d liu ca ct th nht c hin th trn mn hnh Led ma trn, tip tc d liu ca ct th hai c a ra hng sau tch cc ct th hai lc ny d liu ca hng th hai c hin th trn mn hnh Led ma trn, c nh vy cho n d liu ca ct cui cng c a ra hng sau tch cc ct cui cng. C nh th qu trnh trn c lp i lp li > 24ln/1s, n y chng ta quan st c mt hnh nh lin tc hin th trn mn hnh Led ma trn. 4.3.2.3.V d: Hin th ch B ln mn hnh Led ma trn (hng c tch cc mc1, ct c tch cc mc 0).

Hng 8


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GVHD:Thc s L nh Kha

Hng 1

Hng 8

Ct 8

Ct 1 Hnh 4.9: Hin th ch B trn led ma trn dng phng php qut ct. D liu th nht c ga tr: 11111110 c a ra hng, tch cc ct th nht (iu khin ct th nht cho ra gi tr l 0); d liu th hai c gi tr: 10010010 a ra hng, tch cc ct th hai; d liu th 3 c gi tr: 10010010 a ra hng, tch cc ct th 3; d liu th 4 c gi tr: 10010010 a ra hng, tch cc ct th 4; tip tc liu hng th 5 c gi tr: 01101100 a ra hng, tch cc ct th 5; k tip l d liu ca ct th 6 c gi tr: 00000000 c a ra hng, tch cc ct th 6 ; d liu ca ct th 7 c gi tr: 00000000 a ra hng, tch cc ct th 7; d liu th 8 c gi tr: 00000000 a ra hng, tch cc ct th 8. Nh vy ton b d liu ca ch B c a ra hin th trn mn hnh Led ma trn. Qu trnh trn c din ra rt nhanh > 24ln/ 1s nn chng ta c cm gic n din ra mt cch ng thi, nh chng ta quan st c trn mn hnh Led ma trnl mt ch B lin tc. Phng php hin th Led ma trn s dng thanh ghi dch: u im: Tit kim ng truyn, hiu qu kinh t. Tit kim chn PORT. Truyn d liu i xa hn. M rng bng Ma trn ln mt cch d dng. Lp trnh d dng trong phng php qut ct. Nhc im: Tn thi gian thc hin vic truyn d liu n cc ct. Chuyn i khng linh hot bng s dng phng php cht. Lp trnh kh khn hn khi s dng phng php qut hng.


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VCCb1

b2 Q1 A1015

b3 Q2 A1015

b4 Q3 A1015

b5 Q4 A1015c4

b6 Q5 A1015Q6 b7 A1015

b8 Q7 A1015c7

Q8 A1015

4.4 Mch nguyn l:

c1

c2

c3

c5

c6

c8

90PD

9RN

VCCb9b10 Q9 A1015


Q10 b11 A1015Q13 b14 A1015c13c10

Q11 b12 A1015

Q12 b13 A1015

Q14 b15 A1015

Q15 b16 A1015c14c15

Q16 A1015

8 7 6 5 4 3 2 1c9

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

b16 b15 b14 b13 b12 b11 b10 b9

c11

c12

c16

5 2 7 1 12 8 14 9

8 7 6 5 4 3 2 19RN3MTRAN18 7 6 5 4 3 2 1

1 2 3 4 5 6 7 81 2 3 4 5 6 7 8

16 15 14 13 12 11 10 916 15 14 13 12 11 10 9330

b8 b7 b6 b5 b4 b3 b2 b1

90PB

4k7

h8 h7 h6 h5 h4 h3 h2 h113 3 4 10 6 11 15 16

h8 h7 h6 h5 h4 h3 h2 h1

h8 h7 h6 h5 h4 h3 h2 h1

13 3 4 10 6 11 15 16

5 2 7 1 12 8 14 9MTRAN2

SVTH :Trn Thnh Tm & Nguyn Tin Nghac1c2c3c4 c5c6c7c8

4k7c9c10 c12 c14 c16 c11 c13 c15

90PC

9RN2

GVHD:Thc s L nh Kha

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GVHD:Thc s L nh Kha

CHNG V : LCD(Liquid Crystal Display)5.1 Gii Thiu Chung V LCD C rt nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, trn hnh 1 l hai loi LCD thng dng.

Hnh 1 : Hnh dng ca hai loi LCD thng dng Khi sn xut LCD, nh sn xut tch hp chp iu khin (nh HD44780) bn trong lp v v ch a cc chn giao tip cn thit. Cc chn ny c nh s th t v t tn nh hnh 2 :

Hnh 2 : S chn ca LCD 2> Chc nng cc chn : Tn Chn V Chc Nng Chn S 1 2 3 Tn VSS VDD Vee Chc Nng Chn ni t cho LCD. Chn cp ngun cho LCD. Chn ny dng iu chnh tng phn ca LCD Chn chn thanh ghi (Register select). Ni chn RS vi logic 0 (GND) hoc logic 1 (VCC) chn thanh ghi. + Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR ca LCD ( ch ghi-write) hoc ni vi b m a ch ca LCD ( ch c - read). + Logic 1: Bus DB0-DB7 s ni vi thanhTrang 87

4

RS



GVHD:Thc s L nh Kha

ghi d liu DR bn trong LCD. 5 R/W Chn chn ch c/ghi (Read/Write). Ni chn R/W vi logic 0 LCD hot ng ch ghi, hoc ni vi logic 1 LCD ch c. Chn cho php (Enable). Sau khi cc tn hiu c t ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1 xung cho php ca chn E. + ch ghi: D liu bus s c LCD chuyn vo (chp nhn) thanh ghi bn trong n khi pht hin mt xung (high-to-low transition) ca tn hiu chn E. + ch c: D liu s c LCD xut ra DB0-DB7 khi pht hin cnh ln (lowto-high transition) chn E v c LCD gi bus n khi no chn E xung mc thp. Tm ng ca bus d liu dng trao i thng tin vi MPU. C 2 ch s dng 8 ng bus ny : + Ch 8 bit : D liu c truyn trn c 8 ng, vi bit MSB l bit DB7. + Ch 4 bit : D liu c truyn trn 4 ng t DB4 ti DB7, bit MSB l DB7

6

E

7-14

DB0DB7

. Bng 1 : Chc nng cc chn ca LCD * Ghi ch : ch c, ngha l MPU s c thng tin t LCD thng qua cc chn DBx.Cn khi ch ghi, ngha l MPU xut thng tin iu khin cho LCD thng qua cc chn DBx.


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GVHD:Thc s L nh Kha

3> S khi ca HD44780: Hnh 3 : S khi ca HD44780

5.1.1 Cc thanh ghi : Chp HD44780 c 2 thanh ghi 8 bit quan trng : Thanh ghi lnh IR (Instructor Register) v thanh ghi d liu DR (Data Register) - Thanh ghi IR : iu khin LCD, ngi dng phi ra lnh thng qua tm ng bus DB0-DB7. Mi lnh c nh sn xut LCD nh a ch r rng. Ngi dng ch vic cung cp a ch lnh bng cch np vo thanh ghi IR. Ngha l, khi ta np vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng m lnh ti a ch m IR cung cp v thc hin lnh . VD : Lnh hin th mn hnh c a ch lnh l 00001100 (DB7DB0) Lnh hin th mn hnh v con tr c m lnh l 00001110 - Thanh ghi DR : Thanh ghi DR dng cha d liu 8 bit ghi vo vng RAM DDRAM hoc CGRAM ( ch ghi) hoc dng cha d liu t 2 vng RAM ny gi ra cho MPU ( ch c). Ngha l, khi MPU ghi thng tin vo DR, mch ni bn trong chp s t ng ghi thng tin ny vo DDRAM hoc CGRAM. Hoc khi thng tinSVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 89


GVHD:Thc s L nh Kha

v a ch c ghi vo IR, d liu a ch ny trong vng RAM ni s c chuyn ra DR truyn cho MPU. - Bng cch iu khin chn RS v R/W chng ta c th chuyn qua li gi 2 thanh ghi ny khi giao tip vi MPU. Bng sau y tm tt li cc thit lp i vi hai chn RS v R/W theo mc ch giao tip.

Bng 2 : Chc nng chn RS v R/W theo mc ch s dng 5.1.2 C bo bn BF: (Busy Flag) Khi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt khong thi gian hon tt. Khi ang thc thi cc hot ng bn trong chip nh th, LCD b qua mi giao tip vi bn ngoi v bt c BF (thng qua chn DB7 khi c thit lp RS=0, R/W=1) ln bo cho MPU bit n ang bn. D nhin, khi xong vic, n s t c BF li mc 0. 5.1.3 B m a ch AC : (Address Counter) Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM (DDRAM v CGRAM) m thng qua b m a ch AC. B m ny li ni vi 2 vng RAM theo kiu r nhnh. Khi mt a ch lnh c np vo thanh ghi IR, thng tin c ni trc tip cho 2 vng RAM nhng vic chn la vng RAM tng tc c bao hm trong m lnh. Sau khi ghi vo (c t) RAM, b m AC t ng tng ln (gim i) 1 n v v ni dung ca AC c xut ra cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v R/W=1 (xem bng tm tt RS - R/W). Lu : Thi gian cp nht AC khng c tnh vo thi gian thc thi lnh m c cp nht sau khi c BF ln mc cao (not busy), cho nn khi lp trnh hin th, bn phi delay mt khong tADD khong 4uS- 5uS (ngay sau khi BF=1) trc khi np d liu mi. Xem thm hnh bn di.

Hnh 4 : Gin xung cp nht AC 5.1.4 Vng RAM hin th DDRAM : (Display Data RAM) y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM l mt k t trn mn hnh v khi bn ghi vo vng RAM ny mt m 8 bit, LCD s hin th ti v tr tng ng trn mn hnh mt k t c m 8 bit m bn cung cp. Hnh sau y s trnh by r hn mi lin h ny.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 90


GVHD:Thc s L nh Kha

Hnh 4 : Mi lin h gia a ch ca DDRAM v v tr hin th ca LCD Vng RAM ny c 80x8 bit nh, ngha l cha c 80 k t m 8 bit. Nhng vng RAM cn li khng dng cho hin th c th dng nh vng RAM a mc ch. Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC theo m HEX 5.1.5 Vng ROM cha k t CGROM: Character Generator ROM Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k t, v nh a ch bng 8 bit. Tuy nhin, n ch c 208 mu k t 5x8 v 32 mu k t kiu 5x10 (tng cng l 240 thay v 28 = 256 mu k t). Ngi dng khng th thay i vng ROM ny.

Hnh 5 : Mi lin h gia a ch ca ROM v d liu to mu k t. Nh vy, c th ghi vo v tr th x trn mn hnh mt k t y no , ngi dng phi ghi vo vng DDRAM ti a ch x (xem bng mi lin h gia DDRAM v v tr hin th) mt chui m k t 8 bit trn CGROM. Ch l trong bng m k t trong CGROM hnh bn di c m ROM A00.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 91


GVHD:Thc s L nh Kha

V d : Ghi vo DDRAM ti a ch 01 mt chui 8 bit 01100010 th trn LCD ti th 2 t tri sang (dng trn) s hin th k t b.

Bng 3 : Bng m k t (ROM code A00) 5.1.6 Vng RAM cha k t ha CGRAM : (Character Generator RAM) Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000 ngi dng c th to cc mu k t ha ring. Tuy nhin dung lng vng ny rt hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k t loi 5x10 im nh. ghi vo CGRAM, hy xem hnh 6 bn di.


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GVHD:Thc s L nh Kha

Hnh 6 : Mi lin h gia a ch ca CGRAM, d liu ca CGRAM, v m k t. 4> Tp lnh ca LCD : Trc khi tm hiu tp lnh ca LCD, sau y l mt vi ch khi giao tip vi LCD : * Tuy trong s khi ca LCD c nhiu khi khc nhau, nhng khi lp trnh iu khin LCD ta ch c th tc ng trc tip c vo 2 thanh ghi DR v IR thng qua cc chn DBx, v ta phi thit lp chn RS, R/W ph hp chuyn qua li gi 2 thanh ghi ny. (xem bng 2) * Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c th kh lu i vi tc ca MPU, nn ta cn kim tra c BF hoc i (delay) cho LCD thc thi xong lnh hin hnh mi c th ra lnh tip theo. * a ch ca RAM (AC) s t ng tng (gim) 1 n v, mi khi c lnh ghi vo RAM. (iu ny gip chng trnh gn hn) * Cc lnh ca LCD c th chia thnh 4 nhm nh sau : Cc lnh v kiu hin th. VD : Kiu hin th (1 hng / 2 hng), chiu di d liu (8 bit / 4 bit), SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 93


GVHD:Thc s L nh Kha

Ch nh a ch RAM ni. Nhm lnh truyn d liu trong RAM ni. Cc lnh cn li . (!!!) 5.2 Tp lnh ca LCD Tn lnh Clear Display Hot ng M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 0 0 0 1 Lnh Clear Display (xa hin th) s ghi mt khong trngblank (m hin k t 20H) vo tt c nh trong DDRAM, sau tr b m AC=0, tr li kiu hin th gc nu n b thay i. Ngha l : Tt hin th, con tr di v gc tri (hng u tin), ch tng AC M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 0 0 1 * Lnh Return home tr b m a ch AC v 0, tr li kiu hin th gc nu n b thay i. Ni dung ca DDRAM khng thay i M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 0 1 [I/D] [S] I/D : Tng (I/D=1) hoc gim (I/D=0) b m a ch hin th AC 1 n v mi khi c hnh ng ghi hoc c vng DDRAM. V tr con tr cng di chuyn theo s tng gim ny. S : Khi S=1 ton b ni dung hin th b dch sang phi (I/D=0) hoc sang tri (I/D=1) mi khi c hnh ng ghi vng DDRAM. Khi S=0: khng dch ni dung hin th. Ni dung hin th khng dch khi c DDRAM hoc c/ghi vng CGRAM. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 1 [D] [C] [B] D: Hin th mn hnh khi D=1 v ngc li. Khi tt hin th, ni dung DDRAM khng thay i. C: Hin th con tr khi C=1 v ngc li. V tr v hnh dng con tr, xem hnh 8 B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li. Xem thm hnh 8 v kiu nhp nhy. Chu k nhp nhy khong 409,6ms khi mch dao ng ni LCD l 250kHz.

Return home

Entry mode set

Display on/off control


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GVHD:Thc s L nh Kha

Hnh 8: Kiu con tr, kiu k t v nhp nhy k t Cursor or display shift M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 1 [S/C] [R/L] * * Lnh Cursor or display shift dch chuyn con tr hay d liu hin th sang tri m khng cn hnh ng ghi/c d liu. Khi hin th kiu 2 dng, con tr s nhy xung dng di khi dch qua v tr th 40 ca hng u tin. D liu hng u v hng 2 dch cng mt lc. Chi tit s dng xem bng bn di: S/C R/L Hot ng :

Function set

Bng 5: Hot ng lnh Cursor or display shift M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 1 [DL] [N] [F] * * DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit (t bit DB7 n DB0). Ngc li, giao thc giao tip l 4 bit (t bit DB7 n bit DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn 2 ln lin tip. vi 4 bit cao gi/nhn trc, 4 bit thp gi/nhn sau. N : Thit lp s hng hin th. Khi N=0 : hin th 1 hng, N=1: hin th 2 hng. F : Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh, F=1: kiu k t 5x10 im nh. . * Ch : Ch thc hin thay i Function set u chng trnh.


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GVHD:Thc s L nh Kha

V sau khi c thc thi 1 ln, lnh thay i Function set khng c LCD chp nhn na ngoi tr thit lp chuyn i giao thc giao tip. Khng th hin th kiu k t 5x10 im nh kiu hin th 2 hng Set CGRAM address . Set DDRAM address M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 1 [ACG][ACG][ACG][ACG][ACG][ACG] Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG] ch 1 bit ca chui d liu 6 bit. Ngay sau lnh ny l lnh c/ghi d liu t CGRAM ti a ch c ch nh. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD] [AD] Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn thit lp ta hin th mong mun. Ngay sau lnh ny l lnh c/ghi d liu t DDRAM ti a ch c ch nh. Khi ch hin th 1 hng, a ch c th t 00H n 4FH. Khi ch hin th 2 hng, a ch t 00h n 27H cho hng th nht, v t 40h n 67h cho hng th 2. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = [BF] [AC] [AC] [AC] [AC] [AC] [AC] [AC] (RS=0, R/W=1) Nh cp trc y, khi c BF bt, LCD ang lm vic v lnh tip theo (nu c) s b b qua nu c BF cha v mc thp. Cho nn, khi lp trnh iu khin, bn phi kim tra c BF trc khi ghi d liu vo LCD. Khi c c BF, gi tr ca AC cng c xut ra cc bit [AC]. N l a ch ca CG hay DDRAM l ty thuc vo lnh trc M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = [Write data] (RS=1, R/W=0) Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo cc chn DBx t mch ngoi s c LCD chuyn vo trong LCD ti a ch c xc nh t lnh ghi a ch trc (lnh ghi a ch cng xc nh lun vng RAM cn ghi). Sau khi ghi, b m a ch AC t ng tng/gim 1 ty theo thit lp Entry mode.Lu l thi gian cp nht AC khng tnh vo thi gian thc thi lnh. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = [Read data] (RS=1, R/W=1) Khi thit lp RS=1, R/W=1,d liu t CG/DDRAM c chuyn ra MPU thng qua cc chn DBx (a ch v vng RAM c xc nh bng lnh ghi a ch trc ).Trang 96

Read BF and address

Write data to CG or DDRAM

Read data from CG or DDRAM



GVHD:Thc s L nh Kha

Sau khi c, AC t ng tng/gim 1 ty theo thit lp Entry mode, tuy nhin ni dung hin th khng b dch bt chp ch Entry mode. 5> Giao tip gia LCD v MPU : c tnh in ca cc chn giao tip : LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm khong c tnh in sau y:

Bng 6 : Maximun Rating c tnh in lm vic in hnh: (o trong iu kin hot ng Vcc = 4.5V n 5.5V, T = -30 n +75C) 5.3 Khi to LCD6> Khi to LCD: Khi to l vic thit lp cc thng s lm vic ban u. i vi LCD, khi to gip ta thit lp cc giao thc lm vic gia LCD v MPU. Vic khi to ch c thc hin 1 ln duy nht u chng trnh iu khin LCD v bao gm cc thit lp sau : Display clear : Xa/khng xa ton b ni dung hin th trc . Function set : Kiu giao tip 8bit/4bit, s hng hin th 1hng/2hng, kiu k t 5x8/5x10. Display on/off control: Hin th/tt mn hnh, hin th/tt con tr, nhp nhy/khng nhp nhy. Entry mode set : cc thit lp kiu nhp k t nh: Dch/khng dch, t tng/gim (Increment). 5.3.1 Mch khi to bn trong chp HD44780: Mi khi c cp ngun, mch khi to bn trong LCD s t ng khi to cho n. V trong thi gian khi to ny c BF bt ln 1, n khi vic khi to hon tt c BF cn gi trong khong 10ms sau khi Vcc t n 4.5V (v 2.7V th LCD hot ng). Mch khi to ni s thit lp cc thng s lm vic ca LCD nh sau: Display clear : Xa ton b ni dung hin th trc . Function set: DL=1 : 8bit; N=0 : 1 hng; F=0 : 5x8 Display on/off control: D=0 : Display off; C=0 : Cursor off; B=0 : Blinking off. Entry mode set: I/D =1 : Tng; S=0 : Khng dch. Nh vy sau khi m ngun, bn s thy mn hnh LCD ging nh cha m ngun do ton b hin th tt. Do , ta phi khi to LCD bng lnh. 5.3.2 Khi to bng lnh: (chui lnh) Vic khi to bng lnh phi tun theo lu sau ca nh sn xut


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GVHD:Thc s L nh Kha


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GVHD:Thc s L nh Kha

Nh cp trn, ch giao tip mc nh ca LCD l 8bit (t khi to lc mi bt in ln). V khi kt ni mch theo giao thc 4bit, 4 bit thp t DB0-DB3 khng c kt ni n LCD, nn lnh khi to ban u (lnh chn giao thc giao tip function set 0010****) phi giao tip theo ch 8 bit (ch gi 4 bit cao mt ln, b qua 4 bit thp). T lnh sau tr i, phi gi/nhn lnh theo 2 nibble. Lu l sau khi thit lp function set, bn khng th thay i function set ngoi tr thay i giao thc giao tip (4bit/8bit). 5.4 Lu gii thut:Bt u

Init LCD

Gi Data

Hin th


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GVHD:Thc s L nh Kha

5.5 Mch nguyn l:VCC

J3

LCD1 2 3 4 5 6 7 8

2

7 8 9 10 11 12 13 14

D0 D1 D2 D3 D4 D5 D6 D7

VDD V0

3

2

13VR 10K

RS R/W E A K

4 5 6

CON8

15 16

LCDVSSJ4

5 4 3 2 1CON5


1

3

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GVHD:Thc s L nh Kha

CHNG VI : ADC6.1 Gii thiu v module ADC. 6.1.1 C bn v ADC. Trong cuc sng ca chng ta, nhng tn hiu m chng ta thng tip cn l tn hiu tng t , v d nh ting ni, sng in thoi, vv... Nu chng ta x l trc tip tn hiu tng t ny th rt kh, v vy cn thit phi chuyn i chng sang dng s. Bin i tng t s (analog digital) l thnh phn cn thit trong vic x l thng tin v cc cch iu khin s dng phng php s. Tn hiu thc Analog. Mt h thng tip nhn d liu phi c cc b phn giao tip Analog Digital (A/D). Cc b chuyn i tng t s, vit tt l ADC thc hin hai chc nng c bn l lng t ha v m ha. Lng t ha l gn cho nhng m nh phn cho tng gi tr ri rc sinh ra trong qu trnh lng t ha Bin i AD c tnh cht t l. Tn hiu vo Analog c bin i thnh mt phn s X bng cch so snh vi tn hiu tham chiu Vref. u ra ca b ADC l m ca phn s ny. Bt k mt sai s tn hiu Vref no cng s dn n sai s mc ra, v vy ngi ta c gn gi cho Vref cng n nh cng tt. Vref

Vin

ADOUTPUT_a(0 B111110);C

Digital output

Hnh 2.1 Quan h vo ra cc khi ADC Nu b ADC xut m ra gm n bit th s mc ra ri rc l 2n. i vi quan h tuyn tnh, tn vo c lng t ha theo ng mc ny. Mi mc nh vy l mt tn hiu Analog c phn bit vi hai m k tip nhau, n chnh l kch thc ca LSB (Least Significant Bit). Q=LSB= Trong :FS 2n

Q : Lng t LSB : Bit c trng s thp nht FS : Gi tr ton thang Tt c cc gi tr Analog ca lng t Q c biu din bi m s, m m ny tng ng vi gi tr trung bnh ca lng t (c th hiu l gia khong LSB) gi l mc ngng. Cc gi tr Analog nm trong khong t mc ngng sai bit i LSB vn c th hin bng cng mt m, l sai s lng t ha. Sai s ny c th s gim i bng cch tng s bit trong m ra b ADC. Sau y ti s trnh by nguyn tc chuyn i: - Bc 1 : Ly mu t hiu n tng t ( tc l ri rc ha tn hiu tng t ) c th l iu ch bin pha (PWM)


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GVHD:Thc s L nh Kha

Tn s ly mu cng cao th chnh xc ca ri rc ha l cng cao v ngc li, nu tn s ly mu cng ln th cn lng d liu ln do cn b nh ln v khi x l s rt phc tp. Tn s ly mu >= 2 ln tn s cao nht ca tn hiu ( trnh hin tng gp ph ) - Bc 2 : Lng t ha cc xung c ly mu .( m ha ) tc l iu ch xung PCM. Lng t ha y c ngha l dng mt thc o vi k bc nh phn ( tc l 2^k khong bng nhau ) o cc xung c ly mu v d

T ta c cc s tng ng vi xung v n c th hin qua cc s nh phn v d vi k = 8 ( tc l biu din s ny da vo 8bit ) ta mun biu din s 9 s nh phn tng ng l: 0 0 0 0 1 0 0 1 trong bt u tin l MSB lm du My tnh s thu nhn gi tr ny ri thc hin vic lu tr , x l. 6.1.2 ADC trong PIC 16F877A Trn VK c mt b bin i ADC 10bit, 8 ng vo Analog, 8 ng vo ny c ni vi ng vo ca b chuyn i. Sau b chuyn i s to ra mt kt qu 10 bit tng ng vi gi tr Ananlog u vo. in th tham chiu u vo s c la chnSVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 102


GVHD:Thc s L nh Kha

bng phn mm (t Vdd, Vss hoc 2 chn AN2, AN3. Module ADC l module duy nht c kh nng hot ng trong ch ng. hot ng trong ch ng Sleep, xung clock cung cp cho ADC phi c nhn t dao ng ni RC ca ADC. Mt b ADC c bn gm c: Ng vo VIN. in p chun VREF. Cc bit ng ra. Quan h cc i lng ny c th m t nh sau: N=(VIN / VREF).NMax Vi: N : Chuyn i thp phn ca cc bit ng ra NMax :Gi tr thp phn ln nht ti ng ra . Nmax ph thuc vo s lng bit ti ng ra ca ADC V d :s dng ADC 8 bit th gi tr Nmax =28 1 =255 Khi : N=(VIN / VREF).255 6.2 S nguyn l:L0

VCC

2L12

11

1DX

1R46 10K 1R47

1U11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20MCLR/VPP RB7/PGD RA0/AN0 RB6/PGC RA1/AN1 RB5 RA2/AN2/VRef -/CVRef RB4 RA3/AN3/VRef + RB3/PGM RA4/T0CKI/C1OUT RB2 RA5/AN4/SS/C2OUT RB1 RB0/INT RE0/RD/AN5 VDD RE1/WR/AN6 GND RE2/CSAN7 VDD RD7/PSP7 GND RD6/PSP6 OSC1/CLKI RD5/PSP5 RD4/PSP4 OSC2/CLKO RC0/T1OSO/T1CKI RC7/RX/DT RC1/T1OSI/CCP2 RC6/TX/CK RC2/CCP1 RC5/SDO RC3/SCK/SCL RC4/SDI/SDA RD0/PSP0 RD3/PSP3 RD1/PSP1 RD2/PSP2

L2

VCC4R29 8 7 6 5 4 3 2

1C71RS 104

VCC 100

VR 10K

1Y1

1C8 33p

1C9 33p

40 39 38 37 36 35 34 33 32 31 VCC 30 29 28 27 26 25 24 23 22 21

2L32

11

1

L42

1

L52L62

11

330

L72

1

PIC16F877A

Vi Vcc = 5V.Bin tr VR=10k


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GVHD:Thc s L nh Kha

CHNG VII : BN PHM GIAO TIP LCD7.1 Keypad V Nguyn L Hot ng Mt bn phm s Hex c thnh lp t 16 nt nhn n. Cc nt nhn ny c ni vo vi iu khin. Khi thc hin kim tra phm nhn, vn cn thit l phi thc hin chng rung phm v chng nhiu. Qu trnh chng rung phm v chng nhiu c th thc hin bng phn mm: Do thi gian rung phm vo khong 20ms nn qu trnh chng rung bng phn mm n gin l to mt thi gian ch ln chng trnh b qua nh hng khi rung phm v chng nhiu.5V R4 10k R3 10k R2 10k R1 10k

7 4 1

8 5 2 0

9 6 3 #

A B C D

J1 8 7 6 5 4 3 2 1 PORT B

*

pht hin phm nhn ta s dng phng php qut hng. Khi khng nhn phm th hng ca bn phm Hex ni vi Vcc thng qua in tr R nn c mc logic 1. phn bit c trng thi ca phm nhn th mc logic khi nhn phm phi l mc logic 0. M khi nhn mt phm no th tng ng hng v ct ca bn phm Hex s kt ni vi nhau. Do , thc hin kim tra mt phm th ta phi cho trc ct cha phm tng ng mc logic 0, sau kim tra hng ca phm, nu hng = 0 th c nhn phm cn hng = 1 th khng nhn phm. V d nh mun kim tra phm 4 th ta cho ct cha phm 4 mc logic 0(chn 4 ca J1, cc ct khc = 1), sau thc hin kim tra chn 7 ca J1 (hng ca phm 4), nu chn ny = 0 th phm 4 c nhn. 7.2 Keypad v giao tip vi LCD. Trong mch di LCD c ni vi Port B cn bn phm ni vi Port D. Chng trnh ch n gin l ch xem c phm no nhn th hin th phm ln mn hnh LCD.


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VCCR7 10k1U1

U1

VCC

1DX

1R46 10K

1C7

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1R47

100

VCC

VCC

1 2 3 4 5 6 7 8 9 10 11 12 13 14

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1Y 1

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1C9

SVTH :Trn Thnh Tm & Nguyn Tin Ngha10 9 8 1 2 3 4 5 6 7 11 12 13 14 15 16 17 18 23 24RE2/CSAN7 RB7/PGD RE1/WR/AN6 RB6/PGC RE0/RD/AN5 RB5 RB4 MCLR/VPP RB3/PGM RA0/AN0 RB2 RA1/AN1 RB1 RA2/AN2/VRef -/CVRef RB0/INT RA3/AN3/VRef + VDD RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT GND RD7/PSP7 VDD RD6/PSP6 GND RD5/PSP5 OSC1/CLKI RD4/PSP4 OSC2/CLKO RC0/T1OSO/T1CKI RD3/PSP3 RC1/T1OSI/CCP2 RD2/PSP2 RD1/PSP1 RC2/CCP1 RD0/PSP0 RC3/SCK/SCL RC4/SDI/SDA RC7/RX/DT RC5/SDO RC6/TX/CK

33p

33p

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SW1

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PIC16F877A

SW4

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SW14R6 R

SW15

R6 R

R5 R

R4 R

GVHD:Thc s L nh Kha

VCC

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GVHD:Thc s L nh Kha

7.3 S Gii Thut

Bt u

Init LCD

Qut phm

C phm nhn

S

Hin th


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GVHD:Thc s L nh Kha

CHNG VIII : GIAO TIP I2C (GIAO TIP EEPROM 24C04)8.1 Gii Thiu Chung V I2C: Ngy nay trong cc h thng in t hin i, rt nhiu ICs hay thit b ngoi vi cn phi giao tip vi cc ICs hay thit b khc giao tip vi th gii bn ngoi. Vi mc tiu t c hiu qu cho phn cng tt nht vi mch in n gin, Phillips pht trin mt chun giao tip ni tip 2 dy c gi l I2C. I2C l tn vit tt ca cm t Inter Intergrated Circuit Bus giao tip gia cc IC vi nhau. I2C mc d c pht trin bi Philips, nhng n c rt nhiu nh sn xut IC trn th gii s dng. I2C tr thnh mt chun cng nghip cho cc giao tip iu khin, c th k ra y mt vi tn tui ngoi Philips nh: Texas Intrument (TI), Maxim-Dallas, analog Device, National Semiconductor Bus I2C c s dng lm bus giao tip ngoi vi cho rt nhiu loi IC khc nhau nh cc loi Vi iu khin 8051, PIC, AVR, ARM, chip nh nh RAM tnh (Static Ram), EEPROM, b chuyn i tng t sang s (ADC), s sang tng t(DAC), IC iu khin LCD, LED

8.1.1 c im giao tip I2C Mt giao tip I2C gm c 2 dy: Serial Data (SDA) v Serial Clock (SCL). SDA l ng truyn d liu 2 hng, cn SCL l ng truyn xung ng h v ch theo mt hng. Nh hnh v trn, khi mt thit b ngoi vi kt ni vo ng I2C th chn SDA ca n s ni vi dy SDA ca bus, chn SCL s ni vi dy SCL.

Hnh 1.2. Kt ni thit b vo bus I2C ch chun (Standard mode) v ch nhanh (Fast mode)SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 107


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Mi dy SDA hay SCL u c ni vi in p dng ca ngun cp thng qua mt in tr ko ln (pull-up resistor). S cn thit ca cc in tr ko ny l v chn giao tip I2C ca cc thit b ngoi vi thng l dng cc mng h (open-drain or opencollector). Gi tr ca cc in tr ny khc nhau ty vo tng thit b v chun giao tip, thng dao ng trong khong 1K n 4.7K. Tr li vi hnh mc 8.1, ta thy c rt nhiu thit b (ICs) cng c kt ni vo mt bus I2C, tuy nhin s khng xy ra chuyn nhm ln gia cc thit b, bi mi thit b s c nhn ra bi mt a ch duy nht vi mt quan h ch/t tn ti trong sut thi gian kt ni. Mi thit b c th hot ng nh l thit b nhn d liu hay c th va truyn va nhn. Hot ng truyn hay nhn cn ty thuc vo vic thit b l ch (master) hay t (slave). Mt thit b hay mt IC khi kt ni vi bus I2C, ngoi mt a ch (duy nht) phn bit, n cn c cu hnh l thit b ch (master) hay t (slave). Ti sao li c s phn bit ny ? l v trn mt bus I2C th quyn iu khin thuc v thit b ch (master). Thit b ch nm vai tr to xung ng h cho ton h thng, khi gia hai thit b ch/t giao tip th thit b ch c nhim v to xung ng h v qun l a ch ca thit b t trong sut qu trnh giao tip. Thit b ch gi vai tr ch ng, cn thit b t gi vai tr b ng trong vic giao tip.

Master truyn d liu

Master nhn d liu Nhn hnh trn ta thy xung ng h ch c mt hng t ch n t, cn lung d liu c th i theo hai hng, t ch n t hay ngc li t n ch. V d liu truyn trn bus I2C, mt bus I2C chun truyn 8bit d liu c hng trn ng truyn vi tc l 100Kbits/s Ch chun (Standard mode). Tc truyn c th ln ti 400Kbits/s Ch nhanh (Fast mode) v cao nht l 3,4Mbits/s Ch cao tc (Highspeed mode). Mt bus I2C c th hot ng nhiu ch khc nhau: Mt ch mt t (one master one slave). Mt ch nhiu t (one master multi slave). Nhiu ch nhiu t (Multi master multi slave). D ch no, mt giao tip I2C iu da vo quan h ch/t. Gi thit mt thit b A. mun gi d liu n thit b B, qu trnh c thc hin nh sau: Thit b A (Ch) xc nh ng a ch ca thit b B (t), cng vi vic xc nh a ch, thit b A s quyt nh vic c hay ghi vo thit b t. Thit b A gi d liu ti thit b B. Thit b A kt thc qu trnh truyn d liu. Khi A mun nhn d liu t B, qu trnh din ra nh trn, ch khc l A s nhn d liu t B. Trong giao tip ny, A l ch cn B vn l t. Chi tit vic thit lp mt giao tip gia hai thit b s c m t chi tit trong cc mc di y.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 108


GVHD:Thc s L nh Kha

8.1.2 START and STOP conditions START v STOP l nhng iu kin bt buc phi c khi mt thit b ch mun thit lp giao tip vi mt thit b no trong mng I2C. START l iu kin khi u, bo hiu bt u ca giao tip, cn STOP bo hiu kt thc mt giao tip. Hnh di y m t iu kin START v STOP. Ban u khi cha thc hin qu trnh giao tip, c hai ng SDA v SCL u mc cao (SDA = SCL = HIGH). Lc ny bus I2C c coi l ri (bus free), sn sng cho mt giao tip. Hai iu kin START v STOP l khng th thiu trong vic giao tip gia cc thit b I2C vi nhau.

Hnh 1.4. iu kin START v STOP ca bus I2C iu kin START: mt s chuyn i trng thi t cao xung thp trn ng SDA trong khi ng SCL ang mc cao (cao = 1; thp = 0) bo hiu mt iu kin START. iu kin STOP: Mt s chuyn i trng thi t mc thp ln cao trn ng SDA trong khi ng SCL ang mc cao. C hai iu kin START v STOP u c to ra bi thit b ch. Sau tn hiu START, bus I2C coi nh ang trong trang thi lm vic (busy). Bus I2C s ri, sn sng cho mt giao tip mi sau tn hiu STOP t pha thit b ch. Sau khi c mt iu kin START, trong qua trnh giao tip, khi c mt tn hiu START c lp li thay v mt tn hiu STOP th bus I2C vn tip tc trong trng thi bn. Tn hiu START v lp li START u c chc nng ging nhau l khi to mt giao tip. 8.1.3 nh dng d liu truyn D liu c truyn trn bus I2C theo tng bit, bit d liu c truyn i ti mi sn dng ca xung ng h trn dy SCL, qu trnh thay i bit d liu xy ra khi SCL ang mc thp.

Hnh 1.5. Qu trnh truyn 1 bit d liu Mi byte d liu c truyn c di l 8 bits. S lng byte c th truyn trong mt ln l khng hn ch. Mi byte c truyn i theo sau l mt bit ACK bo hiu nhn d liu. Bit c trng s cao nht (MSB) s c truyn i u tin, cc bt sSVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 109


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c truyn i ln lt. Sau 8 xung clock trn dy SCL, 8 bit d liu c truyn i. Lc ny thit b nhn, sau khi nhn 8 bt d liu s ko SDA xung mc thp to mt xung ACK ng vi xung clock th 9 trn dy SDA bo hiu nhn 8 bit. Thit b truyn khi nhn c bit ACK s tip tc thc hin qu trnh truyn hoc kt thc.

Hnh 1.6. D liu truyn trn bus I2C

Hnh 1.7. Bit ACK trn bus I2C


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Mt byte truyn i c km theo bit ACK l iu kin bt buc, nhm m bo cho qu trnh truyn nhn c din ra chnh xc. Khi khng nhn c ng a ch hay khi mun kt thc qu trnh giao tip, thit b nhn s gi mt xung Not-ACK (SDA mc cao) bo cho thit b ch bit, thit b ch s to xung STOP kt thc hay lp li mt xung START bt u qu trnh mi. 8.1.4 nh dng a ch thit b Mi thit b ngoi vi tham gia vo bus I2C u c mt a ch duy nht, nhm phn bit gia cc thit b vi nhau. di a ch l 7 bit, iu c ngha l trn mt bus I2C ta c th phn bit ti a 128 thit b. Khi thit b ch mun giao tip vi ngoi vi no trn bus I2C, n s gi 7 bit a ch ca thit b ra bus ngay sau xung START. Byte u tin c gi s bao gm 7 bit a ch v mt bt th 8 iu khin hng truyn.

Hnh 1.8. Cu trc byte d liu u tin Mi mt thit b ngoi vi s c mt a ch ring do nh sn xut ra n quy nh. a ch c th l c nh hay thay i. Ring bit iu khin hng s quy nh chiu truyn d liu. Nu bit ny bng 0 c ngha l byte d liu tip theo sau s c truyn t ch n t, cn ngc li nu bng 1 th cc byte theo sau byte u tin s l d liu t con t gi n con ch. Vic thit lp gi tr cho bit ny do con ch thi hnh, con t s ty theo gi tr m c s phn hi tng ng n con ch.


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8.1.5 Truyn d liu trn bus I2C, ch Master - Slave Vic truyn d liu din ra gia con ch v con t. D liu truyn c th theo 2 hng, t ch n t hay ngc li. Hng truyn c quy nh bi bit th 8 (R\W) trong byte u tin c truyn i.

Truyn d liu t ch n t (ghi d liu): Thit b ch khi mun ghi d liu n con t, qu trnh thc hin l: Thit b ch to xung START Thit b ch gi a ch ca thit b t m n cn giao tip cng vi bit RW = 0 ra bus v i xung ACK phn hi t con t. Khi nhn c xung ACK bo nhn din ng thit b t, con ch bt u gi d liu n con t theo tng byte mt. Theo sau mi byte ny u l mt xung ACK. S lng byte truyn l khng hn ch. Kt thc qu trnh truyn, con ch sau khi truyn byte cui s to xung STOP bo hiu kt thc

Truyn d liu t t n ch (c d liu): Thit b ch mun c d liu t thit b t, qu trnh thc hin nh sau: Khi bus ri, thit b ch to xung START, bo hiu bt u giao tip. Thit b ch gi a ch ca thit b t cn giao tip cng vi bit RW = 1 v i xung ACK t pha thit b t Sau xung ACK du tin, thit b t s gi tng byte ra bus, thit b ch s nhn d liu v tr v xung ACK. S lng byte khng hn ch. Khi mun kt thc qu trnh giao tip, thit b ch gi xung Not-ACK v to xung STOP kt thc.


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Qu trnh kt hp ghi v c d liu: gia hai xung START v STOP, thit b ch c th thc hin vic c hay ghi nhiu ln, vi mt hay nhiu thit b. thc hin vic , sau mt qu trnh ghi hay c, thit b ch lp li mt xung START v li gi li a ch ca thit b t v bt u mt qu trnh mi.

Ch giao tip Master-Slave l ch c bn trong mt bus I2C, ton b bus c qun l bi mt master duy nht. Trong ch ny s khng xy ra tnh trng xung t bus hay mt ng b xung clock v ch c mt master duy nht c th to xung clock. 8.1.6 Ch Multi-Master Trn bus I2C c th c nhiu hn mt master iu khin bus. Khi bus I2C s hot ng ch Multi-Master. 8.2 Module I2C Trong Vi iu Khin PIC Vi nhng tin ch em li, khi giao tip I2C c tch hp cng trong kh nhiu loi Vi iu khin khc nhau. Trong cc loi Vi iu khin PIC dng Mid-range ph bin ti Vit Nam, ch t 16F88 mi c h tr phn cng I2C, cn cc loi 16F84, 16F628 th khng c. Vi nhng loi Vi iu khin khng c h tr phn cng giao tip I2C, s dng ta c th dng phn mm lp trnh, khi ta s vit mt chng trinh iu khin 2 chn bt k ca Vi iu khin n thc hin giao tip I2C (cc hm START, STOP, WRITE, READ). Trong bi vit ny ta cp n vic s dng giao tip I2C ca cc loi PIC c tch hp khi I2C sn trong n, m c th l Vi iu khin PIC16F877A. 8.2.1 c im phn cng ca PIC16F877A Hnh di y ch ra cu trc phn cng ca khi iu khin giao tip ni tip ng b (MSSP) hot ng ch I2C. Khi I2C c y chc nng, hot ng c 2 ch l MASTER (ch) v SLAVE (t), c ngt xy ra khi c iu kin START hay STOP xy ra, nhm nh r ng I2C c ri hay khng ( chc nng Multi-master ). Ch a ch c th l 7 bit hay 10 bit. Khi I2C c 6 thanh ghi iu khin hot ng, l: SSPCON: Thanh ghi iu khin. SSPCON2: Thanh ghi iu khin th 2. SSPSTAT: Thanh ghi trng thi. SSPBUF: Thanh ghi b m truyn nhn.SVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 113


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SSPSR: Thanh ghi dch. SSPADD: Thanh ghi a ch. Cc thanh ghi SSPCON, SSPBUF, SSPADD v SSPSON2 c th truy cp c/ghi c.Thanh ghi SSPSR khng th truy cp trc tip, l thanh ghi dich d liu ra hay vo. Cc thanh ghi SSPCON, SSPCON2 v SSPSTAT c nh a ch bit, mi bit c chc nng ring. ngha ca tng thanh ghi v ca mi bit trong tng thanh ghi c cp k trong ti liu Datasheet ca PIC

Hnh2.1. Cu trc khi I2C trong PIC 8.2.2 Cch thc s dng Module I2C trong CCS Trong vic lp trnh cho PIC s dng giao tip I2C ca n trong cc ng dng, ngi lp trnh c th thc hin mt cch d dng vi trnh dch CCS. Ni d dng y l ch v mt c php lnh, ta khng cn s dng nhiu cu lnh kh nh nh trong lp trnh ASM. Vic khi to, chn ch hot ng v thc hin giao tip ca I2C c cc hm dng sn ca CCS thc hin. Cc hm lit k di y l ca phin bn CCS 3.242, l: I2C_isr_state(): Thng bo trng thi giao tip I2C I2C_start(): To iu kin START I2C_stop(): To iu kin STOP I2C_read(): c gi tr t thit b I2C, tr v gi tr 8 bit I2C_write(): Ghi gi tr 8 bit n thit b I2C s dng khi I2C ta s dng khai bo sau: #use i2c(ch_, tc , sda = PIN_C4, scl=PIN_C3) Ch : Master hay SlaveSVTH :Trn Thnh Tm & Nguyn Tin Ngha Trang 114


GVHD:Thc s L nh Kha

Tc : Slow (100KHz) hay Fast (400KHz) SDA v SCL l cc chn I2C tng ng ca PIC Sau khai bo trn, ta c th s dng cc hm nu trn thc hin, x l cc giao tip I2C vi cc thit b ngoi vi khc. 8.2.3 EEPROM 24C04 24C04 l loi EEROM 4k, gm 2 block 256 x 8 bit. B nh tng thch vi chun I2C vi 2 dy SDA v SDL. B nh xut ra 4 bit v mt thit b duy nht c nhn ra v p ng li trn bus I2C. 8.2.3.1 Hnh Dng

8.2.3.2 S cu to:

8.2.3.3 S Chn


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SCL (Serial clock) : ng vo ng b d liu ra vo ca b nh. SDA(Serial Data Address Input/Output): chn ny dng bin i d liu v truyn ra hay nhn vo b nh. E1 E2 ( chip Enable): l ng vo chn chip v phi s dng t nht 2 bt quan trng b2,b3 ca 7 bt chn thit b.ng vo ny c iu khin t ng v c ni vi Vcc hay Vss thnh lp m chn thit b( Device select Code)

PRE(Protect Enable): dng b xung tnh trng ca bit Block Address Pointer MODE: ng vo ny trn chn 7 ca 24c04 v c th c iu khin t ng. N phi c chn l VIH hay VIL cho ch ghi cc Byte. VIH ( Multibyte Write mode ): c th bt u trn bt c a ch no trn b nh. Master s gi t 1 n 4 byte d liu km theo ACK bo nhn

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