2.1 Khao sat vi iu khin PIC16F877A

2.2.1 S chn cua vi iu khin PIC16F877A

Hinh 2.6 S chn cua vi iu khin PIC16F877A 2.2.2 Mt s thng s v vi iu khin PIC16F877A y la vi iu khin thuc ho ho PIC16Fxxx vi tp lnh gm 35 lnh co o dai 14 bit. Mi lnh u c thc thi trong mt chu ky xung clock. Tc hoat ng ti a cho phep la 20MHz vi chu ky lnh la 200ns. B nh chng trinh la 8K x 14 bit, b nh d liu la 368x8 byte RAM va b nh d liu EEPROM vi dung lng 256x8 byte. S PORT I/O la 5 vi 33 pin I/O [3]. Cac c tinh ngoai vi bao gm cac khi chc nng sau: Timer0 : B m 8 bit vi b chia tn 8 bit. Timer1 : B m 16 bit vi b chia tn s, co th thc hin chc nng m da vao xung clock ngoai vi ngay khi vi iu khin hoat ng ch sleep. Timer2 : B m 8 bit vi b chia tn s, b postcaler. Hai b Capture/ so sanh/ iu ch rng xung. Cac chun giao tip ni tip SSP ( synchronous Serial Port ), SPI va I2C.

Chun giao tip ni tip USART vi 9 bit ia chi. Cng giao tip song song PSP ( Parallel Slave Port )vi cac chn iu khin RD,WR, CS bn ngoai. Cac c tinh Analog : - 8 knh chuyn i ADC 10bit. - Hai b so sanh Bn canh o la mt vai c tinh khac cua vi iu khin nh : - B nh flash vi kha nng ghi/xoa c 100.000 ln. - B nh EEPROM vi kha nng ghi/xoa c 1000.000 ln. - D liu b nh EEPROM co th lu tr trn 40 nm. - Kha nng t nap chng trinh vi kha nng iu khin cua phn mm. - Nap c chng trinh ngay trn mach in ICSP ( In Circuit SeRial Programming ) thng qua 2 chn.- Watchdog timer vi b giao ng trong.

- Chc nng bao mt chng trinh. - Ch Sleep - Co th hoat ng vi nhiu dang Oscillator khac nhau. 2.2.3 S khi cua vi iu khin PIC16F877A S khi cua PIC16F877A nh hinh di [4]:

Hinh 2.7 S khi cua PIC16F877A 2.2.4 T chc b nh Cu truc b nh cua vi iu khin PIC16F877A gm co b nh chng trinh (Program memory ) va b nh d liu ( Data memory). 2.2.4.1 B nh chng trinh ( program memory) B nh chng trinh cua vi iu khin PIC16F877A la b nh flash, dung lng b nh la 8K word ( 1word = 14 bit ) va c phn thanh nhiu trang ( t page0 n page3). Nh vy b nh chng trinh co kha nng cha c 8*1024 = 8192 lnh ( vi mi lnh sau khi ma hoa co dung lng 1 word = 14 bit [3]. ma hoa c ia chi cua 8K b nh chng trinh thi b m chng trinh phai co dung lng la 13 bit ( PC).

Khi vi iu khin c reset thi b m chng trinh se chi n ia chi 0000h (Reset vector ). Khi co ngt xay ra thi b m chng trinh se chi m ia chi 0004h ( Interrupt vector ). B nh chng trinh khng bao gm b nh Stack va khng c ia chi hoa bi b m chng trinh. B nh Stack c cp cu th trong phn sau.

Hinh 2.8 B nh chng trinh PIC16F877A

2.2.4.2 B nh d liu B nh d liu cua PIC la b nh EEPROM c chia thanh nhiu bank. Vi PIC166F877A b nh d liu c chia la 4 bank. Mi bank co dung lng 128 byte, bao gm cac thanh ghi co chc nng c bit SFR ( Special Function Rigister ) nm vung ia chi thp va cac thanh ghi co muc ich chung GPR (General Purpose Register) nm vung ia chi con lai cua bank. Cac thanh ghi SFR thng xuyn c s dung (vi du nh thanh ghi STATUS ) se c t tt ca cac bank trong b nh d liu giup thun tin cho qua trinh truy xut va giam bt lnh cua chng trinh. S cu th cua b nh d liu cua PIC16F877A nh sau [4]:

Hinh 2.9 S b nh d liu cua PIC16F877A a. Thanh ghi chc nng c bit SFR y la cac thanh ghi s dung bi CPU hoc c dung thit lp va iu khin cac khi chc nng c tich hp bn trong vi iu khin. Co th phn thanh ghi SFR thanh hai loai : thanh ghi SFR lin quan n chc nng bn trong ( CPU ) va

thanh ghi dung thit lp va iu khin cac khi chc nng bn ngoai ( vi du nh ADC, PWM) [3]. Thanh ghi STATUS ( 03h, 83h, 103h, 183h) : thanh ghi cha kt qua thc hin cac phep toan cua khi ALU, trang thai reset va cac bit chon bank cn c truy xut trong b nh d liu.

Thanh ghi OPTION_REG (81h, 181h) : thanh ghi nay cho phep oc va ghi, cho phep iu khin chc nng pull-up cua cac chn PORTB,xac lp cac tham s v cac xung tac ng, cach tac ng cua ngt ngoai vi va b m TIMER0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh): thanh ghi cho phep oc va ghi, cha cac bit iu khin va cac bit c hiu khi TIMER0 tran va ngt ngoai vi RB0/INT va ngt interrput- on- change tai cac chn cua PORTB.

Thanh ghi PIE1 (8Ch): cha cac bit iu khin chi tit cac ngt cua cac khi chc nng ngoai vi.

Thanh ghi PIR1 (0Ch): cha c ngt cua cac khi chc nng ngoai vi, cac ngt nay c cho phep bi cac bit iu khin cha trong thanh ghi PIE1.

Thanh ghi PIE2 (8Dh): cha cac bit iu khin cac ngt cua cac khi chc nng CCP2, SSP bus, ngt cua b so sanh va ngt ghi vao b nh EEPROM.

Thanh ghi PIR2 (0Dh): cha cac c ngt cua cac khi chc nng ngoai vi, cac ngt nay c cho phep bi cac bit iu khin cha trong thanh ghi PIE2.

Thanh ghi PCON (8Eh): cha cac c hiu cho bit trang thai cua ch reset cua vi iu khin.

b. Thanh ghi muc ich chung GPR Cac thanh ghi nay co th c truy xut trc tip hoc gian tip thng qua thanh ghi FSG ( File Select Register ). y la cac thanh ghi d liu thng thng, ngi s dung co th tuy theo muc ich chng trinh ma co th dung cac thanh ghi nay cha cac bin s, hng s, kt qua hoc tham s phuc vu cho chng trinh [3]. 2.2.5 Stack Stack khng nm trong b nh chng trinh hay b nh d liu ma la mt vung nh c bit khng cho phep oc hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xay ra lam chng trinh bi re nhanh, gia tri cau b m chng trinh PC t ng c vi iu khin ct vao stack. Khi mt trong cac lnh RETURN, RETLW hay RETFIE c thc thi, gia tri PC se t ng c ly ra t trong stack, vi iu khin se thc hin tip chng trinh theo ung quy trinh inh trc. B nh Stack trong vi iu khin PIC ho 16F87xA co kha nng cha c 8 ia chi va hoat ng theo c ch xoay vong. Nghia la gia tri ct vao b nh Stack ln

th 9 se ghi e ln gia tri ct vao Stack ln u tin va gia tri ct vao Stacsk ln th 10 se ghi e ln gia tri ct vao Stack ln th 2. Cn chu y la khng co c hiu nao cho bit trang thai Stack, do o ta khng bit c khi nao Stack se tran. Bn canh o tp lnh cua vi iu khin dong PIC cung khng co lnh POP hay PUSH, cac thao tac vi b nh Stack se hoan toan c iu khin bi CPU [3]. 2.2.6 Cac cng xut nhp cua PIC16F877A Cng xut nhp (I/O port) chinh la phng tin ma vi iu khin dung tng tac vi th gii bn ngoai. S tng tac nay rt a dang va thng qua qua trinh tng tac o, chc nng cua vi iu khin c th hin mt cach ro rang. Mt cng xut nhp cua vi iu khin bao gm nhiu chn I/O pin, tuy theo cach b tri va chc nng cua vi iu khin ma s lng cng xut nhp va s lng chn trong mi cng co th khac nhau. Bn canh o, do vi iu khin c tich sn bn trong cac c tinh giao tip ngoai vi nn bn cach chc nng la cng xut nhp thng thng thi mt s chn xut nhp co cac chc nng khac thc hin s tac ng cua cac daewcj tinh ngoai vi nu trn i vi th gii ngoai. Chc nng cua tng chn xut nhp trong mi cng hoan toan co th c xac lp va iu khin thng qua thanh ghi SFR lin quan n cac chn xut nhp o. Vi iu khin PIC16F877A co 5 cng xut nhp la PORTA, PORTB, PORTC, PORTD va PORTE. Cu truc va chc nng tng cng xut nhp c trinh bay cu th trong phn tip theo [3]. 2.2.6.1 PORTA PORTA (RPA ) bao gm 6 I/O pin. y la cac chn 2 chiu (bidirectional pin ) nghia la co th xut va nhp c. Chc nng I/O nay c iu khin bi thanh ghi TRISA ( ia chi 85h ). Mun xac lp chc nng cua mt chn trong PORTA la input, ta set bit iu khin tng ng vi chn o trong thanh ghi TRISA va ngc lai, mun xac lp chc nng cua mt chn trong PORTA la output ta clear bit iu khin vi chn o trong thanh ghi TRISA. Thao tac nay hoan toan tng t i vi cac PORT va cac thanh ghi iu khin tng ng ( i vi PORTA la TRISA, i vi PORTB la TRISB, i vi PORTC la TRISC, i vi PORTD la

TRISD, i vi PORTE la TRISE ). Bn canh o, PORTA con la ngo ra cua b ADC, b so sanh, ngo vao analog, ngo vao xung clock cua Timer0 va ngo vao cua b giao tip MSSP (Master Synchronous Serial Port) [3]. Chc nng cac chn trong PORTA [4]:

Hinh 2.10 Chc nng cua cac chn trong PORTA Cac thanh ghi SFR lin quan n PORTA bao gm [3]: - PORTA (ia chi 05h): cha gia tri cua pin trong PORTA. - TRISA ( ia chi 85h): iu khin xut nhp. - CMCON ( ia chi 9Ch): thanh ghi iu khin b so sanh.

- CVRCON ( ia chi 9Dh): thanh ghi iu khin b so sanh in ap. - ADCON1 ( ia chi 9Eh): thanh ghi iu khin b ADC. 2.2.6.2 PORTB PORTB (RPB) gm 8 pin I/O. thanh ghi iu khin xut nhp tng ng la TRISB. Bn canh o mt s chn cua PORTB con c s dung trong qua trinh nap chng trinh cho vi iu khin vi cac ch nap khac nhau. PORTB con lin quan n ngt ngoai vi va b Timer0 [3]. Chc nng cu th cua tng chn trong PORTB nh sau [4]:

Hinh 2.11 Chc nng cac chn trong PORTB Cac thanh ghi SFR lin quan n PORTB bao gm [3]: - PORTB ( ia chi 06h, 106h ): cha cac gia tri pin trong PORTB.

- TRISB ( ia chi 86h, 186h ): thanh ghi iu khin xut nhp. - OPTION_REG ( ia chi 81h, 181h ): iu khin ngt ngoai vi va b Timer0.2.2.6.3 PORTC

PORTC (RPC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng la TRISC. Bn canh o PORTC con cha cac chn chc nng cua b so sanh, Timer1, b PWM va cac chun giao tip ni tip I2C, SPI, SSP, USART [3]. Chc nng cu th cua cac chn trong PORTC nh sau [4]:

Hinh 2.12 Chc nng cac chn trong PORTC

Cac thanh ghi iu khin lin quan n PORTC gm [3]: - PORTC ( ia chi 07h): cha gia tri pin trong PORTC. - TRISC ( ia chi 87h ): thanh ghi iu khin xut nhp. 2.2.6.4 PORTD PORTD ( RPD) gm 8n chn I/O. Thanh ghi iu khin xut nhp tng ng la TRISD. Ngoai ra PORTD con la cng xut d kiu cua chun giao tip PSP (Parallel Slave Port) [3]. Chc nng cu th cac chn trong PORTD nh sau [4]:

Hinh 2.13 Chc nng cac chn trong PORTD

Cac thanh ghi lin quan n PORTD bao gm [3]: - PORTD : cha gia tri cac pin trong PORTD. - TRISD: thanh ghi iu khin xut nhp. 2.2.6.5 PORTE PORTE ( RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng la TRISE. Cac chn cua PORTE co ngo vao analog. Bn canh o PORTE con la cac chn iu khienr cua chun giao tip PSP.[3] Chc nng cu th cua cac chn trong PORTE nh sau [4]:

Hinh 2.14 Chc nng cac chn trong PORTE Cac thanh ghi lin quan n PORTE bao gm [3]: - PORTE : cha gia tri pin trong PORTE.

- TRISE : iu khin xut nhp va xac lp cac thng s cho chun giao tip PSP. - ADCON1 : thanh ghi iu khin khi ADC. 2.2.7 TIMER 2.2.7.1 TIMER0 y la mt trong ba b m hoc inh thi cua vi iu khin PIC16F877A, Timer0 la b m 8 bit c kt ni vi b chia tn ( prescaler) 8 bit. Cu truc cua Timer0 cho phep ta la chon xung clock tac ng va canh tich cc cua xung clock. Ngt Timer0 se xut hin khi Timero bi tran. Bit TMR0IE ( INTCON) la bit iu khin cua Timer0. TMR0IE=1 cho phep ngt Timer0 tac ng, TMR0IE=0 khng cho phep Timer0 tac ng. S khi cua Timer0 nh sau [3]:

Hinh 2.15 S khi cua Timer0

Mun Timer0 hoat ng ch Timer ta clear bit TOSC ( OPTION_REG), khi o gia tri thanh TMR0 se tng theo chu ky xung ng h ( tn s vao Timer0 bng tn s oscillator). Khi gia tri thanh ghi TMR0 t FFh tr v 00h thi ngt Timer0 se xut hin mt cach linh ng. Mun Timer0 hoat ng ch counter ta set bit TOSC ( OPTION_REG), khi o xung tac ng ln b m se c ly t chn RA4/TOCK1. Bit TOSE (OPTION_REG) cho phep la chon tac ng vao b m. Canh tac ng se la canh ln nu TOSE=0 va canh tac ng se la canh xung nu TOSE=1. Khi thanh ghi TMR0 bi tran bit TM0IF (INTCON) se c set. y chinh la c ngt cua Timer0. C ngt nay phai c xoa bng chng trinh trc khi b m bt u thc hienjlaij qua trinh m. Ngt Timer0 khng th anh thc vi iu khin t ch sleep. B chia tn s ( presccaler ) c chia se gia Timer0 va WDT ( Watchdog Timer). iu o co nghia la nu prescaler c s dung cho Timer0 thi WDT^ se c h tr cua prescaler va ngc lai. Prescaler c iu khin bi thanh ghi OPTION_REG. Bit PSA (OPTION_REG) xac inh i tng tac ng cua prescaler. Cac bit PS2:PS0 (OPTION_REG ) xac inh ti s chia tn s cua prescaler. Xem lai thanh ghi OPTION_REG xac inh lai mt cach chi tit v cac bit iu khin trn[3]. Cac thanh ghi iu khin lin quan n Timer0 bao gm [3]: TMR0 ( ia chi 01h, 101h ): cha gia tri m cua Timer0. INTCON ( ia chi 0Bh, 8Bh, 10Bh, 18bh): cho phep ngt hoat ng (GIE va PEIE). OPTION_REG ( ia chi 81h, 181h ): iu khin prescaler. 2.2.7.2 TIMER1 Timer1 la b inh thi 16 bit, gia tri cua Timer1 se c lu lai trong hai thanh ghi (TMR1H:TMR1L). C ngt cua Timer1 la bit TMR1IF ( PIR1). Bit iu khin cua Timer1 la TMR1IE ( PIE).

Tng t nh Timer0, Timer1 cung co hai ch hoat ng: ch inh thi (Timer) vi xung kich la xung clock cua oscillator ( tn s cua Timer bng tn s cua oscillator) va ch m ( Counter) vi xung kich la xung phan anh cac s kin cn m ly t bn ngoai thng qua chn RC0/T1OSO/T1CKI ( canh tac ng la canh ln). Vic la chon xung tac ng ( tng ng vi vic la chon ch hoat ng la Timer hay Counter ) c iu khin bi TMR1CS ( T1CON) [3]. S khi cua Timer1 [4]:

Hinh 2.16 S khi cua Timer1 Ngoai ra Timer1 con co hai chc nng reset input bn trong iu khin bi mt trong hai khi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON) c set, Timer1 se ly xung clock t hia chn RC1/T1OSI/CCP2 va RC0/T1OSO/T1CKI lam xung m. Timer1 se bt u m sau canh xung u tin cua xung ngo vao. Khi o PORTC se bo qua s tac ng cua hai bit TRISC va PORTC c gan gia tri 0. Khi clear bit T1OSCEN Timer1 se ly xung t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1 co hai ch m la ng b (Synchronous) va bt ng b (Asynchronous). Ch m c quyt inh bi bit iu khin T 1SYNC (T1CON). Khi T 1SYNC = 1 xung m ly t bn ngoai se khng c ng b vi xung clock bn trong, Timer1 se tip tuc qua trinh m khi vi iu khin ch sleep va ngt do Timer1 tao ra khi bi tran co kha nng anh thc vi iu khin .

Khi T 1SYNC =0 xung m vao Timer1 se c ng b hoa vi xung clock bn trong. ch nay Timer1 se khng hoat ng khi vi iu khin ang ch sleep.[3]. Cac thanh ghi lin quan n Timer1 bao gm [3]: INTCON ( ia chi 0Bh, 8Bh, 10Bh, 18Bh ): cho phep ngt hoat ng (GIE va PEIE). PIR1 ( ia chi 0Ch ): cha c ngt Timer1 ( TMR1IF). PIE1 ( ia chi 8Ch): cho phep ngt Timer1 ( TMR1IE). TMR1H ( ia chi 0Eh ): cha gia tri 8 bit thp cua b m Timer1. TMR1L ( dia chi 0Eh): cha 8 bit cao cua b m Timeer1. T1CON ( ia chi 10h): xac lp cac thng s cho Timer1. 2.2.7.3 TIMER2 Timer2 la b inh thi 8 bit va c h tr bi hai b chia tn prescaler va potscaler. Thanh ghi cha gia tri m cua Timer2 la TMR2. Bit cho phep ngt Timer2 tac ng la TMR2ON ( T2CON). C ngt cau Timer2 la bit TMR2IF (PIR1). Xung ngo vao ) tn s bng tn s oscillator) c a qua b chia tn prescaler 4 bit ( vi cac ty s chia tn s la 1:1, 1:4, 1:16 va c iu khin bi cac bit T2CKPS1:T2CKPS0(T2CON)) [3]. S khi cua Timer2:

Hinh 2.17 S khi cua Timer2 Timer2 con c h tr bi thanh ghi PR2. Gia tri m trong thanh ghi TMR2 se tng t 00h n gia tri cha trong thanh ghi PR2, sau o c reset v 00h. khi reset thanh ghi PR2 nhn c gia tri mc inh FFh. Ngoai ra ngo ra cua Timer2 con c kt ni vi khi SSp do o Timer2 con ong vai tro tao ra xung clock ng b cho khi giao tip SSP. Cac thanh ghi lin quan n Timer2 bao gm : INTCON ( ia chi 0Bh, 8Bh, 10Bh, 18Bh): cho phep hoat ng toan b cac ngt (GIE va PEIE). PIR1( ia chi 0Ch) : cha c ngt Timer2 ( TMR2IF). PIE1 ( ia chi 8Ch ) : cha bit iu khin Timer2 ( TMR2IE). TMR2 ( ia chi 11h) : cha gia tri m cua Timer2. T2CON ( ia chi 12h) : xac lp ca thng s cua Timer2. PR2 ( ia chi 92h) : thanh ghi h tr cho Timer2. 2.2.8 ADC ADC (Analog to Digital Converter) la b chuyn i tin hiu t tng t sang s. PIC16F877A co 8 ngo vao analog (RA4:RA0 va RE2:RE0). Hiu in th chun

VREF co th c la chon la VDD, VSS hay hiu in th chun c xac lp trn hai chn RA2 va RA3. Kt qua chuyn i tin hiu t tng t sang s la 10 bit s tng ng va c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s dung b chuyn i ADC cac thanh ghi nay co th c s dung nh cac thanh ghi thng thng khac. Khi qua trinh chuyn i hoan tt, kt qua se c lu vao hai thanh ghi ADRESH : ADRESL, bit ADCON0 c xoa v 0 va c ngt ADIF c set. Quy trinh chuyn i tin hiu t tng t sang s bao gm cac bc sau: Thit lp cac thng s cho b chuyn i ADC:

Chon ngo vao analog, chon in ap mu ( da trn cac thng s cua thanh ghi ADCON1). Chon knh chuyn i AD ( thanh ghi ADCON0). Chon xung clock cho knh chuyn i AD ( thanh ghi ADCON0). Cho phep b chuyn i AD hoat ng (thanh ghi ADCON0). - Thit lp cac c ngt cho b AD: Clear bit ADIF. Set bit ADIE. Set bit PEIE. Set bit GIE - i cho ti khi qua trinh ly mu hoan tt.-Bt u qua trinh chuyn i ( set bit GO / DONE ).

- i cho ti khi qua trinh chuyn i hoan tt bng cach: Kim tra bit GO / DONE , nu GO / DONE =0 thi qua trinh chuyn i hoan tt. Kim tra c ngt.-oc kt qua chuyn i va xoa c ngt, set bit GO / DONE ( nu cn tip tuc

chuyn i).

- Tip tuc thc hin cac bc 1 va 2 cho cac qua trinh chuyn i tip theo [3].

Hinh 2.18 S khi b chuyn i ADC Cac thanh ghi lin quan n b chuyn i ADC bao gm [3]: INTCON ( ia chi ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep cac ngt cac bit GIE, PEIE PIR1 ( ia chi 0Ch): cha c ngt AD ( ADIF). PIE1 ( ia chi 8Ch): cha bit iu khin AD( ADIE). ADRESH ( ia chi 1Eh) va ADRESL ( ia chi 9Eh): cac thanh ghi cha kt qua chuyn i AD. ADCON0 ( iac chi 1Fh) va ADCON1 ( ia chi 9Fh): xac lp cac thng s cua b chuyn i AD.

PORTA ( ia chi 05h) va TRISA ( ia chi 85h): lin qun n cac ngo vao analog PORTA. PORTE ( ia chi 09h) va TRISE ( iac hi 89h): lin quan n cac ngo vao analog PORTE. 2.2.9 TRUYN THNG NI TIP 2.2.9.1 USART USART ( Universal Synchronous Asynchronous Receiver Transmitter) l mt trong hai chun giao tip. USART cn c gi l giao din giao tip ni tip ni tip SCI (Serial Communication Interface). C th s dng giao din ny cho cc giao tip vi thit b ngoi vi, vi cc vi iu khin khc hay vi my tnh. Cc dng ca giao din ngoi vi bao gm: - Bt ng b (Asynchronous) - ng b _ Master mode - ng b _ Slave mode Hai pin dng cho giao din ny l RC6/TX/CK v RV7/RX/DT, trong RC6/TS/CK dng truyn xung clock (baud rate) v RC7/RX/DT dng truyn data. Trong trng hp ny ta phi set bit TRISC v SPEN (RCSTA cho php giao din USART. Pic16F877A c tch hp sn b to tc baud BRG ( Baud Rate Genetator) 8 bit dng cho giao din USART. BRG thc cht l mt b m c th s dng cho c hai dng ng b v bt ng b v c iu khin bi thanh ghi PSBRG. dng bt ng b, BRG cn c iu khin bi bit BRGH (TXSTA). dng ng b tc ng ca bit BRGH c b qua. Tc baud do BRG to ra c tnh theo cng thc sau:

Trong X l gi tr ca thanh ghi RSBRG ( X l s nguyn v 0