Keysight Technologies 2018.03meptec.org/Resources/9 - Barnes.pdf · 2018-05-04 · Bruce...

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Keysight Technologies 2018.03.29

Heidi Barnes

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S I G N A L I N T E G R I T Y A N D P O W E R I N T E G R I T Y

© Keysight Technologies 2018

Hewlett-Packard

Agilent Technologies

Keysight Technologies

Bill and Dave’s Company

and the HP Way

High Frequency

Simulation Tools

Test and Measurement

3

T H E T R A N S M I S S I O N O F I N F O R M AT I O N


~25,000,000,000 bits per second

01010101011101110110 ~2 bits per second

http://www.sleewee.com/sos-distress-signal.php

https://www.cloudyn.com/blog/10-facts-didnt-know-server-farms/

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F O L L O W T H E R E T U R N PAT H


The Channel ADS Channel Simulator

Poor Ground Return - Fail Engineered Design - Pass

Eye Diagram

(Overlay of rising and

falling data transitions)

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E N G I N E E R E D D E S I G N V S . C O S T LY D E B U G / R E D E S I G N


What is so hard about stringing a wire

between the transmitter and the receiver?

In 1858…signal quality declined rapidly, slowing

transmission to an almost unusable speed. The

cable was destroyed the following month when

Wildman Whitehouse applied excessive voltage

to it while trying to achieve faster operation.

Transatlantic telegraph cable

Where was the SI Engineer in 1858?

6

N E T L I S T O F C O N N E C T I O N S


Modern High Density Electronics

➢ 1000’s of nets

➢ 1 ground net

• Barely noticeable on a schematic

• Typically the largest copper net in layout

7

W H AT D E S I G N M A R G I N D I D I G I V E U P ?


Marisa Alia-Novobiliski, “AFRL, NextFlex leverage open-source

community to create flexible circuit system” AFRL Feb. 2, 2018

8© Keysight Technologies 2018

9

WAT C H O U T F O R H I G H C U R R E N T D E N S I T I E S I N T H E G R O U N D R E T U R N PAT H


▪ Electronic devices produce HEAT

▪ Joule losses in metallization produce HEAT

▪ Heat is transferred to the ambient (conduction, convection, radiation)

▪ Heat causes a Temperature rise in the electronic circuits

Thermal validation is needed to avoid▪ Component overheating

▪ Thermal stress

▪ Electronic malfunctioning

10

WAT C H O U T F O R C U R R E N T C O N S T R I C T I O N P O I N T S


Coupled Electro-Thermal Equations

ks

Electric resistance Rs [V/A] Thermal resistance Rk [K/W]

QRTT k12 IRVV s12

…Where electric resistance Rs

changes with temperature T

…Where the injected heat flux Q

changes with voltage V

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H I G H C U R R E N T D E N S I T Y I N A S I N G L E P O I N T G R O U N D R E T U R N C O N N E C T I O N


Equivalent cross section via has more

conductive cooling than the trace.

Wide trace provides conductive cooling for the via.

27 mil trace ≅ Via Cross Section 200 mil trace >> Via Cross Section

ADS PIPro

Simulation

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M O D E R N C I R C U I T S A R E N E V E R J U S T D C


+ + + +

- - - -

dt

dVCI

Current flow equals

capacitance times the

rate of voltage change.

Voltage equals

inductance times the

rate of current change

dt

dILV

Electric field

between two

plates

Magnetic fields

surrounding the

current in a wire.

+ _

LC

Current equals

voltage divided by

the resistance

R

VI

Steady state

R

ResistorCapacitor

Inductor

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T H E B E G I N N I N G S O F M A X W E L L’ S E Q U AT I O N S F O R E L E C T R O M A G N E T I C T H E O R Y ( E M )


Oliver Heaviside

1850-1925

Voltages and Currents are changing with Time and Distance

(Magnitude and Phase)

• Create a simple model of a

transmission line.

• Utilize calculus to analyze the

model when summing a series of

incremental length sections.

For small R and G

Sinusoidal Input Resulting Relationships

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E R I C B O G AT I N – “ S I G N A L I N T E G R I T Y E VA N G E L I S T ”


0C

LZ

1

0

LvCZ

Derivation from Telegrapher

Equations:

Derivation from transmission

line charging:

L

LL

L

vCI

VVvC

v

x

xVCIthen

v

xt

t

QIxCC

1Z and

CVQ , ,

Independent

of Length

The Math….

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The Channel has finite length:

• Speed of Tx : Signal Rise-time

• Type of Data : Data Rate Gb/s

• Speed of Channel: Time Delay

FA S T E R R I S I N G E D G E H A S H I G H E R F R E Q U E N C I E S


dBFrequency3

%8020

22.0Time Rise

ps

mils

Dkvelocity

12

psDataRateNRZ

1IntervalUnit

V=IR

What is high speed ?

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G R O U N D R E T U R N D I S C O N T I N U I T Y I N A C O N N E C T O R T R A N S I T I O N


1 2 3 4 5 6 7 8 90 10

-4

-3

-2

-1

-5

0

freq, GHz

dB

(Perf

ect_

Matc

h_21m

il..S

(2,1

))dB

(Sin

gle

_C

_21m

il..S

(2,1

))dB

(Sin

gle

_C

LC

_21m

il..S

(2,1

))

MICROSTRIP TRANSMISSION LINE DISCONTINUITY EXAMPLE

NO DISCONTINUITY (50 OHM MATCHED IMPEDANCE)

CAPACITIVE DISCONTINUITY (50 OHM MATCHED IMPEDANCE)

L-C-L FILTER DISCONTINUITY (50 OHM MATCHED IMPEDANCE)

MICROSTRIP

C

L-C-L

INS

ER

TIO

N L

OS

S S

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(d

B)

FREQUENCY (GHz)

AGILENT ADS

SIMULATION

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E N E R G Y L O S T D U E T O I M P E D A N C E R E F L E C T I O N S C A N R A D I AT E


Edge plating

Shielded

cavities

Controlled Impedance

Transmission Lines

Ground Signal Ground

Interconnects

Chip and Wire on PCB

Ground Fill

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I T D E P E N D S … . I N E E D A S I M U L AT O R !


Too much loss and no signal gets through……

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D E S I G N C O N 2 0 1 8 : 3 2 T O 5 6 G B / S S E R I A L L I N K A N A LY S I S A N D

O P T I M I Z AT I O N M E T H O D S F O R PAT H O L O G I C A L C H A N N E L S T U T O R I A L


32 Gb/s NRZ Signaling

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I M P E D A N C E I S S T I L L A C H A L L E N G E


Supply Consumer

It takes time for the supply

to respond to the demand.

If the flow at the supply is

different than at the

consumer what happens?

21© Keysight Technologies 2018

Natural

Response

Power Rail

Step

Load

AC Load

Forced

Response

Volts

Amps

Keysight Infiniium

S-Series Oscilloscope

Load Current

T I M E D O M A I N P O W E R R A I L R I P P L E D U E T O A L O A D T R A N S I E N T

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I

VZ

Target

Target Impedance Calculation

Max Ripple

Max Transient Load

Voltage

Regulator

Module

VRM

PCB Power

Distribution

Network

PDN

Package +

Die Circuit

LOAD

P O W E R I N T E G R I T Y I S D E L I V E R I N G T H E R I G H T P O W E R T O T H E L O A D


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Decoupling Capacitors

40% Fewer

ComponentsTarget Z

Original

Decaps

Optimized

Decap

Design

F L AT I M P E D A N C E V S F R E Q U E N C Y F O R B E S T P E R F O R M A N C E

DesignCon Paper 2017: H. Barnes, J. Carrel, S. Sandler, “Power Integrity for 32 Gb/s SERDES Transceivers”

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E N E R G Y S W I N G S B E T W E E N T H E L A N D T H E C


𝑉 𝑡 = 𝐿𝑑𝑖

𝑑𝑡𝐼 = න𝐶

𝑑𝑉

𝑑𝑡

Energy stored in

the Magnetic FieldEnergy stored in

the Electric Field

𝐸𝐵 L

𝑍 = 𝑗𝜔𝐿 𝑍 =−1

𝑗𝜔𝐶

Phase V Leads I Phase V Lags I

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𝑍0 =𝐿

𝐶

𝑄 =𝑍0

𝑅𝑡𝑜𝑡𝑎𝑙

𝑓0 =1

2𝜋 𝐿𝐶

𝒁𝒑𝒆𝒂𝒌 = 𝒁𝟎 ∙ 𝑸

∆𝑉 = ∆𝐼 ∙ 𝑍𝑝𝑒𝑎𝑘

1 Amp

AC SweepZpeak=1.5 Ohms

Zo=250 mOhms

𝟏

𝝎𝑪𝝎𝑳

Parallel L-C in the PDN

V R Lsupply Cbulk

ESRCbulk

ESLCbulk

Cdecap

ESRCdecap

ESLCdecap

Impedance vs. Frequency

1.5 Ohms

20 mOhms6 nH 100 nF

Flat VRM

+6dB/Octave - 6dB/Octave

PA R A L L E L I N D U C TA N C E C A N R E S O N AT E W I T H T H E D E C O U P L I N G C A PA C I TA N C E


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E M S I M U L AT O R S C A N O P T I M I Z E L AY O U T F O R L O W L


L

+ -Loop Inductance

L increases

with loop area

CAP

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D E C O U P L I N G I S R E Q U I R E D T O E X T E N D T H E P O W E R S U P P LY B A N D W I D T H


Step Load Forced

Power Supply

Simple R-L Model

PROBLEM

The Load can make the Power

Supply Control Loop go unstable

1st Order SOLUTION

Design for Flat Impedance at the

output to keep V and I in phase

and the feedback stable.

Frequency Domain

Power Supply Output Impedance

Time Domain

Voltage and Current vs. Time

LOG SCALE LOG SCALE for time

R

𝝎𝑳

𝑓𝑠𝑢𝑝𝑝𝑙𝑦

ControlledNo Control

High Z

V R L

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D E S I G N I N G F O R F L AT I M P E D A N C E


Step Load Forced

PROBLEM

Find the decoupling capacitor that

will maintain a Flat Z Load for the

Power Supply

1st Order SOLUTION

Add Bulk Capacitor to

maintain flat impedance

Frequency Domain

Power Supply Output Impedance

Time Domain

Voltage and Current vs. Time

LOG SCALELOG SCALE for time

Target Z

𝝎𝑳𝒔𝒖𝒑𝒑𝒍𝒚

𝑓𝑠𝑢𝑝𝑝𝑙𝑦

Power

Supply

Decoupling

Ideal Bulk C

𝟏

𝝎𝑪𝒃𝒖𝒍𝒌

𝐶𝑏𝑢𝑙𝑘 =𝐿𝑠𝑢𝑝𝑝𝑙𝑦𝑍𝑇𝑎𝑟𝑔𝑒𝑡2

Flat Z Load

V R Lsupply Cbulk

Ztarget

Flat Z Design

R-L Supply

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PA R A L L E L R E S O N A N C E C A U S E S I M P E D A N C E P E A K


Package/Die

DecouplingVRM

Control

No PDN

Decoupling

Step Forced

Time Domain

Voltage and Current vs. TimeFrequency Domain

Impedance at the Package Pin

No PDN

Decoupling

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I N C R E A S E S PA R T C O U N T T O R E A C H TA R G E T Z


Package/Die

DecouplingVRM

Control

Low ESR 100 uF

Capacitor

Step Forced

Time Domain



Target Z

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F L AT Z = M A X I M U M S TA B I L I T Y A N D M I N I M U M R I P P L E


Package/Die

DecouplingVRM

Control

Flat PDN

Decoupling

Step Forced

Time Domain



Target Z

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F O L L O W T H E R E T U R N PAT H T O S U C C E S S


“Ground is for potatoes and carrots, electrical circuits use a return path”

Bruce Archambeault – EMC Consultant and IBM Distinguished Engineer

Check for high current density constriction points.

Control the impedance by engineering the return path.

Minimize the inductance in the power delivery and return path.

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Keysight Technologies 2018.03meptec.org/Resources/9 - Barnes.pdf · 2018-05-04 · Bruce...

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Transcript of Keysight Technologies 2018.03meptec.org/Resources/9 - Barnes.pdf · 2018-05-04 · Bruce...