Keith Bergevin Senior Design Engineer 4234 54 th St., Bldg 620 Sacramento, Calif. 95652-1521 Phone:...
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Keith Bergevin Senior Design Engineer 4234 54 th St., Bldg 620 Sacramento, Calif. 95652-1521 Phone: (916) 231-1652, Fax: (916) 231-2818 email: [email protected] http://www.dmea.osd.mil Defense Microelectronics Activity Rapid Obsolescence in Recent Designs – Is There a Solution?
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Transcript of Keith Bergevin Senior Design Engineer 4234 54 th St., Bldg 620 Sacramento, Calif. 95652-1521 Phone:...
Keith BergevinSenior Design Engineer4234 54th St., Bldg 620Sacramento, Calif. 95652-1521Phone: (916) 231-1652, Fax: (916) 231-2818email: [email protected]://www.dmea.osd.mil
Keith BergevinSenior Design Engineer4234 54th St., Bldg 620Sacramento, Calif. 95652-1521Phone: (916) 231-1652, Fax: (916) 231-2818email: [email protected]://www.dmea.osd.mil
DefenseMicroelectronics
Activity
DefenseMicroelectronics
Activity
Rapid Obsolescence inRecent Designs – Is
There a Solution?
Rapid Obsolescence inRecent Designs – Is
There a Solution?
22
Presentation RoadmapPresentation Roadmap
Why are recent generation designs highly susceptible to obsolescence?
What options are available?
ASIC redesign methodologies
Ensuring a complete solution
Why are recent generation designs highly susceptible to obsolescence?
What options are available?
ASIC redesign methodologies
Ensuring a complete solution
33
Why are Recent Generation Designs Becoming an Enormous Problem?
Why are Recent Generation Designs Becoming an Enormous Problem?
Consist primarily of ASIC devices Virtually sole source
Custom ASICs have limited supply – typically one fabrication run
Unique design eliminates component supply “sharing”
Very difficult to redesign High density, complex devices
Design documentation is critical but often deficient
No correlation between part numbers and design functions
Consist primarily of ASIC devices Virtually sole source
Custom ASICs have limited supply – typically one fabrication run
Unique design eliminates component supply “sharing”
Very difficult to redesign High density, complex devices
Design documentation is critical but often deficient
No correlation between part numbers and design functions
44
What Options are Available?What Options are Available?
Direct FFF replacement? No! ASICs perform specific functions – with the exception of
FPGAs, finding an equivalent device number will not suffice
Exhaustive database search for second source? No! Custom designs render search of other programs for
equivalent devices useless
The only remaining option – various levels of redesign Component, board, or system redesign
Direct FFF replacement? No! ASICs perform specific functions – with the exception of
FPGAs, finding an equivalent device number will not suffice
Exhaustive database search for second source? No! Custom designs render search of other programs for
equivalent devices useless
The only remaining option – various levels of redesign Component, board, or system redesign
55
The Dilemma of ASIC RedesignThe Dilemma of ASIC Redesign
Recent program upgrades experienced obsolescence within two years – why go through the same process? Valid argument - Without a change in approach, the solution
will again be temporary
Insufficient data exists on the obsolete module, resulting in prohibitively expensive redesign proposals Unfortunately, this is a common occurrence
Where does this lead us?
Recent program upgrades experienced obsolescence within two years – why go through the same process? Valid argument - Without a change in approach, the solution
will again be temporary
Insufficient data exists on the obsolete module, resulting in prohibitively expensive redesign proposals Unfortunately, this is a common occurrence
Where does this lead us?
66
The Prudent Way Out of This MessThe Prudent Way Out of This Mess
The Previous slides have established the following: The “quick & easy” solutions do not exist A redesign approach is the only remaining option Insufficient documentation results in difficult and costly
redesigns Option (2) was recently implemented without eliminating
obsolescence
An ideal solution would include the following: Tools and methodologies to reduce NRE redesign costs Implement designs with better DMS immunity Realize obsolescence is inevitable - apply methodologies that
enable device re-targeting without costly redesign
The Previous slides have established the following: The “quick & easy” solutions do not exist A redesign approach is the only remaining option Insufficient documentation results in difficult and costly
redesigns Option (2) was recently implemented without eliminating
obsolescence
An ideal solution would include the following: Tools and methodologies to reduce NRE redesign costs Implement designs with better DMS immunity Realize obsolescence is inevitable - apply methodologies that
enable device re-targeting without costly redesign
77
DMEA’s ASIC Redesign Approach
DMEA’s ASIC Redesign Approach
Apply cutting edge tools & methodologies to accurately characterize legacy component
Scrutinize components to select least vulnerable DMEA flexible foundry Select components commonly used by industry to provide
greater assurance of future availability
Provide complete, verifiable, vendor-independent documentation VHDL, Verilog, EDIF, etc.
Apply cutting edge tools & methodologies to accurately characterize legacy component
Scrutinize components to select least vulnerable DMEA flexible foundry Select components commonly used by industry to provide
greater assurance of future availability
Provide complete, verifiable, vendor-independent documentation VHDL, Verilog, EDIF, etc.
88
Developing an Accurate Redesign Specification – An
Extremely Difficult Requirement
Developing an Accurate Redesign Specification – An
Extremely Difficult Requirement
Many obsolete ASICs contain up to 1M gates
ASIC devices perform unique functions Vendor data sheets provide no functional descriptions
Specific component number provides no functional information
Package size, type, & pin-out vary greatly
Virtually impossible to have 100% test coverage Board level test programs typically cover small subset of
ASIC functions
Many obsolete ASICs contain up to 1M gates
ASIC devices perform unique functions Vendor data sheets provide no functional descriptions
Specific component number provides no functional information
Package size, type, & pin-out vary greatly
Virtually impossible to have 100% test coverage Board level test programs typically cover small subset of
ASIC functions
99
DMEA Developments in the Specialty of Device
Characterization
DMEA Developments in the Specialty of Device
Characterization
Hardware Modeling: A novel approach to ASIC redesign Method of interfacing actual legacy silicon into simulation
environment
The device becomes a logic model which is instantiated into the VHDL design for simulation
Enables creation of a fast, efficient and 100% accurate simulation model of the legacy device
Enables direct functional comparison of Legacy vs. redesigned component
Hardware Modeling: A novel approach to ASIC redesign Method of interfacing actual legacy silicon into simulation
environment
The device becomes a logic model which is instantiated into the VHDL design for simulation
Enables creation of a fast, efficient and 100% accurate simulation model of the legacy device
Enables direct functional comparison of Legacy vs. redesigned component
1010
Hardware Modeler ConfigurationHardware Modeler Configuration
High-end WorkstationHigh-end WorkstationHardware ModelerHardware Modeler
Device AdapterDevice Adapter
1111
Prototype DevelopmentPrototype Development
1. Synthesize VHDL model to Field Programmable Gate Array (FPGA)
2. Migrate test vectors to board or chip level tester
Vectors translated from VHDL test benches
3. Apply test vector set to legacy device and FPGA prototype
4. Compare vector output files
5. Test prototype at customer facility
1. Synthesize VHDL model to Field Programmable Gate Array (FPGA)
2. Migrate test vectors to board or chip level tester
Vectors translated from VHDL test benches
3. Apply test vector set to legacy device and FPGA prototype
4. Compare vector output files
5. Test prototype at customer facility
1212
Fabrication OptionsFabrication Options
DMEA Flexible Foundry
Form, fit, function replacement via commercial devices Re-Target VHDL to ASIC with matching footprint
FPGA to ASIC conversion
FPGA die repackaging
Replace legacy device with FPGA Low-cost approach for small quantities
May require modification to board layout
DMEA Flexible Foundry
Form, fit, function replacement via commercial devices Re-Target VHDL to ASIC with matching footprint
FPGA to ASIC conversion
FPGA die repackaging
Replace legacy device with FPGA Low-cost approach for small quantities
May require modification to board layout
1313
SummarySummary
Recent generation designs are extremely susceptible to obsolescence Database and other tracking tools largely ineffective in
finding replacement devices
DMEA is maintaining a leadership role in applying tools, techniques, and expertise to combat obsolete ASICs
Adhere to sound DMS redesign practices to ensure long term cost-effective solutions
Recent generation designs are extremely susceptible to obsolescence Database and other tracking tools largely ineffective in
finding replacement devices
DMEA is maintaining a leadership role in applying tools, techniques, and expertise to combat obsolete ASICs
Adhere to sound DMS redesign practices to ensure long term cost-effective solutions
