June, 2010 Quality Excellence as Seen Through the Eyes of ... · TM Freescale, the Freescale logo,...

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-AUT-F0861

Quality Excellence as Seen Through the "Eyes of the Customers

June, 2010

Jim Baillie Vice President – Global Quality

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 222

Agenda

►Quality Vision

►Organizational Update

►Guiding Principles

►Strategies and Initiatives

►Quality Metrics

►Quality of Design

►Customer Support Strategy

►Summary/Q&ATurning today’s challenges into the competencies of tomorrow


Quality Vision

Achieving world-class product quality and problem resolution responsiveness by utilizing a defect prevention mindset and instinctive quality culture that results in a relentless pursuit of total customer loyalty in everything we do.


Freescale Senior Leadership Team

Michel Cadieux Human Resources

and Security

Vivek MohindraStrategy & Business

Transformation

Alan CampbellChief Financial

Officer

Henri RichardGlobal Sales &

Marketing

Reza KazerounianMicrocontroller

Solutions Group

Tom DeitrichRF, Analog & Sensor

GroupAlex PepeSupply Chain

Rich BeyerChairman & CEO

Ken HansenChief Technology

Officer

Lisa SuNetworking

and MultimediaGroup

John Holmes ActingLegal

Jim BaillieQuality

►An unwavering and uncompromising commitment to Quality Excellence by the Freescale Executive Team


Freescale Quality Leadership Team

►A global team of over 425 Quality professionals dedicated to achieving world-class performance…..

Jim BaillieVice President

Quality

John TheissDie Mfg & TSO

Ed HallSupplier Quality& External Mfg

Bob SulskiRASG Quality

Mike McCullarNMG Quality

Garic PowerMSG Quality

MBG Quality Supply Chain Quality Quality Functions

Garic PowerGlobal PA Labs

Bernard AzalbertQuality Systems

John TheissGlobal REL Labs

Gil WernerCustomer Support

Strategy

Ralf MelzerEMEA Quality

Hisayuki KamataJapan Quality

Haneefa IbrahimAsia Quality & FMO

Regional Quality


DEFECTS► See the world through the eyes of the customer

by protecting them from defects and assuming every reported failure is “guilty” until proven innocent

► Shifting the paradigm from defect detection/correction to a defect prevention methodology

► Using NPI qualification as a validation step that all the development processes have been successfully completed

► Ensuring every employee believes that they own Quality and strives to do their job right the first time

Quality Guiding Principles


Strategies & Initiatives

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

0

10

20

30

40

50

2009Baseline

Q1'10 Q2'10 Q3'10 Q4'10

PPM

FREESCALE Product Quality - NPI PPMYear to Date

0

10

20

30

40

50

2009Baseline

Q1'10 Q2'10 Q3'10 Q4'10

PPM

FREESCALE Product Quality - NPI PPMYear to Date

0

10

20

30

40

50

2009Baseline

Q1'10 Q2'10 Q3'10 Q4'10

PPM

Freescale Product Quality - PPMYear to Date

0

10

20

30

40

50

2009Baseline

Q1'10 Q2'10 Q3'10 Q4'10

PPM

Freescale Product Quality - PPMYear to Date

0

400

800

1200

1600

2000

2009Baseline

Q1'10 Q2'10 Q3'10 Q4'10

Coun

t of C

QI S

tarts

Freescale Product Quality - CQI

Year to Date

0

400

800

1200

1600

2000

2009Baseline

Q1'10 Q2'10 Q3'10 Q4'10

Coun

t of C

QI S

tarts

Freescale Product Quality - CQI

Year to Date

Quality Metrics

~20% reduction in 2010 ~25% reduction in 2010

~33% reduction in 2010

Projection

►Aggressive Quality improvement goals and action plan established for 2010

►PPM and customer return metrics trending down ahead of target

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 999

Agenda

►Quality Abstract/Vision




►Quality Metrics





Design

►New Technology Introduction

Process

►Design for Testability

►Design for Manufacturability

Qualityby

Design

Quality by Design


Functional IP &design collateral

Start Planning

Start Execution

Prototype PilotPlanningTCG2

TCG3 M1

Technology Development(Design)

Certified technology

Specification Compliant IP &design collateral

RD2 End of LifeMC

G5

Start EOL EOL

ProductionCertification M3M2

Manufacturing(Build)

TCG

TCG Technology Council gate End development or technology lifeMC

GMCG Manufacturing Council gateMilestonesM

ML0

Technology spec Defined

ML1

Technology Ready for

Design

ML2

Technology Ready for Prototype

ML3

Technology Ready for Product

Maturity LevelAssessments

MCG4

Factory Ready for Volume Production

►Freescale has a detailed New Technology Introduction Process where Quality requirements are built in from the beginning.

New Technology Introduction and Quality Checkpoints


Design for Test, Verification and Test Maturity Quality checkpoints earlier in the design development process.

Quality requirements are reviewed at points 1, 2, 3 and 4

Design for Test, Verification and Test Maturity Quality checkpoints earlier in the design development process.

Quality requirements are reviewed at points 1, 2, 3 and 4

Manufacture

Product Manufacturing(Deliver)

Start Concept

Product Definition(Define)

Product Development(Design)

Planning End of Life

Start Manufacture

Start EOL

EOL

PCG5

ExecutionPCG3

Start Planning

Start Execution

PCG4

FeasibilityConceptPCG0

PCG1

StartFeasibility

PCG2

PilotPrototype M1 ProductionCertification M3

ProductionCAB

M2

Qual LotReviews

Tapeout

Maturity Levels Aligned to NPI Lifecycle


Product

LaunchE

xecutionP

lanningFeasi-bility

Test Coverage

Verification

Design For Test

Resource Planning

Test Quality Levels

Test Requirements Specification

Zero Defects


DFT Maturity Matrix – Clear Standard for Design-for-TestDFT Maturity Level 0 Level 1 Level 2 Level 3 Level 4

Digital ► Ext. generated functional

► SAF > 90% ► SAF > 95% ► Transition >85%► Path Delay >= 200 out of 1000

most critical

► Transition > 90%► SAF > 99%► Bridge > 80%► Small-delay defect coverage► Selective path-delay testing

Analog(ADC, DAC, PLL,

Oscillators)

Ext. generated functional ► Partial Scan Wrapper ► Full Scan Wrapper (DC)► Ad-hoc analog test

modes (based on designer intuition)

► Additional signals to increase analog testability

► DC scan stuck-at > 95%► AC Scan Wrapper if module

running near Fsys.

► Partial Analog BIST and/or critical test points (tool determined test points)

SRAM ► Externally generated

► Large Array MBIST generated

► March C- or PMOVI algorithm

► Data Retention support► Checkerboard & Inverse

tests► Different data

backgrounds run on the March

► All RAMs BIST tested with same BIST type

► BIST March LR/LA better► BIST X/Y fast addressing► BIST Bit Mapping► SCAN write through

► Programmable BIST based on 14N coverage

► Sep BIST for DP RAMS► BIST Intra-Word Coverage► BIST Any-bit-fast tests► SDD BIST Support **► LWSH BIST support **► BIST paths >= Func paths.** - Only required if RAM has test mode

ROM ► Externally generated

► MBIST tested► 100% SAF

► 100% AF (inc and dec addressing)

► BIST X/Y fast addressing► MBIST Bit Mapping Support► Scan read support► BIST MISR Aliasing probability <

1PPM (>= 20-bit MISR)

► BIST Any-bit-fast tests► BIST paths >= Functional paths.► BIST MISR Aliasing probability <

0.1PPM (>=24-bit MISR)

NVM, Flash ► Ext. generated functional based

► User modes only

► Array Test Modes ► Basic BIST supported by State Machine

► Independent erasable test row

► Configurable BIST► DC Scan logic > 98%► Massively parallel test enabler

(UTI or BDM based)► MBIST Bit Mapping Support

► Code Execution BIST that detects Address Decode SOF and Address Coupling Faults

► BIST paths >= Functional paths► DC Scan logic part > 99%► Transition delay on logic > 85%

I/O ► Ad hoc, functionally generated

► Most I/Os controllable via register

► Full control* of all pads I/O state (jtag or registers)

► Full control* of all pad electricals ► All pad electrical controls observable via ATPG scan

Parametric, IDDQ, HVST, Burn-in, Voltage Margin, JVT Support

► No DFT support for IDDQ, High Voltage Stress, Burn in, Voltage Margin, Low Frequency and JVT

► Power down mode for IDDQ

► Limited / Partial supportMBIST used for Burn IN

► Scan based ATPG for IDDq► Burn In Mode covering Memories

and partial scan► PLL Bypass for low frequency

► DFT techniques to enable HVT and voltage margin test for designs including level shifters

► Burn In Mode covering 100% memories and scan


Design for Manufacturability Roadmap

DefectClass DFM Technique 0.13um 90nm <90nm

Redundant Vias DeployRequired

DeployRequired

DeployRequired

Wire Optimization DeployRequired

DeployRequired

DeployRequired

Random

Logic Restructuring Pilot Pilot

Timing-aware Floating Fill Deploy Deploy

Vdd/VssTied Fill Deploy Deploy

Model-based CMP analysis Pilot

Systematic

Model-based Litho analysis

DeployRequired

DeployRequired


Agenda

►Quality Abstract/Vision




►Quality Metrics





CQ

I IN

CID

EN

TS

Pareto Analysis – Failure Modes

►The yellow bars represent reported quality issues that have been verified and containment/corrective actions implemented internally in the failure mode category indicated

►The green bars represent reported quality issues being validated with customers to determine if they are Freescale caused so they may be redistributed to the internal failure mode categories and resolved

FIELDFOCUSED

INTERNALLYFOCUSED


Field Quality – World Wide Team

x

x

Andrew CameronJim MackieEKB, Scotland

Sixto ArjonillaRichard HofbeckBernhard SannwaldAntoinette EspirituYork MoellerhenJens PfeifferGeorg BreuckerChristian TrefflerRichard JammersAyda Kilian x

x

x

x

Tony LiuMark MaShenzhen, China

H.N.TayKLM

Paul ChaeSeoul, Korea

x

Kok Pin YeohPenang, Malaysia

Becker ChenPing ChenShanghai, China

x

xxx

Ken CavanaughMilwaukee, WI

Luis PinedaDetroit, MI

Rich ZinkusLake Zurich, IL

x

x

x

Jeff ShadleHorseham, PA

x Hiram CerilloAustin, TX

Keith WilsonMarshall, IL

Peter ThomasMitch CampbellFlorida

xGabriel LaraFabiano CostaJuan Cortes – FQE FA LABGuadalajara, Mexico

x

Marcello MacedoSao Paulo, Brasil

Jose Aurelio NajeraMexico City, Mexico

Jose Medina LopezChihuahua/Juarez, Mexico

x

x Kenny Heong Singapore


Managing Quality perceptionResponses to the customer in hours

DATA MININGDATA MINING

Non Quality issues

Customer Induced

Signature Analysis

Counterfeit / GreyDirect interfacewith customer

FQE

CUSTOMERREPORTS

ISSUE CQI

Faster resolution times “Protecting the Customer from Defects”Preserving Freescale critical resources – unresolved issues, proactive, NPI, etc.

Field Failure VerificationField Failure Verification

EOS/ESDNo Trouble FoundCustomer Caused

Customer Application/ManufacturingVisual Inspection

Reflow and ReseatA-B-A Verification

X-rayCurve trace

Socketed Applications BoardESD Audits

FA LABSUnresolvedNon repeat

Detailed Analysis

RETURNRETURNCENTERSCENTERS

ATETESTING

PE/TE

APPS

CQI

TNI

Customer Return Support Strategy


► Quality metrics trending positively

► Quality Systems process discipline being emphasized

► Lessons learned, best practices and error proofing fan-out

► Technical problem solving capability being expanded in the field

► Culture is becoming more Quality driven

► Continue driving higher levels of customer loyalty

SummaryTaking Aim at Best-in-Class Quality


Back-up

21


“As customer expectations for Quality rise, Freescale is transforming its strategy in incident reduction, new product execution and culture.

It begins with customer centric metrics that reflect their experiences with Freescale product. It requires a paradigm shift from detection/correction proficiency to defect prevention methodology using advanced problem solving tools. This overflows into deployment of a rigorous NPI phase gate methodology and qualification process that ensures Quality and Reliability are designed in.

Lastly, Freescale Executives are driving an instinctive Quality culture that is not only displayed by their leadership but also in key processes that touch every employee.”

Quality Presentation Abstract


Culture:►Implement Corporate Quality targets into FSL bonus plan and PM goals►Enhance information flow through SLT Quality Reviews, Weekly Reporting, and

Containment/Prevent Reoccurrence:►2009 top problem parts including NPI devices►2010 Product PPM drivers

Continuous Process Improvement/Excursion Prevention►Front End - wafer fab/foundry►Back End - material/assembly-test/subcontractor

New Product Development Process Optimization:►Technology certification►Design methodology►Test comprehensiveness

NTF – TNI/EOS-ESD Reduction – Customer Partnerships:►Field failure verification►Customer correlation/escalation►Geo/Disti focus

Quality Improvement Strategy


Quality By Design

June, 2010 Quality Excellence as Seen Through the Eyes of ... · TM Freescale, the Freescale logo,...

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