JFETS AND MOSFETS

Instructor

Engr: Mir Muhammad Lodro

Lecturer

Department of Electrical (Telecomm) Engineering

Sukkur IBA

OUTLINES

JFETs N-channel JFET P-channel JFET Operation of JFET JFET terminals JFET drain curves JFET trans-conductance JFET biasing

Ohmic region Active region

MOSFET Depletion mode Enhancement mode

Fig: JFET biased for conduction (common source configuration)

JFET OPERATION

DRAIN CHARACTERISTIC CURVES FOR JFET

VGS controls ID

For the JFET in the following figure, VGS(off)= - 4v and IDSS=12mA. Determine minimum value of VDD required to put the device in constant current area of operation.

Since VGS(off) = -4 V ,VP=4V. The minimum value of VDS for the JFET to be in its constant current area is

In the constant current area with VGS=0 V,

Drop across drain resistor

Apply kirchhoff’s law around the drain

circuit

This is the required value of VDD to put the transistor in constant current area

Sol:

EXAMPLE:

JFET FORWARD TRANS-CONDUCTANCE

JFET BIASING

Self-bias Voltage-divider bias

SELF-BIAS JFETS

For n-channel JFET,IS=ID and VG=0 ,VS=IDRD gate to source voltage is

Thus

Drain voltage with respect to ground is

Since VS=IDRS , the drain to source voltage is

Find VDS and VGS for following JFET circuit, internal parameter values are such as gm, VGS(off), and IDSS are such that a drain current of approximately 5mA is produced . Another JFET even of the same type may not produce the same results when connected in this circuit due the variations in parameter value.

Solution

Here ID=IS

VGS is –ve for n-channel

EXAMPLE

MID-POINT BIAS

Usually desirable to bias a JFET near mid-point of its transfer characteristic curve where ID=IDSS/2Mid-point allows maximum amount of drain current swing between IDSS

and 0.When VGS=VGS(off)/3.4 = ID=IDSS/2

Select resistor values for RD and RS to setup an approximate mid-point bias. For this particular JFET, the parameters are IDSS =12mA and VGS(off)= -3 V. VD should be approximately 6 V.

EXAMPLE

SolutionFor mid-point biasing

Then

VOLTAGE DIVIDER BIAS

Fig: n-channel JFET with voltage-divider bias (IS=ID)

Voltage at source of JFET must be more positive than voltage at the gate in order to keep the gate-source junction reverse-biased

Gate voltage is set by resistors R1 and R2

Source voltage

Gate to source voltage is

And source voltage is

The drain current can be expressed as

EXAMPLE

Determine ID and VGS for the JFET with voltage divider bias given that for this particular JFET the internal parameter values are such that VD=7V.

Solution

Calculate gate to source voltage

For voltage divider Q-point is determined as follows For ID=0

For VGS=0

The point at which load line intersects the transfer characteristic curve is known as Q-point

Fig: Generalized dc load line for a JFET with voltage-divider bias

EXAMPLE

Determine the approximate Q-point for the JFET with voltage-divider bias , given that this particular device has transfer characteristic curve of

Solution

First establish two points for the bias line i-e ID and VGS

Approximate Q-point values are ID=1.8mA and VGS=-1.8 V

MOSFET (METAL OXIDE SEMI-CONDUCTOR FET)

MOSFET is another category of field effect transistor. The MOSFET differs from JFET in that it has no pn junction structure.Gate is insulated from channel by silicon dioxide (SiO2) layer

MOSFETModes

Depletion (D-MOSFET)

Enhancement (E-MOSFET)

D-MOSFET (DEPLETION MOSFET)

N-channel MOSFET operates in depletion mode when a negative gate to source voltage is applied and in enhancement mode when positive gate to source voltage is applied

These devices are generally operated in Depletion mode

D-MOSFET OPERATION

Greater the negative voltage on gate, greater the depletion of n-channel electrons

With positive gate voltage, more electrons are attracted into the channel, thus increasing channel conductivity.

E-MOSFET (ENHANCEMENT-MOSFET)

•E-MOSFET operates only in enhancement mode and has no depletion mode•E-MOSFET has no structural channel (substrate extends completely to SiO2 layer)•Positive gate voltage induces a channel by creating a thin layer of negative charges in substrate region adjacent to SiO2 layer. •For gate voltage below threshold there is no channel • conductivity of channel is enhanced by increasing gate-to-source voltage and thus pulling more electrons into the channel area

Fig: E-MOSFET schematic symbols

Broken lines symbolize the absence of physical channel

THANKS

Drs Ian Munro Ross (front) and G.C Dacey jointly developed experimental procedure for measuring characteristics of Field Effect Transistor in 1955.

(AT&T archives)