Jerry Tutorial Short
Transcript of Jerry Tutorial Short
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Digital System Design using VHDL and the
Spartan-3E FPGA Board
Gennadiy Chernyavskiy
Tech 499
12/06/06
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Contents
Chapter 2: A Design Example
2.1 Design Description..3Chapter 3: Design Implementation using Xilinx
3.1 Introduction....4
3.2 Procedure for programming the Spartan-3E..5
References17
Appendix A: VHDL code.18Appendix B: UCF.22
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Chapter 2
2.1 Design Description
The goal of the project is to design a digital system for controlling the tail lights of a 1965
Ford Thunderbird using VHDL and synthesizing the logic circuit into a Spartan-3EFPGA board. The sequence of the lights for a 1965 Ford Thunderbird is shown in Figure
1-1.
Figure 1-1: The sequence of the lights for a 1965 Ford Thunderbird.
In order to get this project functioning, we first wrote a VHDL file called tail_light.vhd
(copy of this file is provided in Appendix A). The board has a 50MHz oscillator (see [2]pages 22-23); therefore, the clock signal is so fast that the human eye is unable to see the
sequence of the flashing lights. As a consequence, we have to add an additional file
called counter.vhd (copy of this file is provided in Appendix A), which will slow theincoming clock down. In order for these two files to work together, we have to write the
top_level.vhd (copy of this file is provided in Appendix A). A step by step tutorial will
explain how to load this project into the Xilinx board.
Note: First the user should apply power and then connect the USB cable to the Spartan-
3E board. If any change is done to the (vhdl) code, the user should first remove the USB
cable, second remove power, third reapply power to the Spartan-3E board and lastreconnect the USB cable. At this point it is safe to reload the modified code into the
Xilinx board.
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Chapter 33.1 Introduction
In order to create a project to program the Spartan-3E FPGA, it is necessary to take a few
preliminary steps. First, a project needs to be created in Xilinx. The project is named
tail_light. Then the specific characteristics of the hardware that are being used areselected as shown in Figure 3-1.
Figure 3-1: Project Properties Window
Finally, the source files counter.vhd, tail_light.vhd, and top_level.vhd are selected as the
source code to be used to program the Spartan-3E FPGA.
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3.2 Procedure for Programming the Spartan-3E FPGA
STEP 1: Select the tail_light folder in the CD-ROM and copy to the C:\ drive of yourcomputer. Then double click on the highlighted icon shown below. This will open the
Xilinx Project Navigator window.
Figure 3-2: tail-light project
Once the Xilinx Project Navigator window opens there will be 4 windows available for
you to see.
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Figure 3-3: Four windows
Window 1: The Sources Project window lists the name of files that constitutes the
project tail_light.
Window 2: Displays the files source code. Here the user can write new code or make
changes to existing code.
Window 3: The Processes window shows the different process that can be done to the
selected code. Here the user can compile the source code, generate synthesis reports,
generates a file for an FPGA, and download files to an FPGA.
Window 4: The log window displays any messages from the processes window. For
example, after Xilinx checks the syntax of a given source code, it will display the resultsof that process.
STEP 2: The tail_light project requires the use of 7 LEDs and 4 switches.
It is necessary to assign pins from the Spartan-3E FPGA to these components.For this project, switches SW1, SW2, SW3, and SW4 are used for input from the user as
shown in Figure 3-4.
1
2
3
4
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Figure 3-4: Switches used for Left, Right, Hazard, and Reset signals
Four Switches
Pin assignments for the switches:
NET "SW" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; NET "SW" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; NET "SW" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; NET "SW" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
Taken from Spartan 3-E Starter User Guide (see Reference Manual pages 159-164)
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LEDs - LD1, LD2, LD3, LD4, LD6, LD7, and LD8 are used as output as shown in
Figure 3-5.
Figure 3-5: Eight LEDs
Eight Discrete LEDs
UCF Constraints for Eight Discrete LEDs
NET "LED" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
NET "LED" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW |DRIVE = 8
Taken from Spartan 3E Starter User Guide (see Reference Manual pages 159-164)
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Using the three pinout tables, it is possible to assign a switch or LED to a pin on the
Spartan-3E.The clock signal comes from an oscillator found on the Spartan-3E board as shown in
Figure 3-6. Pin C9 on the Spartan-3E is the designated pin for the clock signal input.
Figure 3-6: 50 MHz Oscillator.
STEP 3: Make sure that top_level-struct is selected in the Sources window. Thenexpand the User Constraints in the Processes window and double clickAssign PackagePins. This is where you tell Xilinx which pins on the Spartan-3E will be used (see Figure
3-7).
On-Board 50 MHz Oscillator
CLK_50MHz: (C9)
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Figure 3-8
When finished, click the save icon. This action will create the .ucf file for the top_level-
struct file and it will contain the pin assignments for the Spartan-3E.
STEP 4: Again, make sure that top_level-struct is selected in the Sources window.
Then, in the Processes window, expand the Synthesize-XST process and then double
click it. This action will check the syntax of the source code for top_level-struct andconvert the source code into a netlist of gates. A synthesis report will also be produced.
When the synthesis is finished, green check marks should be displayed just like in Figure
3-9, indicating that top_level-struct has been compiled successfully.
Figure 3-9
STEP 5: Expand the Implement Design process and double click on it. This is where
the netlist is translated, mapped, placed and routed into the logic circuits of the Spartan-3E FPGA. After this process has been run, green check marks should be displayed just
like in Figure 3-10.
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Figure 3-10
STEP 6: Expand the Generate Programming File process. Right click on GenerateProgramming File and select Create Bit File. Double clickGenerateProgramming
File. This process creates a bit file that is used to program the Spartan-3E chip. Again,after this process is finished, green check marks should be shown as in Figure 3-11.
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Figure 3-11
Step 7: Now you are ready to program the Spartan-3E chip. Plug in the USB cable to
the computer. Connect the Spartan-3E board to powerFIRST, and then connect the USBcable to the board. This order must be followed for the Spartan-3E chip to be
programmed properly.
Step 8: Now double click on Configure Device (iMPACT) under the GenerateProgramming File process. You will be asked how you want the device configured.
Select Boundary Scan Mode and clickNext. Then select Automatically connect to
cable and identity Boundary Scan Chain and clickFinish as shown in Figure 3-12.
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Figure 3-13
Open the top_level.bit file. Should a warning appear declaring that the Startup Clock has
been changed to the jtagclk, disregard the warning and clickOK.
Step 9: Right click on the depiction of the Spartan 2 chip and select Program (see
Figure 3-14).
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Figure 3-14
A Programs Options window will open. Simply clickOKand the top_level.bit file will
be downloaded to the Spartan-3E chip. If the download is successful, the message
will display. Also, LD should be blinking. This is the output from the counter and isused for testing purposes.
Step 10: Now it is time to test the program. Turn on the reset button (switch SW4) and
then turn it back off. The following table shows the correct outputs with thecorresponding inputs from the user.
As the inputs are applied, only the left and right signals should flash sequentially. The
hazard signal, the left and right signal combined, should flash concurrently.
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Input
Left Right Hazard
Output
LD1, LD2, LD3, LD6, LD7, LD8
Off Off Off No output
Off Off On Hazard signals on
Off On On Hazard signals onOn On On Hazard signals on
On Off On Hazard signals on
On Off Off Left signal on
On On Off Left signal on
Off On Off Right signal on
After it has been verified that the given inputs produce the proper output, the project is
complete.
References[1] Full Spartan-3E Documentation
http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Prod
ucts&Nav2=Programmable
[2] Spartan-3E Starter User Guide (Reference Manual)
http://www.digilentinc.com/Data/Products/S3EBOARD/S3EStarter_ug230.pdf
[3] Spartan-3E Board (Schematic Diagram)http://www.digilentinc.com/Data/Products/S3EBOARD/S3E%20Starter_sch.pdf
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next_all_lights if (l_r_haz = "100") then
next_state
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all_lights
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Appendix B: UCF (user constraints file)
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "C9" ;NET "clkdiv" LOC = "F12" | IOSTANDARD = LVTTL ;NET "l_r_haz" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;NET "l_r_haz" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;NET "l_r_haz" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;NET "lights" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "lights" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "lights" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "lights" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "lights" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "lights" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;NET "rst" LOC = "N17" | PULLUP ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
#Do not forget:#Start User Defined Timing Constraints#End User Defined Timing Constraints