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SemiconductorMemories

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

December 20, 2002

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Memory ClassificationMemory ArchitecturesThe Memory CorePeripheryReliabilityCase Studies

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Read-Write MemoryNon-VolatileRead-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

Random

AccessNon-Random

Access

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO

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Word 0

Word 1

Word 2

WordN2 2

WordN2 1

Storagecell

M bits M bits

Nwords

S0

S1

S2

SN2 2

A0

A1

AK2 1

K 5 log2N

SN2 1

Word 0

Word 1

Word 2

WordN2 2

WordN2 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals

Input-Output(M bits)

Decoder

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Amplify swing torail-to-rail amplitude

Selects appropriateword

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Advantages:1. Shorter wires within blocks2. Block address activates only 1 block => power savings

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DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed

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WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2

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WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND

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Programmming using theActive Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5 x 7 )

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All word lines high by default with exception of selected row

WL[0]

WL[1]

WL[2]

WL[3]

VDDPull-up devices

BL[3]BL[2]BL[1]BL [0]

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No contact to VDD or GND necessary;

Loss in performance compared to NOR ROMdrastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8 x 7 )

Programmming using

the Metal-1 Layer Only

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Polysilicon

Threshold-alteringimplant

Metal1 on Diffusion

Programmming using

Implants Only

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Metal bypass

Polysilicon word lineK cells

Polysilicon word lineWLDriver

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

WL

(c) Use silicides

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PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pref

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Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

toxtox

Device cross-section Schematic symbol

G

S

D

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0 V

2 5 V 0 V

DS

Removing programming voltage leaves charge trapped

5 V

2 2.5 V 5 V

DS

Programming results inhigher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection

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Source

Substratep

Gate

Drain

n1 n1

FLOTOX transistor Fowler-Nordheim I-V characteristic

20 30 nm

10 nm

-10 V10 V

I

VGD

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WL

BL

VDD

Absolute threshold controlis hardUnprogrammed transistor might be depletion

2 transistor cell

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Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1 source n1 drainprogramming

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Unit Cell

Word line(poly)

Source line(Diff. Layer)

Courtesy Toshiba

GateONO

FGGateOxide

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Word linesSelect transistor

Bit line contact Source line contact

Active area

ST I

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!"#$%&'()"*+",-'(".*/!0+1STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended

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WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ

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GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6

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Static power dissipation -- Want R L largeBit lines precharged to V DD to address t p problem

M3

RL RLVDD

WL

Q Q

M1 M2

M4

BL BL

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Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

V BL VPRE VBIT VPRECS

CS CBL+------------= =V

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!"#$%&'((%)*+',-./012+1T DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.DRAM memory cells are single ended in contrast to

SRAM cells.The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correct operation.

Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

1is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

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DV(1)

V(1)

V(0)t

VPRE

VBL

Sense amp activatedWord line activated

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Uses Polysilicon-Diffusion CapacitanceExpensive in Area

M1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly

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DecodersSense AmplifiersInput/Output BuffersControl / Timing Circuitry

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!"#$%&'"(&)*Collection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder

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A2A2

A2A3

WL 0

A2A3A2A3A2A3

A3 A3A0A0

A0A1A0A1A0A1A0A1

A1 A1

WL 1

Multi-stage implementation improves performance

NAND decoder using2-input pre-decoders

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Precharge devices

VDD

GND

WL3

WL2

WL1

WL0

A0A0

GND

A1A1

WL3

A0A0 A1A1

WL 2

WL 1

WL 0

VDD

VDD

VDD

VDD

2-input NOR decoder 2-input NAND decoder

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Advantages: speed (tpd does not add to overall memory access time)Only one extra transistor in signal path

Disadvantage: Large transistor count

2-input NOR decoder

A0S0

BL 0 BL 1 BL 2 BL 3

A1

S1

S2

S3

D