IWORID 2002 - P.Randaccio Medipix2 Parallel Readout System 4-th IWORID Amsterdam 8 – 12 September...

IWORID 2002 - P.Randaccio

Medipix2 Parallel Medipix2 Parallel Readout SystemReadout System

4-th IWORID Amsterdam 8 – 12 September 2002

V. Fanti, R. Marzeddu, P. Randaccio

Dipartamento di Fisica e Sezione INFN Cagliari


Dynamic imaging with Medipix2Dynamic imaging with Medipix2

ONE CHIP

256x256x14 bits per frame

25 frames per second

2.3 x 107 bits per second

2.9 x 106 bytes per second

EIGHT CHIPS

1.8 x 108 bits per second

2.3 x 107 bytes per second

Serial I/O: 180 MHz

Parallel I/O 32 bit: 5.7 MHz

However, the readout speed should be as high as possible to reduce the dead time; aiming to 10% DT we should reach frequencies 10 times higher.


The PC platform as acquisition system

Actually the PC is the best solution for:

• Acquisition

• Processing

• Visualization

• Storage

in imaging systems.


PC architecturePC architectureNorth Bridge (Hi speed devices) South Bridge (Low speed devices)

I/O & interconnect busses:

• Host Bus• Memory Bus• AGP (Graphics)• V-link (interbridge connection)• ATA (Hard disks)• PCI• USB• IEEE 1394 firewire• Legacy (ISA) …. obsolete


Computer speedComputer speedThe typical processor clock frequency is 1 GHz

The word length is 32 bits = 4 bytes

but ….

the data transfer rate is not 4 Gbyte/s !

The speed is limited by the bus clock:

• Host bus (between CPU and North Bridge): 200 MHz

• Memory : 200 MHz AGP(4x) : 132 MHz

• ATA : 100 MHz PCI : 33 MHz

• ISA : 8 MHz


Maximum transfer speedMaximum transfer speed(the effective one)(the effective one)

Parallel busses single mode burst mode DMA

Legacy bus 2.7 ---- 4.2

PCI bus 10 60 122

All values expressed in Mbytes/s

Serial busses Low speed Full speed

USB 1.1 0.2 1.5

Firewire IEEE1394a 12.5 50


The PCI bus : essentialsThe PCI bus : essentials

Peripheral Component Interconnect (PCI)

32-bit multiplexed data/address bus

Clock frequency : 33 MHz (66 MHz)

Maximum (theo) transfer rate : 132 MB/s (264 MB/s)

3.3V & 5V operability

Plug and Play

single mode e burst mode transaction

reflected wave switching


Transmission lineTransmission lineStandard method: incident wave switchingStandard method: incident wave switching

V

X

VTH

bus end

Incident wave

incident point

t < Tprop.

V

X

VTH

bus end

t > Tprop.

Incident wave

VME, ISA, EISA, …. busses

BUSRtermRterm

Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10

Incident point


PCI method: reflected wave switchingPCI method: reflected wave switchingV

X

VTH

bus end

Incident wave

incident point

t < Tprop.

V

X

VTH

bus endincident point

Tprop<t <2 Tprop.

Reflected wave

BUS

Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10

Incident point

Initiator Target


PCI bus length PCI bus length limitlimit

T_cyc

Clock device #1

T_low

T_high

T_skew

Clock device #2

Dev #nDev #1

d

Dev #2

T_prop 10 ns ; d = bus length ; v = 2 ·108 m/s

Worst case:

x = 2d

x = v ·T_prop = 2 m

d 1 m (theo)

Tprop = 30 ns – Tval – Tsu - Tskew


BridgeBridge

Local bus (CMOS)

PCI bus

BRIDGE

Logic & I/O circuits

Connection between PCI bus and local bus for

timing, operating voltage (5V/3.3V/2.2V), protocols


PLX PCI9054 Bus Master I/OPLX PCI9054 Bus Master I/O AcceleratorAccelerator


Bridge PLX9054Bridge PLX9054

• Bus Master interface

• 32-bit data bus, 28-bit address bus

• 3.3V, 5V tolerant

• Local bus clock up to 50 MHz

• Dual DMA channels

• Six Read/Write FIFOs 16 Lword

• Single and burst mode operation (block transfer up to 16 LWord)

• Unlimited burst length

• Memory spaces remap (up to 256 Mbytes of memory)


Burst read modeBurst read modeLocal BusPCI Bus

PCI Read Request

The bridge prefetches data from Local Bus device at max. clock speed

Prefetched data is stored in the internal FIFO

PCI bus reads data from the FIFO

The PCI bridge returns data from internal FIFO in sequential address read operations until FIFO is empty

Read FIFO (16 x 32 bit)

Read D0

Read D1

Read D15

= empty= full

Read D2


I/O burst advantageI/O burst advantage

North bridgeCPU

South Bridge

Local BusPCI Bus

FIFO

PCI/Local bridge

Host/PCI bridge

FIFO

Host memory

Bus access (address, data, control cycles) slows down I/O operation. The prefetch with FIFOs reduces the time needed for bus access operations by a factor 16. CPU reads data directly from FIFO at very high speed.


Reading data from Medipix2 parallel portReading data from Medipix2 parallel port

Acquisition rate is about 64 MByte/s

32 bits - 16 MHz mean acquisition rate

PCI bridge reads 16 Lword from Medipix2 parallel port through local bus

CPU reads data from FIFO


Most PCs do not support burst read !Most PCs do not support burst read !

If the North Bridge has no FIFO (Intel bridges) the CPU readout phase is slower

Acquisition rate is about 10 MByte/s


Reading from a PCI deviceReading from a PCI device

1 M

4 GBIOS ROM

PCI memory

System RAM

CPU

It is like a memory block transfer from PCI Address Space to program data.

From the software point of view it is just a move instruction.

Each data transfer between bridges and busses is transparent to the software.


PCI Local SpacesPCI Local Spaces

Local bus

BRIDGE

Space1Space0 Space2 Space3 Space4

Configuration Address Space

I/O Address Space

A PCI device can be configured as five memory spaces with configurable address offset and range


Memory space reserved for Memory space reserved for Medipix dataMedipix data

Medipix matrix data read through parallel port

Serial data

ControlStatus

Not assigned

Not assigned

Not assignedLocal Space 4

Local Space 3

Local Space 2

Local Space 1

Local Space 0


Medipix2

Testboard

127 I/O & Power Supply

PCI BoardMotherboard Flat cables 34-pin

MPRS: general schematicMPRS: general schematic


Line drivers from Medipix to DAQ

CMOS - LVDS drivers

Power Supply, voltage regulator 3.3V – 2.2V

MotherboardMotherboard

Drivers

LvdsCmos

Z-adapter

Medipix

2.2 V Voltage

Regulator

Test Board

34-pin I/O flat cables


Motherboard pictureMotherboard picture

Medipix TB Connector DRIVERs Voltage Reg.

OUT Conn.IN Conn.

CMOS LVDS

Z-adapter


DAQ: PCI boardDAQ: PCI boardPCI Universal card for 32-bit, 33 MHz slot.

Main components:

PCI Bridge: connection from PCI Bus to Local Bus

Registers for output lines

Buffers for input lines

Address decode circuit

Local Clock circuit

Voltage regulator 3.3V

Serial Eeprom

Registers Buffers

Bridge

PCI

Clock

3.3 V

AddressDecode

EEPROM


PCI Board picturePCI Board picture

Address decode

Input connector

Output connector

Output registers

Input buffers

Clock

3.3V reg.

Eeprom Bridge


PCI Board picturePCI Board picture


SoftwareSoftware

Software Hardware

LibraryMedipix.dll

(C++)

Control, acquisition & visualization

(VBasic)

PCI board

Motherboard

Medipix2


Utility software:Utility software: PCI board control panel PCI board control panel

Scan PCI bus

Open device

Read/write test

Internal registers configuration


Acquisition utilitiesAcquisition utilities

Set the DACs

Reset matrix data

Set pixel registers

Readout


Image acquisition timingImage acquisition timingMedipix2

MPRSRaw data

memory

MPRS

MPRS

MPRS

Readout

Readout

Stop

Start

X-rays

Image reconstruction

routine

Image Memory

Medipix photon counting phase

time

2 ms

~38 ms

~ 0 ms

~ 0 ms


Image reconstructionImage reconstruction

Any image processing is made by software after the acquisition, in particular:

Image reconstruction with deserialization and derandomization

The total time is : 256x8x14x32xTs = 917504xTs

where Ts is the period of the inner software loop.

The reconstruction time depends on CPU speed: however with a normal PC it lasts no more than 10 ms

The software does the reconstruction during the Medipix2 photon counting phase, so it does not slow down the process.


ConclusionsConclusions• Parallel readout seems to be appropriate for the Medipix2 dynamic imaging acquisition.

• Actual PCs are convenient platforms for the image acquisition, processing, storage and visualization.

• Interfaces based on PCI bus are easy to develop and fast enough for our purposes.

• The hardware complexity is transparent for the software thanks to the bridges.

• Image reconstruction made by software simplifies MPRS hardware design.

IWORID 2002 - P.Randaccio Medipix2 Parallel Readout System 4-th IWORID Amsterdam 8 – 12 September...

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Transcript of IWORID 2002 - P.Randaccio Medipix2 Parallel Readout System 4-th IWORID Amsterdam 8 – 12 September...