Iterative Versus Sequential Circuits Set 4.pdfregister u6 to be loaded. ... lp6 lp7 hp1 hp2 hp3 hp4...

Iterative Versus Sequential Circuits

primary inputs

primary outputs

moduleCI CO

PIC2C1C0 Cn–1 Cn

POn–1

PIn–1

PO

moduleCI CO

PI

PO

moduleCI CO

PI

PO

PI1

PO1PO0

PI0 cascadinginput

cascadingoutput

boundaryinputs

boundaryoutputsCopyright © 2000 by Prentice Hall, Inc.

Digital Design Principles and Practices, 3/e

moduleCI CO

PICi Ci +1

Ci

POi

PO

CLK

CLOCK

register

PIi

Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e


XCMP

Y

X0 Y0

EQI EQO

XCMP

Y

EQI EQO

XCMP

Y

EQI EQO

XCMP

Y

EQI EQOEQ1

X1 Y1

EQ2

X2 Y2 X(N–1) Y(N–1)

EQ3 EQNEQ(N–1)

(b)

1

EQO

EQI

X Y(a)

CMP


EQOEQID Q

CLK

CLOCK

X

Y

CMP



SSS

COUT CIN

X

S

Y

COUT CIN

X Y

COUT CIN

X Y

COUT CIN

X Y

x2 y2 x1 y1 x0 y0

c3c4

c2 c1

x3 y3

c0

s2 s1 s0s3


CIN

B

A

COUT

S S

COUT

CIN

RCOUTD Q

CLK

CLOCK

B

A

RESET_L

full adder


Synchronous Design Methodology

Synchronous systems – all flip-flops are clocked by the same common clock.To ensure reliable operation:

Minimize and determine the amount of clock skew in the system.Ensure that flip-flops have positive setup and hold time margins, including allowance for clock skew.Identify asynchronous inputs and synchronize them with the clock. Ensure that the synchronizers have low probability of failure.

Clock Skew

Difference between arrival times of the clock at different devices.

IN

Q1

Q2

CLOCK

CLOCKD

incorrect

correct

(b)

(a)

Q

CLK

D Q

CLK

DIN

CLOCKFF1 FF2

Q1

CLOCKD

Q2

a long, slow path


CLOCK CLOCK

CLOCK1

CLOCK2

CLOCK_L CLOCK1

CLOCK2

CLOCK3

all in sameIC package

(a) (b)


Clock Skew

Q

CLK

D

CLK

CLKCLK

CLK

CLK

CLK

CLK

Q

CLK

D

Q

CLK

D Q

CLK

D Q

CLK

D

CLOCKQ1

FF1 FF2


Q

CLK

D

CLK

CLKCLK

CLK

CLK

CLK

CLK

Q

CLK

D

Q

CLK

D Q

CLK

D Q

CLK

D

CLOCK

Q1

FF1 FF2


Asynchronous Inputs

Synchronizer – circuit that samples an asynchronous input and produces an output that meets the setup and hold times required in a synchronous system.

SYNCIN

CLOCK

(system clock)

ASYNCIN

(asynchronous input)

synchronizer

D Q

CLK Synchronoussystem

CLOCK

ASYNCIN

SYNCIN

(a)

(b)


Asynchronous Inputs

SYNC2

CLOCK

(system clock)

ASYNCIN


SYNC1

D Q

CLK

synchronizers

D Q

CLK

Synchronoussystem

CLOCK

ASYNCIN

SYNC1

SYNC2

(a)

(b)


SYNC2

CLOCK

(system clock)

ASYNCIN


SYNC1

D Q

CLK

synchronizers

D Q

CLK

Synchronoussystem

Combinational logic

fanout


Asynchronous Inputs

Q2

CLOCK

(system clock)

ASYNCIN


Q1

D2

D1

D Q

CLK

state memorysynchronizer

D Q

CLK

SYNCIND Q

CLKCombinationalexcitation logic


Synchronous System Structure

DATA OUT

DATA INCOMMAND

CLOCK

CONTROL

CONTROL

CONDITIONS

CONTROL

DATA UNIT

OUTPUT

INPUT

CONTROLUNIT

(state machine)


valid

valid

valid

validData-unit result inputs andcontrol-unit excitation inputs

Control-unit state anddata-unit register outputs

CLOCK

Data-unitcontrol inputs

Data-unitconditions


Design ExampleShift and add multiplier

MPY/LPROD – Initially stores the multiplier, and accumulates the low-order bits of the product.HPROD – Initially cleared, and stores the high-order bits of the product.MCND – Stores the multiplicand.If low-order bit of MPY/LPROD

Is 1 then F = 9-bit sum of HPROD and MCND.Is 0 then F = HPROD extended to 9 bits.

HPROD

MCND

F = HPROD + MPY[0] • MCND

MC7

F8

MC0

F0

HP0HP7

MPY/LPROD

MPY0MPY7

shift

+


Design Example

74x163

CLR

CLK

LD

QA

QB

2

14

11

1

9

ENP

ENT

7

10

A

B

3

4

C

D

5

6

MAXCNT

QC

QD15

RCO

13

12

U10

RPU

+5 V

R

74x045 6

U11

CLKCLOCK

RESET

START

RESET

START

MPY0

MAXCNT

CLEARLDHP

LDMCND

MPYS1

MPYS0

RUNC

SELSUM

74x041 2

U11

74x043 4

U11

CLOCK

CLEAR

LDHP

LDMCND

MPYS1

MPYS0

SELSUM

Control Unit State Machine

Data Unit

LP[7:0]

HP[7:0]

MPY[7:0]

MCND[7:0]

LP0

MPY[7:0]

MCND[7:0]

LP[7:0]

HP[7:0]


LDMCND_L=0 enables the multiplicand register U1 to be loaded.LDHP_L=0 enables the HPROD register U6 to be loaded.MPSY[1,0]

= 11 enables the MPY/LPROD register U2 to be loaded.= 01 it shifts right during multiplication.= 00 at other time to preserve register content.

SELSUM=1 multiplexers U7 and U8 select adders U4 and U5 output otherwise it selects HPROD.CLEAR=1 the output of multiplexers U7 and U8 is cleared.

Design ExampleLDMCND_L=0 enables the multiplicand register U1 to be loaded.LDHP_L=0 enables the HPROD register U6 to be loaded.MPSY[1,0]

= 11 enables the MPY/LPROD register U2 to be loaded.= 01 it shifts right during multiplication.= 00 at other time to preserve register content.

SELSUM=1 multiplexers U7 and U8 select adders U4 and U5 output otherwise it selects HPROD.CLEAR=1 the output of multiplexers U7 and U8 is cleared.

IDLE

RUN

WAITINIT

RUNC = 1;LDHP = 1;MPYS = [0,1];SELSUM = MPY0;

CLEAR = 1;LDHP = 1;LDMCND = 1;MPYS = [1,1];

RESET

START′

MAXCNT′

START

1MAXCNT

START′

START


Design Example

7

74x377

G

CLK

1D 1Q

2Q

11

1

2

5

3

2D4

3D7

4D8

5D13

6D14

3Q6

9

5Q12

15

4Q

6Q

7D17 16

7Q

8D18 19

8Q

LDMCND_L

LDHP_L

MPYS0

MPYS1

MCND[7:0]

CLOCK

SELSUM

CLEAR

MCND0 MC0

MC1

MC2

MC3

MC4

MC5

MC6

MC7

MCND1

MCND2

MCND3

MCND4

MCND5

MCND6

MCND7

HP0

LP0

LP1

LP2

LP3

LP4

LP5

LP6

LP7

HP1

HP2

HP3

HP4

HP5

HP6

HP7

F1

F2

F3

F4

F5

F6

F7

F8

S0

S1

S2

S3

S4

S5

S6

S7

HP1

HP0

HP2

HP3

MC1

MC0

MC2

MC3

HP1

HP0

HP2

HP3

S1

S0

S2

S3

F0

F1

F2

F3

F[8:0]

HP[7:0]

MC[7:0]

S[7:0]

HP5

HP4

HP6

HP7

MC5

MC4

MC6

MC7

74x283

A0

C0

B0

S0

S1

7

4

10

5

6

A1

B1

3

2

A2

B2

14

15

A3

B3

12

11

S2

S3

9C4

1

13

74x283

A0

C0

B0

S0

S1

4

10

5

6

A1

B1

3

2

A2

B2

14

15

A3

B3

12

11

S2

S3

9C4

1

13

R

+5 VU1

U4 U7

U5

74x157

1A

1B

2A

2B

3A

3B

4A

4B

G

24

1Y

72Y

93Y

124Y

3

5

6

11

10

14

13

S1

15

HP5

HP4

HP6

HP7

S5

S4

S6

S7

F4

F5

F6

F7

U8

74x157

1A

1B

2A

2B

3A

3B

4A

4B

G

24

1Y

72Y

93Y

124Y

3

5

6

11

10

14

13

S1

15

74x081

23

U9

F8

S8

74x194

CLR

CLK11

1

S110

RIN2

S09

B4

QB14

A3 15

QA

C5 13

QC

D6 12

QD

LIN7

74x194

CLR

CLK11

1

S110

RIN2

S09

B4

QB14

A3 15

QA

C5 13

QC

D6 12

QD

LIN7

MPY[7:0] MPY0

MPY1

MPY2

MPY3

U2

U3

74x377

G

CLK

1D 1Q

2Q

11

2

5

3

2D4

3D7

4D8

5D13

6D14

3Q6

9

5Q12

15

4Q

6Q

7D17 16

7Q

8D18 19

8Q

U6F0

1

LP[7:0]

HP[7:0]

MPY4

MPY5

MPY6

MPY7


Algorithmic State Machines -ASM

Partition the system into two parts:Controller - ASM.Controlled architecture – data processor.

ASM

Algorithm is a well defined procedure consisting of a finite number of steps to the solution of a problem.Controller is a hardware algorithm or Algorithmic State Machine.ASMs can serve as stand-alone sequential network model.

ASMConditional outputs – Mealy model.State outputs – Moore model.State time:

Transition period.Stable period.

ASMState box.

Represents one state in the ASM.May have an optional state output list.Single entry.Single exit to state or decision boxes.

ASMDecision box.

Provides for next alternatives and conditional outputs.Conditional output based on logic value of Boolean expression involving external input variables and status information.Single entry.Dual exit, denoting if Boolean expression is true or false.Exits to decision, state or conditional boxes.

ASMConditional output box.

Provides a listing of output variables that are to have a value logic-1, i.e., those output variables being asserted.Single entry from decision box.Single exit to decision or state box.

ASM BlocksConsists of the interconnection of a single state box along with one or more decision and/or conditional boxes.It has one entry path which leads directly to its state box, and one or more exit pathes.Each exit path must lead directly to a state, including the state box in itself.A path through an ASM block from its state box to an exit path is called a link path.

ASM Block Example

ASM BlocksAn ASM block describes the operation of the system during the state time in which it is in the state associated with the block.The outputs listed in the state box are asserted.The conditions indicated in the decision boxes are evaluated simultaneously to determine which link path is to be followed.If a conditional box is found in the selected path then the outputs found in its output list are asserted.Boolean expression may be written for each link path. The selected link paths are those that evaluate to logic-1.

ASM Blocks

Iterative Versus Sequential Circuits Set 4.pdfregister u6 to be loaded. ... lp6 lp7 hp1 hp2 hp3 hp4...

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