Issues in Integrated Circuit Design for UHF RFID Zhihua WANG,Xuguang SUN, Chun ZHANG,Yongming LI...
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Transcript of Issues in Integrated Circuit Design for UHF RFID Zhihua WANG,Xuguang SUN, Chun ZHANG,Yongming LI...
Issues in Integrated Circuit Design for UHF RFID
Zhihua WANG,Xuguang SUN,Chun ZHANG,Yongming LI
Institute of Microelectronics, Tsinghua University,Beijing,100084,P.R.China
RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, pp.322-328
Dec.9-11,2007,Singapore
Advisor: Yens ho Reporter: C.C.Lan
RFIC Recognition and fulfillment Lab C.C.Lan 2
Outline
IntrouctionIssues in TagIssues in ReaderDesign InstancesConclusion
RFIC Recognition and fulfillment Lab C.C.Lan 3
Introduction
۞Bar code ۞Disadvantage-
۞Lack of programmability۞Limited storage capacity۞In sight operation distance and low data throughput
۞RFID system۞Consists of
۞A reader۞Several tags
RFIC Recognition and fulfillment Lab C.C.Lan 4
Issues in Tag
• Low Power Design
• Rectifier Design
• Anti-collision Mechanism
• Security Mechanism
• On-chip Antenna
RFIC Recognition and fulfillment Lab C.C.Lan 5
Low Power Design
• Digital:– Lower the supply voltage
• 1.5V supply voltage in 0.5 m CMOS process• 1.14V supply voltage in 0.18 m CMOS process• 0.6V supply voltage in 0.18 m CMOS process
– Lower the clock frequency• Clock separation technique(3.35~3.75MHz clock
for PIE decoding)• Digital clock manager(1MHz to produce a
synchronous 40KHz clock with Manchester-coded)
RFIC Recognition and fulfillment Lab C.C.Lan 6
Low Power Design
• Analog:– Voltage regulator
• Perform well as the input RF power varies more than 30dB
• Design regulator into two stages( near field, far field)
– On-chip oscillator• Ring oscillator• Current starve ring oscillator• Low voltage current mirrors
RFIC Recognition and fulfillment Lab C.C.Lan 7
Rectifier Design
M3
M4
M1
M2
VL VH
VP
VP
VDD
Vss
to ant.
Basic doubler
RFIC Recognition and fulfillment Lab C.C.Lan 8
Rectifier Design
PMOS
CPrMP1 Cbp
MPb
Rb
Rb
MnbCbn
CINF
IN
DC -
DC +
ferroelectriccapacitor
IVC(Internal Vth cancellation)
RFIC Recognition and fulfillment Lab C.C.Lan 9
Anti-collision Mechanism
• Aloha based protocol• To reduce the collision probability by separating
tag transmission in distinct time slot• Key research- to optimize the slot number
• Tree based protocol– Use a group splitting mechanism
• Disadvantage is the relatively long identification delay
• Adaptive binary splitting protocol– Improve to shorten identification time
RFIC Recognition and fulfillment Lab C.C.Lan 10
Security Mechanism
• Authentication– Mutual three-pass authentication
• Encryption– A low power encryption hardware using TEA
algorithm– SHA-1 algorithm
RFIC Recognition and fulfillment Lab C.C.Lan 11
On-Chip Antenna
• In some applications, where the operation distance is a primary consideration
• OCA can be an effective way to cut down the total cost and make the size of tag small
RFIC Recognition and fulfillment Lab C.C.Lan 12
Issues in Reader
• Carrier Leakage Problem
• CMOS PA design
RFIC Recognition and fulfillment Lab C.C.Lan 13
Carrier Leakage Problem
12 dBSwitchableAttenuator
Stage 1 (S-to-D)
Low-Noise Amplifier
Mode Selection(LBT or Talk)
Rx-InI-LO
Q-LO
I-Buffer
I-IF Amp
I-Mixer
I-IF Out
Q-IF Out
Q-IF Amp
Q-Buffer
Q-Mixer
Bias Circuit
RFIC Recognition and fulfillment Lab C.C.Lan 14
Carrier Leakage Problem
Coupler
Leak Total
Leak2
RF IN
DiffAmplifier
To IQ mixers
From IQ Mixers
VGAAmplitude
Tuning
Phase Tuning(fine)
Phase Tuning(coarse)
Leakage Canceller
VCO
DAPA
Tx Output
45 degSelection
Tx CancellerLeak1
RFIC Recognition and fulfillment Lab C.C.Lan 15
Carrier Leakage Problem
Tx PA
QPA
BR-LNA
IPA
Blocker Rejecting LNA
“ 0” “ 1”
RFID Tag
Tx=30dBm
Tx Leakage
Limiter
LNA
non-linearRSSI RSSI
Control Unit
Linear
Backscattered from RFID Tag
RFIC Recognition and fulfillment Lab C.C.Lan 16
Design Instances
• A passive RFID Tag with Standard EEPROM
• A security Module using XTEA Algorithm
• A Single Chip RFID Reader Transceiver
RFIC Recognition and fulfillment Lab C.C.Lan 17
A passive RFID Tag with Standard EEPROM
RF rectifier
Demodulator
Clock Extraction
Modulation Generator
Voltage limiter
Voltage Regulator
Reset
EEPROM
ChargePump
Logic Control
ANT
RFIC Recognition and fulfillment Lab C.C.Lan 18
A passive RFID Tag with Standard EEPROM
ANT
C1 C3 C5
C2 C4 C6M1
Modulation Signal
RFIC Recognition and fulfillment Lab C.C.Lan 19
A passive RFID Tag with Standard EEPROM
VDD_unreg
Ref
GND
VDD_reg
VoltageLimiter
LDO VoltageRegulator
RFIC Recognition and fulfillment Lab C.C.Lan 20
A security Module using XTEAAlgorithm
SUM
XOR SUM XORSUM
<<4
>>5
Deltai-1
SubkeyiA
SUM
XOR SUM XORSUM
<<4
>>5
Deltai
SubkeyiB
RFIC Recognition and fulfillment Lab C.C.Lan 21
A Single Chip RFID Reader Transceiver
900
PLL
ADC
Demod
Demod
ADC
VGA
VGA
Mod
Tx DataPA
Tx
Rx
I-LO
Q-LO
Q-BB
I-BB
off-chip cap
off-chip cap
LO
I-RxData
Q-RxData
RFIC Recognition and fulfillment Lab C.C.Lan 22
A Single Chip RFID Reader Transceiver
VDD VDD VDD
Vin
L5C5
Cf
Rf
Vg3 Vg2 Vg1
M4 M3 M1
M2
C4 C3
C1
L2C2 TL0
Rload
L1L3L4
RFIC Recognition and fulfillment Lab C.C.Lan 23
Conclusion
• looks into the UHF RFID IC design in which both tag and reader have their own design challenges
• Issues in RFID– Low power, energy harvesting, anti-collision,
security, and OCA in tag design– Carrier leakage and CMOS PA in reader