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Published in IET Power ElectronicsReceived on 9th November 2011Revised on 14th July 2012doi: 10.1049/iet-pel.2011.0419

ISSN 1755-4535

Analysis, design and implementation of zero-currenttransition interleaved boost converterM. Rezvanyvardom E. Adib H. Farzanehfard M. MohammadiDepartment of Electrical Engineering, Isfahan University of Technology, Isfahan, IranE-mail: m.rezvanyvardom@cc.iut.ac.ir

Abstract: In this study, a new interleaved zero-current transition pulse-width modulation (PWM) boost converter, which usesonly one auxiliary switch to provide soft-switching condition is presented and analysed. In order to reduce switching lossesand to obtain high efficiency, a non-dissipative soft-switching cell is used. In the proposed interleaved converter, softswitching is obtained for all semiconductor devices. The main and auxiliary switches turn on and off under zero-currentcondition. Thus, the reverse-recovery losses of boost diodes are reduced and also, high efficiency is achieved owing toreduction of switching losses. Also, implementation of control circuit is simple since the proposed circuit is controlled byPWM method. Operating principles, theoretical analysis, the design procedure along with a design example are described andverified experimentally. Experimental results are presented to justify the validity of theoretical analysis.

1 Introduction

Current fed DC–DC converters are widely employed inindustrial applications. Nowadays, more and morerenewable energy sources are applied, but, most of thesesources, such as fuel cells and solar cells provide low andunregulated output voltage [1–4]. Therefore for renewablepower sources, high efficiency and high step-up DC–DCconverters are necessary as an interface circuit. Thisinterface circuit should absorb power from a low-voltagehigh-current source and provide a high DC voltage for loadwhich is usually an inverter. Thus, the voltage should beboosted and regulated by using current fed converters as theinterface circuit. When power rating increases, it is neededto connect converters in parallel to provide the outputpower. The interleaved structure is used in high-current andhigh-power applications because of its advantages such aspower distribution and reduction of input current ripple aswell as reduction of passive components and the electro-magnetic interference (EMI) filter size [5–7]. Whenisolation is not necessary, boost converter is applied for theinterface circuit because of its simple structure. Also, theboost converter is widely applied in single-phase powerfactor correction circuits [8], because of its continuous inputcurrent. In modern DC–DC converters, in order to reducesize and weight, switching frequency is increased [9].However, high switching frequency will result in highswitching losses and increased EMI. Therefore at highswitching frequency, soft switching techniques such aszero-voltage transition (ZVT) and zero-current transition(ZCT) are applied to reduce switching losses and increaseefficiency. These techniques provide soft switchingcondition while the control circuit remains PWM. Thereforeswitching losses and EMI are reduced. By operating under

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soft switching condition, DC–DC converters can be appliedat higher switching frequency to further reduce theconverter size and weight [10–18]. ZVT interleavedconverters are proper techniques when MOSFET switchesare used to reduce capacitive turn on losses as well asswitching losses [19–21]. For higher power applicationswhere isolated-gate bipolar transistor switches are usedowing to their lower conduction losses and cost, ZCTtechniques are preferred to eliminate tailing current losses.Several interleaved ZCT PWM converters are introduced in[22–26]. In [22], two auxiliary switches are used toprovide soft switching conditions. The current peak ofsemiconductor devices in the converter introduced in [23] ishigh although interleaved technique is used. In addition, di/dt is higher than the proposed interleaved boost converter,which results in higher EMI. In [24, 25], the main switchesare turned on under the ZCT condition, but are turned offunder the hard-switching condition. In this paper, a newinterleaved ZCT PWM converter is introduced, which usesonly one auxiliary switch. Furthermore, in this converter thecurrent stresses of the main switches are low. Fig. 1 showsproposed interleaved ZCT boost converter. The mainconverter is composed of D1, D2, S1 and S2. The auxiliarycircuit is composed of Sa, Lr, Cr, LS1, LS2, Dp1 and Dp2.The intrinsic anti-parallel diodes of main switches are DS1

and DS2. The output capacitance and load resistance are Co

and Ro, respectively. The proposed converter operates like aconventional interleaved boost converter except duringswitching instances. Lr and Cr are resonant components,while Sa controls the resonant instant. LS1 and LS2 aresnubber inductors of main switches. Auxiliary switch Sa isa unidirectional switch, whereas main switches arebidirectional switches. Complexity of a soft switchingconverter is determined by additional switches used because

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Fig. 1 Proposed interleaved ZCS boost converter

each additional switch requires an additional gate drive signalwhich would increase the complexity of control circuit as wellas the power stage. The proposed converter uses only oneadditional switch to provide soft switching condition for themain switches. Therefore this circuit has less complexity incomparison with the mentioned converters in the references.Also, it is important to notice that since the auxiliary circuitelements are not in the main power path, the current ratingof auxiliary circuit elements is low.

2 Proposed ZCT PWM interleaved boostconverters

In order to simplify the converter analysis, followingassumptions are considered:

1. Output capacitor is large enough so that it can be replacedby a DC-voltage source.2. Inductances L1 and L2 are equal (L1 ¼ L2).3. All semiconductor devices are ideal.

To simplify the analysis, L1, L2 and Co are replaced bycurrent and voltage sources, respectively, as shown in Fig. 2.

It is important to notice that sources such as fuel cells,batteries and solar panels have low-output voltage level ofabout 48 V. Hence an efficient high step-up converter suchas proposed interleaved boost converter is useful as theinterface circuit. The converter operation consists of twosymmetrical half cycles during each switching period.Therefore only half of a switching cycle is explained. Inaddition, it is assumed that converter operates at steady state.

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Converter operation in half of the switching cycle can bedivided into nine modes. The equivalent circuit for eachoperating mode and theoretical waveforms are illustrated inFigs. 3 and 4, respectively. The photograph of the originalset-up is shown in the Fig. 5. Before the first mode it isassumed that main switch S1 and auxiliary switch Sa are offand main switch S2 is conducting L2 current. Also, D1 isconducting and Cr is charged to Vo.

2.1 Mode 1: [t0 2 t1] (Fig. 2a)

This mode begins by turning S1 on. Owing to L1, main switchS1 is turned on under zero-current switching (ZCS) condition.Therefore the current flowing through S1 increases linearly toL1 current (Iin) and LS1 current decreases linearly from Iin tozero. At the end of this mode, S1 current and LS1 currentare Iin and zero, respectively. Duration of this mode is

t1 − t0 = LS1Iin

V0

(1)

where Vo is the output voltage and Iin is the current of L1 andL2 in the proposed converter.

2.2 Mode 2: [t1 2 t2] (Fig. 2b)

At t1, current of resonant inductance Ls1 becomes zero. In thismode S1 and S2 are on and L1 and L2 are being charged.

Fig. 2 Equivalent circuit of interleaved ZCS boost converter

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Fig. 3 Equivalent circuit of each operating mode

a Mode 1b Mode 2c Mode 3d Mode 4e Mode 5f Mode 6g Mode 7h Mode 8i Mode 9

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Fig. 4 Theoretical waveforms of the proposed interleaved converter

2.3 Mode 3: [t2 2 t3] (Fig. 2c)

This mode begins by turning Sa on to provide soft-switchingfor S2 turn off. By turning Sa on, a resonant starts between Lr

and Cr. Therefore auxiliary switch Sa turns on under ZCScondition. This mode ends when the Cr voltage reacheszero. Duration of this mode is

t3 − t2 = Tr

2(2)

where Tr is the resonance period of Lr and Cr. The voltage on

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Cr and the current through the auxiliary switch are obtained as

VCr(t) = Vo cos(v1(t − t2)) (3)

ISa(t) = Vo

Z1

sin(v1(t − t2)) (4)

where v1 = 1/�����LrCr

√, Z1 =

�������Lr/Cr

√and Tr = 2p

�����LrCr

√.

In the equation, v1 and Z1 are the resonant frequency andresonant impedance, respectively.

Fig. 5 Proposed converter with experimental values

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2.4 Mode 4: [t3 2 t4] (Fig. 2d)

At t2, diodes Dp1 and Dp2 begin to conduct and Cr isdischarged resonating with Lr, LS1 and LS2. Therefore thecurrents through main and auxiliary switches are reduced.This mode ends when the current through main switchesreaches zero.

IS1(t) = IS2(t) = Iin −Leq

LS1

Vo

Z1

[1 − cos(veq(t − t3))] (5)

ISa(t) = Vo

Z1

−Leq

Lr

Vo

Z1

[1 − cos(veq(t − t3))] (6)

VCr(t) = − Vo���������������1 + (2Lr/LS1)

√ sin(veq(t − t3)) (7)

where veq and Leq are the resonant frequency and equalinductance in this mode, respectively, and are obtainedfrom the following equations

veq = 1/������LeqCr

√and Leq = Lr|LS1|LS2

As the Dp1 and Dp2 are the conducting, the voltage on D1 andD2 increase as VCr decreases.

VD1(t) = VD2(t)

= Vo +Vo���������������

1 + (2Lr/LS1)√ sin(veq(t − t3)) (8)

2.5 Mode 5: [t4 2 t5] (Fig. 2e)

At t4, the currents through main switches S1 and S2 reach zero.Thus anti-parallel diodes DS1 and DS2 begin to conduct. Thismode ends when the current through auxiliary switch Sa

reaches zero at t5. VCr, IS1, IS2, VD1, VD2 and ISa can becalculated using (5)–(8).

2.6 Mode 6: [t5 2 t6] (Fig. 2f)

At t5, the current of auxiliary switch reaches zero. Thus,auxiliary switch Sa turns off under ZCS condition. Sum ofDp1 and Dp2 currents run through Cr and thus, the voltageacross Cr increases. At the end of this mode anti-paralleldiodes DS1 and DS2 turn off. During this mode S2 is turnedoff under ZCS condition.

2.7 Mode 7: [t6 2 t7] (Fig. 2g)

At t6, the anti-parallel diodes DS1 and DS2 turn off. In thismode, the current through LS2 and Dp2 is constant andequal to Iin. Also, the resonance between LS1 and Cr

continues and the current through LS1 and Dp1 decreasesand thus, the current through main switch S1 increases. Atthe end of this mode the current through LS1 and Dp1

reaches zero and the current of S1 increases to Iin.

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2.8 Mode 8: [t7 2 t8] (Fig. 2h)

In this mode, Cr is charged by the constant current Iin throughLS2 and Dp2. This mode ends when Cr voltage reaches Vo.

VCr(t) = VCr(t7) + Iin

Cr

(t − t7) (9)

2.9 Mode 9: [t8 2 t9] (Fig. 2i)

At t8, the voltage on Cr is Vo. Thus D2 turns on under zerovoltage switching (ZVS) condition and Dp2 turns off underZVS condition. Since the voltage on Cr is clamped at Vo,the voltage on Dp2 and its current remain zero. In this modethe proposed converter behaves like a regular interleavedPWM boost converter.

3 Design procedure

This section presents design procedure for the proposedconverter.

The converter specifications for 250 W converter are

† Output power Po ¼ 250 W;† Output voltage Vo ¼ 200 V;† Input voltage Vin ¼ 48 V;† Switching frequency of the main switches fsm ¼ 100 kHz;† Switching frequency of the auxiliary switchfSa ¼ 200 kHz.

The converter specifications for 50 W converter are

† Output power Po ¼ 50 W;† Output voltage Vo ¼ 200 V;† Input voltage Vin ¼ 48 V;† Switching frequency of the main switches fsm ¼ 100 kHz;† Switching frequency of the auxiliary switchfSa ¼ 200 kHz.

The design procedure of this converter is explained in foursteps as following.

3.1 Resonant elements (Cr, Lr, LS1 and LS2)

In order to obtain soft switching condition for both mainswitches, the maximum current through each snubberinductor should be greater than Iin in the fifth mode. In thiscondition, the current through the main switches will benegative and the main switches body diodes will conduct.Considering 20% over design, the following relation isobtained

Leq

Ls

Vo

Z1

= 1.2Iin (10)

where

Iin = Po

2Vin

(11)

Iin = Po

2Vin

⇒ ILr =Vo

Zr

= 2.4Iin ⇒ Zr =Vo

2.4Iin

(12)

where Po is the output power. Also, the resonant periodshould be negligible in comparison with the switching

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Fig. 6 Voltage (top waveform) and current (bottom waveform) of main switch

Voltage scale is 100 V/div, current scale is 3 A/div and time scale is 2.5 ms/div

Fig. 7 Voltage (top waveform) and current (bottom waveform) of the auxiliary switch

Voltage scale is 100 V/div, current scale is 3 A/div and time scale is 1 ms/div

Fig. 8 Voltage of resonant capacitor Cr.

Voltage scale is 100 V/div and time scale is 0.5 ms/div

period. Thus, the resonant frequency is selected at least tentimes greater than the switching frequency.

Tres = 2p�����CrLr

ó Tsw

10(13)

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where Tres and Tsw are the resonance and switching periods,respectively.

By using (12) and (13), Tres, Lr and Cr can be obtained.Before turning the main switches off, the auxiliary circuitshould operate to reduce the current through the mainswitches to zero. Therefore converter minimum duty cycle is

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Fig. 9 Voltage (top waveform) and current (bottom waveform) of main switch

Voltage scale is 80 V/div, current scale is 0.5 A/div and time scale is 1 ms/div

Fig. 10 Voltage (top waveform) and current (bottom waveform) of the auxiliary switch

Voltage scale is 80 V/div, current scale is 0.5 A/div and time scale is 1 ms/div

Fig. 11 Efficiency versus output power of the proposed interleaved boost converter and its hard switching counterpart

Dmin = t5 − t3Tsw

= p− sin−1((2Zr/Vo)Iin)

vrTsw

(14)

where LS1 and LS2 are the snubber inductors of main switchesand their value can be calculated like any snubber inductor.By calculating Ls value and using (10)–(13), Tres, Lr and Cr

can be obtained.

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3.2 Selection of S1, S2 and Sa

The peak current and voltage stresses of switches are obtainedfrom the following equations

VS1,2 = VSa = Vo max (15)

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Isw1,2 = Po

2Vin

+ DIL

2(16)

ISa =Vo

Z1

(17)

where DIL is the current ripple of each input inductor.

3.3 Selection of D1, D2 and Do

The current peak and voltage stresses of the diodes areobtained from the following equations

VD1,2 max = 2Vo max (18)

Fig. 12 Photograph of the original setup

Table 1 Power losses of each semiconductor device

D1 or D2

losses

Dp1 or

Dp2

losses

Auxiliary

switch

losses

Each main

switch

losses

Output

power

1.2 W 0.3 W 1.5 W 1.8 W 150 W proposed

converter1.3 W 0.4 W 1.6 W 2.1 W 250 W

2 W 4.2 W 150 W hard

switching

converter

2.8 W 5.4 W 250 W

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VDp1,Dp2 max = Vo max (19)

ID1,2 max = Po

2Vin

+ DIL

2(20)

ID1,D2 max = Po

Vin

+ DIL (21)

3.4 Selection of L1, L2 and Co

The value of inductances L1 and L2 and capacitance value ofCo can be obtained exactly like a conventional PWMconverter [27].

4 Experimental results

The schematic of the prototype converter is shown in Fig. 6and the experimental results of the proposed convertertopology are shown in Fig. 7. Also the photograph of theoriginal set-up is shown in Fig. 5 that shows the main andcontrol circuit prototypes. The proposed ZCT interleavedboost converter is implemented for input voltage ofVin ¼ 48 VDC and output voltage of Vo ¼ 200 VDC

operating at fsw ¼ 100 kHz. In the implemented prototype,IRGBC20U is used as main and auxiliary switches.MUR860 diodes are used as D1 and D2 and MUR460diodes are used as Dp1 and Dp2. A 10 nF and a 100 mFcapacitors are used as Cr and Co, respectively. Inductorsvalues for L1 and L2 are 300 mH, and Lr is 8 mH. Inductorsvalues for LS1 and LS2 are 16 mH. Figs. 7 and 8 show thecurrent and voltage waveform of the main and auxiliaryswitches, respectively, for 250 W converter. The resonantcapacitor voltage is presented in Fig. 9. Also, Figs. 10 and11 show the current and voltage waveform of the main andauxiliary switches, respectively, for 50 W converter. It canbe observed that the main switch is turned on under ZCScondition for both converters. Also for both converters, themain switch current is reduced to zero just before turningthis switch off. In addition, ZCS is achieved for theauxiliary switch at turn on and turn off instants. Fig. 12shows the efficiency against output power for the proposedinterleaved boost converter and its hard-switchingcounterpart. The losses of each semiconductor device in theproposed converter and hard-switching converter arecompared in Table 1. Table 1 shows detail comparisonbetween the simulation results of the proposed converterand the traditional hard-switched counterpart. The hard-

Fig. 13 Schematic of control circuit of the proposed interleaved boost converter

Tl494 IC is applied for PWM controller. Also, 74123 IC is used as monostable. The delay circuit is implemented using RC circuits. Also, ICL7667 is applied asgate driver

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switching converter is similar to the proposed converter and isobtained by eliminating the auxiliary circuit. For practicalimplementation, RCD snubber circuit is applied for thehard-switching converter. According to Table 1, asexpected, owing to reduced reverse-recovery losses of theboost diodes and switching losses, the proposed converterhas higher efficiency than the conventional PWM hard-switching converter.

The schematic of the control circuit for the proposedconverter is shown in Fig. 13.

5 Conclusion

In this paper, a new interleaved ZCT PWM boost converter isintroduced. This converter uses only one auxiliary switch toprovide soft-switching condition for the main and auxiliaryswitches. The main and auxiliary switches turn on and offunder zero-current switching condition. This converter hashigher efficiency than the conventional PWM hard-switching converter because of the reduced reverse-recoverylosses of boost diodes and switching losses. Also, theproposed converter is controlled by PWM method.According to the experimental results, the efficiency isimproved by about 2.9%. This converter is analysed and thedesign procedure is presented. The presented experimentalresults verify the theoretical analysis.

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