ISSCC 2016 SILICON SYSTEMS FOR THE INTERNET OF...
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Tutorials (Sunday, January 31 st ) Understanding Phase Noise in LC VCOs Carlo Samori, Politecnico di Milano, Milano, Italy Basics of Memory Tiers in Compute Systems Rob Sprinkle, Google, Mountain View, CA High Voltage Power Devices, Converter Topologies and Applications Yogesh Ramadass, Texas Instruments, San Jose, CA System-Level Power Management Techniques David Flynn, Arm, Cambridge, United Kingdom Basics of SAR ADCs: Circuits and Architectures Pieter Harpe, Eindhoven University of Technology, Eindhoven, The Netherlands Optical Interconnects: Design and Analysis Azita Emami, California Institute of Technology, Pasadena, CA Asynchronous Circuit Design and Methodology for Low-Power IoE Edith Beigne, CEA-LETI, Grenoble, France Noise Simulation in Mixed-Signal SoCs Makoto Nagata, Kobe University, Kobe, Japan Circuit Design for Low-Power Wireless Applications Alyosha Molnar, Cornell University, Ithaca, NY Circuit Design Considerations for Implantable Devices Peng Cong, Google, Mountain View, CA Forums (January 31 st & February 4 th ) Sunday January 31 st Designing Secure Systems: Manufacturing, Circuits, and Architectures Data Converter Calibration & Dynamic Matching Techniques: From Amplifiers to Transceivers Thursday February 4 th Radio Architectures and Circuits Towards 5G Emerging Short-Reach and High-Density Interconnect Solutions for Internet of Everything Advanced IC Design for Ultra Low-Noise Sensing Circuit, Systems and Data Processing for Next Generation Wearable and Implantable Medical Devices Student Activities (Sunday, January 31 st ) Student Research Preview (SRP): Short Presentations w/ Poster Session Silkroad Award: Scholarships awarded for Far-East full-time students ISSCC 2016 SILICON SYSTEMS FOR THE INTERNET OF EVERYTHING January 31 - February 4, 2016 | San Francisco Marriott Marquis | San Francisco, California, USA Paper Submission Deadline September 14, 2015 Special Evening Topic (Sunday, January 31 st ) Computing Architectures Paving the Path to Power Efficiency The Von Neumann computer architecture, which will celebrate its 70 th anniversary in 2016, has seen a performance improvement of 10 12 times (relative to the ENIAC). This progress was enabled by hardware efficiency improvements of a similar magnitude. However, as the benefits of CMOS feature size scaling (Moore and Dennard) are coming to an end, there is an emerging need to re-architect computing systems from the ground up. Will quantum and neuro-inspired computers outperform conventional Von Neumann architectures? Will heterogeneous system architectures become mainstream? In this evening session, a group of experts will share their views on architectural innovations that will shape the future of computing. Evening Panels (February 1 st - 2 nd ) Class of 2025 – Where Will be the Best Jobs? For the past several decades, the camps of analog and digital engineers have been debating the year by which their opponents’ discipline will become obsolete. What is a new (and potentially confused) student to make of this controversy? Will it be worth pursuing the whimsical art of analog electronics, or is it better to focus entirely on digital systems and software? Come to this event to benefit from the advice and perspectives of top educators and industry experts. Do We Need to Downscale our Radios Below 20nm? Downscaling below 20nm is expensive and appears to bring little to no performance benefit for radios. Is there still a reason to further downscale our radios? Does the co-integration of the digital blocks still provide a strong enough incentive? Will future technologies deliver devices with significantly improved high-frequency performance? A panel of system designers, radio architects and technology developers will share their views on this subject. Survey Says! Much like in the US game show Family Feud, this event features two teams (assisted by the audience) that will compete to name the most popular responses to survey questions. What is the first thing you do after you tape-out? What excuse to make to get more time to tape-out? What is the most common cause of data converter design failure? What would you do first if you made $10M from your start-up? Join us for this fun race to the push button. Eureka! The Best Moments of Solid-State Circuit Design in the 2000s Eureka moments are exciting, but do the resulting ideas also work out as hoped for? Do they have a broader impact on the field? Well-known experts from various areas of IC design will share their ups and downs related to recent innovations and provide a historical perspective. January 31 - February 4, 2016 www.isscc.org Moore’s Law: A Path Forward William Holt Executive Vice President Intel Corporation, United States 5G Mobile Technology Evolution Toward 2020 and Beyond Seizo Onoe Chief Technology Officer, Executive Vice President, Member of Board of Directors, and Managing Director of R & D Innovation Division, NTT DOCOMO, Japan Three Pillars Enabling the Internet of Everything: Smart Ordinary Objects, Information-Centric Networks, and Real-Time Insights Sophie Vandebroek Chief Technology Officer and the President of the Xerox Innovation Group, United States Plenary Talks (Monday, February 1 st ) Demonstration Sessions (February 1 st -2 nd ) Technical Sessions (February 1 st - 3 rd ) Short Course (February 4 th ) Circuits for the Internet of Everything (IoE) Processors for IoE Shichin Ouyang, MediaTek USA, San Jose, CA Radios for IoE Hooman Darabi, Broadcom Corporation, Irvine, CA Sensor Interfaces for IoE Nick Van Helleputte, imec, Heverlee, Belgium Frequency References for IoE Fabio Sebastiano, Delft University of Technology, The Netherlands The Road Ahead for Securely Connected Cars Lars Reger CTO Automotive, NXP Semiconductors N.V., The Netherlands
Transcript of ISSCC 2016 SILICON SYSTEMS FOR THE INTERNET OF...
Tutorials (Sunday, January 31st)Understanding Phase Noise in LC VCOs
Carlo Samori, Politecnico di Milano, Milano, ItalyBasics of Memory Tiers in Compute Systems
Rob Sprinkle, Google, Mountain View, CAHigh Voltage Power Devices, Converter
Topologies and ApplicationsYogesh Ramadass, Texas Instruments, San Jose, CASystem-Level Power Management Techniques
David Flynn, Arm, Cambridge, United KingdomBasics of SAR ADCs: Circuits and Architectures
Pieter Harpe, Eindhoven University of Technology, Eindhoven, The NetherlandsOptical Interconnects: Design and Analysis
Azita Emami, California Institute of Technology, Pasadena, CAAsynchronous Circuit Design and Methodology for Low-Power IoE
Edith Beigne, CEA-LETI, Grenoble, FranceNoise Simulation in Mixed-Signal SoCsMakoto Nagata, Kobe University, Kobe, Japan
Circuit Design for Low-Power Wireless ApplicationsAlyosha Molnar, Cornell University, Ithaca, NY
Circuit Design Considerations for Implantable DevicesPeng Cong, Google, Mountain View, CA
Forums (January 31st & February 4th)Sunday January 31st
Designing Secure Systems: Manufacturing, Circuits, and ArchitecturesData Converter Calibration & Dynamic Matching Techniques:
From Amplifiers to Transceivers
Thursday February 4th
Radio Architectures and Circuits Towards 5GEmerging Short-Reach and High-Density Interconnect
Solutions for Internet of EverythingAdvanced IC Design for Ultra Low-Noise Sensing
Circuit, Systems and Data Processing for Next Generation Wearable and Implantable Medical Devices
Student Activities (Sunday, January 31st)Student Research Preview (SRP): Short Presentations w/ Poster Session
Silkroad Award: Scholarships awarded for Far-East full-time students
ISSCC 2016SILICON SYSTEMS FOR THE INTERNET OF EVERYTHINGJanuary 31 - February 4, 2016 | San Francisco Marriott Marquis | San Francisco, California, USA
Paper Submission DeadlineSeptember 14, 2015
Special Evening Topic (Sunday, January 31st)Computing Architectures Paving the Path to Power Efficiency
The Von Neumann computer architecture, which will celebrate its 70th anniversary in 2016, hasseen a performance improvement of 1012 times (relative to the ENIAC). This progress was enabled by hardware efficiency improvements of a similar magnitude. However, as the benefitsof CMOS feature size scaling (Moore and Dennard) are coming to an end, there is an emergingneed to re-architect computing systems from the ground up. Will quantum and neuro-inspiredcomputers outperform conventional Von Neumann architectures? Will heterogeneous systemarchitectures become mainstream? In this evening session, a group of experts will share theirviews on architectural innovations that will shape the future of computing.
Evening Panels (February 1st - 2nd)Class of 2025 – Where Will be the Best Jobs?
For the past several decades, the camps of analog and digital engineers have been debating the year bywhich their opponents’ discipline will become obsolete. What is a new (and potentially confused) studentto make of this controversy? Will it be worth pursuing the whimsical art of analog electronics, or is itbetter to focus entirely on digital systems and software? Come to this event to benefit from the adviceand perspectives of top educators and industry experts.
Do We Need to Downscale our Radios Below 20nm?Downscaling below 20nm is expensive and appears to bring little to no performance benefitfor radios. Is there still a reason to further downscale our radios? Does the co-integration ofthe digital blocks still provide a strong enough incentive? Will future technologies deliver devices with significantly improved high-frequency performance? A panel of system designers,radio architects and technology developers will share their views on this subject.
Survey Says!Much like in the US game show Family Feud, this event features two teams (assisted by theaudience) that will compete to name the most popular responses to survey questions. What isthe first thing you do after you tape-out? What excuse to make to get more time to tape-out?What is the most common cause of data converter design failure? What would you do first ifyou made $10M from your start-up? Join us for this fun race to the push button.
Eureka!The Best Moments of Solid-State Circuit Design in the 2000s
Eureka moments are exciting, but do the resulting ideas also work out as hoped for? Do theyhave a broader impact on the field? Well-known experts from various areas of IC design willshare their ups and downs related to recent innovations and provide a historical perspective.
January 31 - February 4, 2016
www.isscc.org
Moore’s Law:
A Path Forward
William HoltExecutive Vice President Intel Corporation,
United States
5G Mobile Technology Evolution
Toward 2020 and Beyond
Seizo OnoeChief Technology Officer, Executive Vice President,
Member of Board of Directors, and Managing Director of R & D Innovation Division, NTT DOCOMO, Japan
Three Pillars Enabling the Internet ofEverything: Smart Ordinary Objects,
Information-Centric Networks, and Real-Time Insights
Sophie VandebroekChief Technology Officer and the President of
the Xerox Innovation Group, United States
Plenary Talks (Monday, February 1st)
Demonstration Sessions (February 1st -2nd)
Technical Sessions (February 1st - 3rd)
Short Course (February 4th)
Circuits for the Internet of Everything (IoE)Processors for IoE
Shichin Ouyang, MediaTek USA, San Jose, CARadios for IoE
Hooman Darabi, Broadcom Corporation, Irvine, CA
Sensor Interfaces for IoENick Van Helleputte, imec, Heverlee, Belgium
Frequency References for IoEFabio Sebastiano, Delft University of Technology, The Netherlands
The Road Ahead for Securely
Connected Cars
Lars RegerCTO Automotive,
NXP Semiconductors N.V., The Netherlands
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