ISSCC 2007 / SESSION 28 / IMAGE SENSORS / 28 - Harvest … · ISSCC 2007 / SESSION 28 / IMAGE...
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506 • 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 28 / IMAGE SENSORS / 28.4 28.4 A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC M.F. Snoeij 1 , P. Donegan 2 , A.J.P. Theuwissen 1,3 , K.A.A. Makinwa 1 , J.H. Huijsing 1 1 Delft University of Technology, Delft, The Netherlands 2 DALSA, Waterloo, Canada 3 DALSA Semiconductors, Eindhoven, The Netherlands This paper presents a CMOS image sensor that uses a column- level ADC with a new multiple-ramp single-slope (MRSS) archi- tecture. At similar power consumption, this architecture achieves a 3.3× reduction in A/D conversion time compared with the clas- sical single-slope architecture. Like the single-slope ADC, the MRSS ADC requires only a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype has been realized in a 0.25μm CMOS process. Measurements show that compared to an imager with a single-slope ADC, the MRSS ADC enables a frame rate increase of 2.8× while dissipat- ing only 24% more power. In recent years, column-level ADCs have become quite common in CMOS image sensors [1, 2] because a large number of parallel ADC channels are used, which facilitates the high speed readout of large pixel arrays. Column-level ADCs usually employ a single- slope architecture, which has the advantage of requiring only one comparator per column. Such simple column circuitry reduces the required chip area and makes it relatively easy to ensure unifor- mity between column circuits. However, a disadvantage of the single-slope architecture is the fact that its conversion time increases exponentially with the number of bits, which limits read-out speed at high resolutions [2]. While successive approxi- mation or algorithmic ADCs are much faster, these all require much more in-column circuitry, which increases chip area, layout complexity and column non-uniformity. The MRSS ADC achieves a significantly lower conversion time while preserving the key benefit of the single-slope ADC, its sim- ple column circuitry. Figure 28.4.1 shows the block and timing diagrams of an MRSS ADC. The column circuitry consists of a single comparator that can be connected to several ramp volt- ages, labeled 1 through m. An A/D conversion is divided into a coarse and a fine conversion phase. During the coarse phase, all comparators are connected to the first ramp, and a single-slope conversion of m=2 p clock periods is performed, which provides a coarse (p-bit) approximation of the input signal. In the fine A/D conversion phase, all m ramps are operated concurrently for 2 q clock periods, with each ramp spanning 1/m times the range of the coarse ramp. Based on the results of the coarse phase, each comparator is connected to the appropriate ramp. The number of clock periods required for a complete conversion is therefore 2 p + 2 q , where p + q is the ADC’s resolution. The choice of p and q involves a design trade-off between power (dissipated in the ramp generators) and speed. In this design, 8 ramps were selected, resulting in p = 3 and q = 7 for 10b resolution. To prevent the cre- ation of dead-bands, the implemented ramp voltages overlap each other somewhat. Figure 28.4.2 shows the implemented column-level ADC circuit. The comparator is similar to that presented in [1, 2] and is re- used from an existing design. It is auto-zeroed using capacitor C1 and switch S2. During the auto-zero phase, the output of the col- umn-level CDS amplifier is also sampled on C1. Next, the com- parator is connected to one of the ramp voltages via S3. During the coarse ADC phase, ramp1 outputs a coarse ramp that is input into each comparator by using the control line force_ramp1. The result of the coarse A/D conversion is stored in 3 bits of the col- umn memory, and is subsequently fed into a 3-to-8 decoder that connects the comparator to the correct ramp. After this, the fine A/D conversion phase is performed, the results of which are stored in the other 8 bits of the column memory. In Fig. 28.4.3, a block diagram of the ramp generator is shown. The ramps are generated by 8 12b resistor-ladder DACs [3]. For correct operation of the MRSS architecture, it is imperative that the slopes of the ramps match well and that their offsets are well- defined. This is achieved by using a single coarse resistor ladder, to which 8 fine resistor ladders are connected to generate the ramp voltages. With a proper choice of resistor values, it is not necessary to use buffer amplifiers between the coarse and fine ladders. To compensate for the switch resistance, the fine ladder uses NMOS transistors (T 2 through T 31 ) as resistors that are matched to the force switches T 1 and T 32 between the coarse and fine ladders. A separate set of sense switches is used to directly output the voltage at the coarse resistor nodes. The DAC outputs are buffered by folded-cascode opamps, which drive the column circuitry. Their offset variations are compensated by a digital auto-calibration algorithm involving a test-column, whose com- parator is connected to ramp1. While the pixel voltages are out- put to the front-end CDS amplifiers, ramp1 feeds in test voltages corresponding to the middle of one of the other ramps to the test comparator, which subsequently performs the same A/D conver- sion as the other columns. The digital output of the test column contains the offset of one of the ramps compared to ramp1. This is averaged and subsequently cancelled in the digital domain, simply by changing the code assigned to the initial voltage of each ramp. A prototype image sensor was realized in a 0.25μm CMOS process (Fig. 28.4.7). The pixel array has 400×330 3T pixels, with a pixel pitch of 7.4μm. The supply voltage is 2.5V for the analog and digital circuits and 3.3V for the I/O and analog switches. For flexibility, the digital circuitry that controls the column circuitry and ramp generator is implemented off-chip in an FPGA. This enables the ADC to operate in both the single-slope and MRSS modes, allowing for comparisons between the two architectures. The ADC’s performance can be separately evaluated using a test input that feeds a common input signal to all columns. Figure 28.4.4 shows a measurement of the averaged INL at a clock fre- quency of 1MHz, both before and after the auto-calibration of the ramp generators is switched on. It clearly demonstrates the effec- tiveness of the auto-calibration scheme. Figure 28.4.5 shows a measured image at 50fps with the column ADC in 10b single- slope mode. At a clock frequency of 20MHz, the line time is 58μs, of which 53μs is used for the A/D conversion. Figure 28.4.6 shows a measured image at 142fps with the column ADC in 10b MRSS mode. The A/D conversion is now performed in 16μs, reducing the line time to 21μs. The power consumption of the analog circuit is 38mW, of which 30mW is used by the column CDS amplifiers and comparators and 8mW by the ramp generator. In conclusion, a CMOS image sensor with a multiple-ramp sin- gle-slope ADC is presented. Compared to a single-slope ADC, it achieves a 3.3× decrease in conversion time, with a power increase of about 24%, and thus shows the potential of this new ADC architecture to increase power efficiency, speed, and chip area of column-level ADCs. Acknowledgements: The authors would like to thank Matthias Sonder, Binqiao Li, Martin Kiik, Feng-Hua Feng, and Shujuan Xie of DALSA Corporation for their contri- butions to the prototype. References: [1] T. Sugiki et al. , “A 60mW 10b CMOS Image Sensor with Column-to- Column FPN Reduction,” ISSCC Dig. Tech. Papers, pp. 108-109, Feb., 2000. [2] Y. Nitta et al., “High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor,” ISSCC Dig. Tech. Papers, pp. 500-501, Feb., 2006. [3] P. Holloway, “ATrimless 16b Digital Potentiometer,” ISSCC Dig. Tech. Papers, pp. 66-67, Feb., 1984. 1-4244-0852-0/07/$25.00 ©2007 IEEE.
Transcript of ISSCC 2007 / SESSION 28 / IMAGE SENSORS / 28 - Harvest … · ISSCC 2007 / SESSION 28 / IMAGE...
506 • 2007 IEEE International Solid-State Circuits Conference
ISSCC 2007 / SESSION 28 / IMAGE SENSORS / 28.4
28.4 A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC
M.F. Snoeij1, P. Donegan2, A.J.P. Theuwissen1,3, K.A.A. Makinwa1, J.H. Huijsing1
1Delft University of Technology, Delft, The Netherlands2DALSA, Waterloo, Canada3DALSA Semiconductors, Eindhoven, The Netherlands
This paper presents a CMOS image sensor that uses a column-level ADC with a new multiple-ramp single-slope (MRSS) archi-tecture. At similar power consumption, this architecture achievesa 3.3× reduction in A/D conversion time compared with the clas-sical single-slope architecture. Like the single-slope ADC, theMRSS ADC requires only a single comparator per column, and,additionally, 8 switches and some digital circuitry. A prototypehas been realized in a 0.25µm CMOS process. Measurementsshow that compared to an imager with a single-slope ADC, theMRSS ADC enables a frame rate increase of 2.8× while dissipat-ing only 24% more power.
In recent years, column-level ADCs have become quite common inCMOS image sensors [1, 2] because a large number of parallelADC channels are used, which facilitates the high speed readoutof large pixel arrays. Column-level ADCs usually employ a single-slope architecture, which has the advantage of requiring only onecomparator per column. Such simple column circuitry reduces therequired chip area and makes it relatively easy to ensure unifor-mity between column circuits. However, a disadvantage of thesingle-slope architecture is the fact that its conversion timeincreases exponentially with the number of bits, which limitsread-out speed at high resolutions [2]. While successive approxi-mation or algorithmic ADCs are much faster, these all requiremuch more in-column circuitry, which increases chip area, layoutcomplexity and column non-uniformity.
The MRSS ADC achieves a significantly lower conversion timewhile preserving the key benefit of the single-slope ADC, its sim-ple column circuitry. Figure 28.4.1 shows the block and timingdiagrams of an MRSS ADC. The column circuitry consists of asingle comparator that can be connected to several ramp volt-ages, labeled 1 through m. An A/D conversion is divided into acoarse and a fine conversion phase. During the coarse phase, allcomparators are connected to the first ramp, and a single-slopeconversion of m=2p clock periods is performed, which provides acoarse (p-bit) approximation of the input signal. In the fine A/Dconversion phase, all m ramps are operated concurrently for 2q
clock periods, with each ramp spanning 1/m times the range ofthe coarse ramp. Based on the results of the coarse phase, eachcomparator is connected to the appropriate ramp. The number ofclock periods required for a complete conversion is therefore 2p +2q, where p + q is the ADC’s resolution. The choice of p and qinvolves a design trade-off between power (dissipated in the rampgenerators) and speed. In this design, 8 ramps were selected,resulting in p = 3 and q = 7 for 10b resolution. To prevent the cre-ation of dead-bands, the implemented ramp voltages overlap eachother somewhat.
Figure 28.4.2 shows the implemented column-level ADC circuit.The comparator is similar to that presented in [1, 2] and is re-used from an existing design. It is auto-zeroed using capacitor C1and switch S2. During the auto-zero phase, the output of the col-umn-level CDS amplifier is also sampled on C1. Next, the com-parator is connected to one of the ramp voltages via S3. Duringthe coarse ADC phase, ramp1 outputs a coarse ramp that is inputinto each comparator by using the control line force_ramp1. Theresult of the coarse A/D conversion is stored in 3 bits of the col-umn memory, and is subsequently fed into a 3-to-8 decoder thatconnects the comparator to the correct ramp. After this, the fine
A/D conversion phase is performed, the results of which arestored in the other 8 bits of the column memory.
In Fig. 28.4.3, a block diagram of the ramp generator is shown.The ramps are generated by 8 12b resistor-ladder DACs [3]. Forcorrect operation of the MRSS architecture, it is imperative thatthe slopes of the ramps match well and that their offsets are well-defined. This is achieved by using a single coarse resistor ladder,to which 8 fine resistor ladders are connected to generate theramp voltages. With a proper choice of resistor values, it is notnecessary to use buffer amplifiers between the coarse and fineladders. To compensate for the switch resistance, the fine ladderuses NMOS transistors (T2 through T31) as resistors that arematched to the force switches T1 and T32 between the coarse andfine ladders. A separate set of sense switches is used to directlyoutput the voltage at the coarse resistor nodes. The DAC outputsare buffered by folded-cascode opamps, which drive the columncircuitry. Their offset variations are compensated by a digitalauto-calibration algorithm involving a test-column, whose com-parator is connected to ramp1. While the pixel voltages are out-put to the front-end CDS amplifiers, ramp1 feeds in test voltagescorresponding to the middle of one of the other ramps to the testcomparator, which subsequently performs the same A/D conver-sion as the other columns. The digital output of the test columncontains the offset of one of the ramps compared to ramp1. Thisis averaged and subsequently cancelled in the digital domain,simply by changing the code assigned to the initial voltage of eachramp.
A prototype image sensor was realized in a 0.25µm CMOSprocess (Fig. 28.4.7). The pixel array has 400×330 3T pixels, witha pixel pitch of 7.4µm. The supply voltage is 2.5V for the analogand digital circuits and 3.3V for the I/O and analog switches. Forflexibility, the digital circuitry that controls the column circuitryand ramp generator is implemented off-chip in an FPGA. Thisenables the ADC to operate in both the single-slope and MRSSmodes, allowing for comparisons between the two architectures.The ADC’s performance can be separately evaluated using a testinput that feeds a common input signal to all columns. Figure28.4.4 shows a measurement of the averaged INL at a clock fre-quency of 1MHz, both before and after the auto-calibration of theramp generators is switched on. It clearly demonstrates the effec-tiveness of the auto-calibration scheme. Figure 28.4.5 shows ameasured image at 50fps with the column ADC in 10b single-slope mode. At a clock frequency of 20MHz, the line time is 58µs,of which 53µs is used for the A/D conversion. Figure 28.4.6 showsa measured image at 142fps with the column ADC in 10b MRSSmode. The A/D conversion is now performed in 16µs, reducing theline time to 21µs. The power consumption of the analog circuit is38mW, of which 30mW is used by the column CDS amplifiers andcomparators and 8mW by the ramp generator.
In conclusion, a CMOS image sensor with a multiple-ramp sin-gle-slope ADC is presented. Compared to a single-slope ADC, itachieves a 3.3× decrease in conversion time, with a powerincrease of about 24%, and thus shows the potential of this newADC architecture to increase power efficiency, speed, and chiparea of column-level ADCs.
Acknowledgements:The authors would like to thank Matthias Sonder, Binqiao Li, Martin Kiik,Feng-Hua Feng, and Shujuan Xie of DALSA Corporation for their contri-butions to the prototype.
References:[1] T. Sugiki et al. , “A 60mW 10b CMOS Image Sensor with Column-to-Column FPN Reduction,” ISSCC Dig. Tech. Papers, pp. 108-109, Feb.,2000.[2] Y. Nitta et al., “High-Speed Digital Double Sampling with Analog CDSon Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor,”ISSCC Dig. Tech. Papers, pp. 500-501, Feb., 2006.[3] P. Holloway, “A Trimless 16b Digital Potentiometer,” ISSCC Dig. Tech.Papers, pp. 66-67, Feb., 1984.
1-4244-0852-0/07/$25.00 ©2007 IEEE.
507DIGEST OF TECHNICAL PAPERS •
Continued on Page 618
ISSCC 2007 / February 14, 2007 / 3:15 PM
Figure 28.4.1: a) Block diagram of the multiple-ramp single-slope ADC architecture; b) Corresponding timing diagram. Figure 28.4.2: Simplified column-level ADC circuitry.
Figure 28.4.3: Circuit diagram of the multiple-ramp generator.
Figure 28.4.5: Image captured with the column ADC in single-slope mode at 50fps. Figure 28.4.6: Image captured with the column ADC in MRSS mode at 142fps.
Figure 28.4.4: Measured averaged INL at 1MHz. a) without auto-calibration b) with auto-calibration
in1
column 1
multipleramp
generator
t
V
ramp1
ramp2
ramp3
logic &memory
counter &control
in2
column 2
logic &memory
coarsephase
ramp1
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a) b)
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output
S1
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ramp8
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force_ramp1
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extra circuitry compared to single-slope
3x
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Vref_low Vref_high
sense bus
force bus
VDD
DACout
coarse resistor ladder
128 resistors
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T - T = fine resistor ladder
T32
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0 200 400 600 800 1000-3
-2
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INL(LSB)
INL(LSB)
code
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618 • 2007 IEEE International Solid-State Circuits Conference 1-4244-0852-0/07/$25.00 ©2007 IEEE.
ISSCC 2007 PAPER CONTINUATIONS
Figure 28.4.7: Chip micrograph of the prototype image sensor. The die size is 5mm x 5mm.
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