Ip core example
Transcript of Ip core example
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PLD’s and Introduction to theAltera Cyclone II FPGA
Prof. Anish Goel
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Programmable Logic Device Black Box
2 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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General PLA Structure
3 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Gate Level PLA Structure
4 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Customary Schematic of a PLA
5 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Typical PLA Output Circuitry
6 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Structure of a CPLD
7 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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A Section of a CPLD
8 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Structure of an FPGA
9 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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A Two-Input Lookup Table
10 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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A Three-Input Lookup Table
11 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Inclusion of a flip-flop With an LUT
12 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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A Section of a Programmed FPGA
13 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Pass transistor Switches in an FPGA
14 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II General Features Contain a two-dimensional row- and column-based
architecture to implement custom logic Column and row interconnects of varying speeds provide
signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers
The logic array consists of LABs, with 16 logic elements (LEs) in each LABAn LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device
15 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II General Features (continued) Cyclone II devices provide a global clock network and up
to four phase-locked loops (PLLs) Consists of up to 16 global clock lines that drive throughout
the entire device Can provide clocks for all resources within the device, such as
input/output elements (IOEs), LEs, embedded multipliers, and embedded memory blocks
Global clock lines can also be used for other high fan-out signals
Cyclone II PLLs provide general-purpose clocking with clock synthesis and phase shifting as well as external outputs
16 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II General Features (continued) M4K memory blocks are true dual-port memory blocks with
4K bits of memory plus parity (4,608 bits) Provide dedicated true dual-port, simple dual-port, or single-port
memory up to 36-bits wide Arranged in columns across the device in between certain LABs
Each embedded multiplier block Can implement up to either two 9 × 9-bit multipliers, or one 18 ×
18- bit multiplier Embedded multipliers are arranged in columns across the device
Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB rows and columns around the periphery of the device Each IOE contains a bidirectional I/O buffer and three registers for
registering input, output, and output-enable signals
17 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Altera Cyclone II Programmable Device
18 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II EP2C20 Device Block Diagram
19 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II Logic Element (LE) A four-input look-up table (LUT), which is a function generator
that can implement any function of four variables A programmable register A carry chain connection A fast interconnect between adjacent LABs
A register chain connection A fast, registered, connection between adjacent LEs
The ability to drive all types of interconnects: Local, row, column, register chain, and direct link interconnects
Support for register packing Combining a register with combinational logic in a design
Support for register feedback Feedback from flip-flop output back into the LUT
20 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II Logic Element (LE)
21 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II LAB Structure
22 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Embedded Memory (M4K Block) 4,608 RAM bits Memory Configuration
True dual-port memorySimple dual-port memorySingle-port memory
Byte enable Parity bits Common Functions
Dual Port Memory Configuration
23 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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M4K RAM Block LAB Row Interface
24 PLD's and Altera Cyclone FPGA Prof. Anish Goel
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Cyclone II IOE Structure
25 PLD's and Altera Cyclone FPGA Prof. Anish Goel