Ip address lookup Bit Shuffle Trie

International Islamic University

IP Address Lookup using Bit-Shuffled Trie

Supervisor

Prof. Dr. Muhammad Sher

Candidate

Sunawar Khan

December 29, 2015

Outline

1. About the Paper1.1 What this Paper Tells1.2 When and Where

2. Abstract3. Introduction4. Motivation5. Proposed Method6. Multibit-trie to Bit Shuffled-trie7. Algorithmic Approach for Ip Lookup

7.1 Trie-Based Approach7.2 The Range Search Approach7.3 Hashing Based Approach

8. Bit Shuffled Trie9. Performance Evolution

9.1 Hardware Implementation Detail9.2 Implementing Updates to the routing tables

10. Extension to IPv611. Conclusion 2 of 32

Sunawar Khan - IP Address Lookup using Bit-Shuffled Trie

This Paper Studies About

• It tells that the size of IPv4 table is increased, the density of the21 to 24 bits prefixes will become higher.

• Reason: More prefixes encoded in a ST-Vector.

• Solution: A new elegant pipelined architecture for IPv4 and IPv6is presented.Two new method presented namely◦ the bit shuffled trie structure◦ Bit vector processing to facilitate the matching of variable-length

prefixes.

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prefixes.

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prefixes.

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The Paper

• Title: IP address lookup using bit-shuffled trie• Type: Study of IP address efficient memory management.

◦ Computer Communication◦ http://www.sciencedirect.com/science/article/pii/S014036641400142X/

• Authors:◦ Derek Pao◦ Ziyan Lu◦ Yat Hang Poon

• From: Electronic Engineering Department, City University of Hong Kong, Hong Kong

• Year: 2014• Volume: 47• Cited By:3

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Abstract

• An algorithmic RAM-based IP address lookup method calledbit-shuffled trie is presented.

• It Is very superior method for memory efficiency using pipelinedarchitecture.

• For memory efficiency purpose, the proposed method allow us toimplement the IP Address lookup engine for both IPv4 and IPv6on a single FPGA device.

• 8 operation required to process an insertion or deletion.

• Incremental updates to the routing table can handled efficiently.

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Abstract

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Abstract

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Abstract

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Abstract

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Introduction

Internet growth is rapidly increasing in term of users andcommunication line speed.• Routing table in routers can have half a million IPv4 prefixes.

• To support 100Gbps line speed, the IP address lookup engineneeds to perform 300 million lookup per second(MLPS).

• Ternary Content Addressable Memory(TCAM) had been apopular candidate for implement look up table.

• Industry and academia are eager to research on more cost-effectivealgorithmic RAM-based IP address lookup methods.◦ The IBM Power Edge network processor is equipped with on-chip

hardware accelerator to support wire-speed IP address lookup andpacket classification.

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Introduction

Internet growth is rapidly increasing in term of users andcommunication line speed.• Routing table in routers can have half a million IPv4 prefixes.• To support 100Gbps line speed, the IP address lookup engine

needs to perform 300 million lookup per second(MLPS).

• Ternary Content Addressable Memory(TCAM) had been apopular candidate for implement look up table.

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Introduction

needs to perform 300 million lookup per second(MLPS).• Ternary Content Addressable Memory(TCAM) had been a

popular candidate for implement look up table.

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Introduction

needs to perform 300 million lookup per second(MLPS).• Ternary Content Addressable Memory(TCAM) had been a

popular candidate for implement look up table.• Industry and academia are eager to research on more cost-effective

algorithmic RAM-based IP address lookup methods.◦ The IBM Power Edge network processor is equipped with on-chip

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New Presented Method

In this paper new presented method

• A new IP address method is called bit-shuffled-trie.

• For this purpose use FGPA device and achieve throughput of350MLPS.

• On average, about 8 memory writes are required to perform aninsertion deletion to the routing table.

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Introduction-Motivation

• System traverse the binary-trie to the packet destination IPaddress to IP lookup problem.

• Multiple bits are processed in a step called stride width.

• RAM based lookup engine is consisted of 2 index tables in thebasic configuration.◦ First level table has 1024 entries.◦ Second level table contains multiple 256-entry blocks.

• Reason for high memory cost.

• How memory cost reduced.

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• RAM based lookup engine is consisted of 2 index tables in thebasic configuration.

◦ First level table has 1024 entries.◦ Second level table contains multiple 256-entry blocks.

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• Result from above discussion◦ First:

• Advantage:Speed and simplicity.• Disadvantage:Memory efficiency.

◦ Second:

• Memory efficiency of the bit-map approach can be further improved.

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Proposed Method

• In our method, we try to minimize the memory cost of the IPaddress lookup engine by the following strategies.

◦ Prefixes in the routing table are divided into 6 groups based on theprefix length.

◦ All the prefixes in a group have a minimum length of Lmin bits. Theleading Lmin bits of the prefixes are called the fixed-length portion,and the remaining Lmax - Lmin bits are called the extension bits.

• A memory efficient search engine based on novel concept calledbit-shuffled trie.

◦ We shall exploit the parallelism offered by hardware implementation.

• Separate hardware pipeline are used to search the 6 group of prefixesin parallel.

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Proposed Method

• In our method, we try to minimize the memory cost of the IPaddress lookup engine by the following strategies.◦ Prefixes in the routing table are divided into 6 groups based on the

prefix length.

◦ All the prefixes in a group have a minimum length of Lmin bits. Theleading Lmin bits of the prefixes are called the fixed-length portion,and the remaining Lmax - Lmin bits are called the extension bits.

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Proposed Method

prefix length.◦ All the prefixes in a group have a minimum length of Lmin bits. The

leading Lmin bits of the prefixes are called the fixed-length portion,and the remaining Lmax - Lmin bits are called the extension bits.

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Proposed Method

prefix length.◦ All the prefixes in a group have a minimum length of Lmin bits. The

leading Lmin bits of the prefixes are called the fixed-length portion,and the remaining Lmax - Lmin bits are called the extension bits.

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An Examples

• Table 1 Shows that Consider a group of 5-bit prefixes.

Prefix Original Value Bit-shuffle Value

A 00001 00100B 00010 01000C 01000 00010D 01011 01110E 10011 11100F 10100 10001G 10110 11001H 11001 10110

Table: Sample Set of Prefixes11 of 32

Multibit-trie to Bit Shuffled-trie

1. Conventional multibit-trie, bits of the input address areprocessed from left to right.In bit-shuffled trie, bits of the input address can be processed insome other order.

2. Conventional multibit-trie, bits are processed in a given levelIn bit-shuffled trie,different subsets are processed in a given leveldepending on the search path.

3. Conventional multibit-trie, Expansion is required.Inbit-shuffled trie, bit-map approach use to handle the variation inprefix length.

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Algorithmic Approach - Related Work

In this section we review three algorithmic approaches for Ip lookup.

• Trie-Based Approach.

• The Range Search Approach.

• Hashing Based Approach◦ Iplookup is essentially a table lookup operation where routing table

size in the order of half million entries.◦ Mainly we focus on memory cost of the reviewed methods.

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Bit Shuffled Trie-Table Used

Prefix Length No of Prefixes Percentage(%)

8-12 Bits 313 0.18-12 Bits 13324 4.28-12 Bits 55153 17.28-12 Bits 246971 76.918-12 Bits 3544 1.18-12 Bits 1784 0.6

Total 321089 100

Table: Grouping Prefixes By Length-Table-1

Data Extract dated 2010-03-1914 of 32

Bit Shuffled Trie-Table Used

Prefix Length No of Prefixes Percentage(%)

8-12 Bits 373 0.18-12 Bits 15089 3.28-12 Bits 7217 15.38-12 Bits 382889 80.78-12 Bits 2641 0.68-12 Bits 744 0.2

Total 474452 100

Table: Grouping Prefixes By Length-Table-2

Data Extract dated 2014-01-0115 of 32

Bit Shuffled Trie

Figure: Over all structure of the IP Lookup engine

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Bit Shuffled Trie

1. Bit-shuffle and bit-extract circuits, and the subtree processingmodule.

2. Dimensioning of lookup tables and selection of bits.

3. Block overlaying and block compaction.

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Bit Shuffled Trie

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Bit Shuffled Trie

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Bit Shuffled Trie

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Bit Shuffled Trie-BitShuffle And Bit Extract

In this section we shall discuss the implementations of the two basicoperations, bit-shuffle and bit-extract. Bit-shuffle and bit-extractcircuits, and the subtree processing module

Data Bits d7 d6 d5 d4 d3 d2 d1 d0

Mask-Vector 0 1 0 1 0 0 1 0Outputs of bit-extract circuit 0 0 0 0 0 d6 d4 d1

Outputs of bit-shuffle circuit d7 d5 d3 d2 d0 d6 d4 d1

Table: An 8-bit example to illustrate the bit-shuffle and bit-extract operations

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Bit Shuffled Trie-Dimensioning and Selection of Bits

• Dimensioning of lookup tables and selection of bits.◦ The bit selection algorithm will select the bit with the highest

non-zero cost.In the event that all the bit positions have zero cost, i.e. allsubgroups have at most 1 key.The bit selection algorithm will then select the least significant(rightmost) bit out of the remaining bits.

• Pseudo Code Available

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Bit Shuffled Trie-Block Compaction and overlaying

• Block overlaying and block compaction.The bit-shuffling and indexing operations effectively divide thegroup of prefixes into subsets, where each subset has a smallnumber of items.

Address(hex) ps-bit Item(group)80 1 d,001000(G1)81 1 a,000001(G1)82 1 b,000010(G1)83 0 empty slot84 1 c,000100(G1)85 1 e,000101(G1)86 0 x,101010(G2)87 0 y,001101(G1)

Table: Overlaying of secondary groups and Selected bits

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Performance Evaluation

• Hardware Implementation Detail.

• Implementing Updates to the routing tables

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Hardware Implementation Detail.

• We evaluate the memory cost of the proposed method

Length-Group T1(mask/index) T2(bv + mask + base) T3(ps + residue prefix + base)

8-12 bits n/a n/a 512 * (0+0+15+19)13-16 bits 256×5 2K×(8+2+12) 4K × (0+2+15+19)17-20bits 1K×7 8K×(8+4+5) 24K × (1+4+15+19)21-24 bits 4K×9 32K×(8+6+17) 148K × (1+6+15+19)25-28 bits 128×(3+4+4) 1K×(8+15+12) 4K × (1+15+15+19)29-32 bits 256×(3+4+4) 2K×(8+18+11) 2K × (1+18+15+19)

Table: Memory usages of the 6 length-groups.

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• A comparison of the memory cost of some selected methods

Method No. of Prefixes Bytes/prefix Next-hop DataChang 163.5K 8.7 to 9.4 8-bit/prefixChang 301K 4.7 8-bit/prefixHsieh 220K,to 296K 15 8-bit/prefixSong 250K 22 8-bit/prefixLe 41 K to 155K 15 8-bit/prefixBando 279K 4 to 5.2 8-bit/prefixSourdis 270K 3 not includedSun 18K,to 161K 2.6 to 3 not includedBit-Shuffled Trie 474K 2.4 not included

3.05 8-bit/prefix

Table: Comparison of memory cost with some recent methods.

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Making speed comparison with other methods is more difficult. Theactual processing speed depends on four factors:

• The fabrication technology used.

• The memory model, i.e. ssingle-port vs. dual-port memory.

• The routing table size.

• Whether the hardware needs to access external RAM (other thanreading the next-hop data after the longest matching prefix hasbeen found) during the lookup operation.

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In this study, we rely on performance data obtainable from previouspublications.• Speed of is higher because it implemented on ASIC instead of

• Processing logic required in the basic binary-trie method issimpler.

Method Lookup(MLPS) Implementation Platform Remarks

Chang 167 to 200 Virtex-5Single-port RAMRequire access to externel RAM

Chang 377.5 Virtex-6 Single-port RAMLe 325 Virtex-4 Dual-port RAMJiang 250 Virtex-II Single-port RAM

Bando 200 Virtex-4Single-port RAMRequire access to externel RAM

Sourdis 500 to 700 90 nm ASIC Single-port RAMBit-Shuffled 175 Virtex-5 Single-port RAMTrie 350 Virtex-5 Dual-port RAM

Table: Comparison of operating speed with some recent methods.

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FPGA.• Processing logic required in the basic binary-trie method is

simpler.

Table: Comparison of operating speed with some recent methods.

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FPGA.• Processing logic required in the basic binary-trie method is

simpler.

Table: Comparison of operating speed with some recent methods.25 of 32

Incremental updates to the routing table

In this section we study dynamic updates to the bit-shuffled trie.There can be three types of updates to the routing table,

• Modification of the next-hop value associated with a prefix.

• Insertion of a new prefix.

• Deletion of an existing prefix.

In this study, we shall mainly consider insertions and deletions.

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Extension to IPv6 lookup

The 128-bit IPv6 address is logically divided into 2 parts

• The leading 64 bits correspond to the network address.

• The remaining 64 bits correspond to the host ID.In principle we can divide the prefixes into 12 length-groups whereeach length-group covers a range of 4 bits as in the case for IPv4

Output Signals Meaningsm0 if the first phase pipeline finds a matching prefix, m0 is set to 1;otherwise m0 is set to 0A0 if m0 = 1, then the corresponding next-hop data is found at NH[A0]cmd addr a reference address for accessing the command table of the second phase processing unitcmd vec a 4-bit vector representing which of the 4 s phase pipelines need to be searched

Table: Output signals of the first phase processing pipeline.

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• The remaining 64 bits correspond to the host ID.

In principle we can divide the prefixes into 12 length-groups whereeach length-group covers a range of 4 bits as in the case for IPv4

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Conclusion

A simple and elegant pipelined architecture for IPv4 and IPv6 lookupis presented.

• The proposed method makes use of two major ideas, namely◦ The bit-shuffled trie structure◦ The bit-vector processing.

• The memory cost of the proposed method is as low as 2.4 and8.25 bytes per prefix for IPv4 and IPv6.

• When the size of the IPv4 table is further increased, the density ofthe 21 to 24 bits prefixes will become higher.

In this paper method only requires about 3 MB of on-chip memoryto support a 500 K prefixes IPv4 routing table and a 200 K prefixesIPv6 routing table.

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Conclusion

A simple and elegant pipelined architecture for IPv4 and IPv6 lookupis presented.• The proposed method makes use of two major ideas, namely

◦ The bit-shuffled trie structure◦ The bit-vector processing.

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Conclusion

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Conclusion

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Conclusion

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Key Terms

• FGPA◦ Field Programmable Gate Array

• ASIC◦ Application Specified Integrated Circuits

• MLPS◦ Million Lookup Per Second

• TCAM◦ Ternary Content Address Matching◦ A Specified length speed Memory◦ Search Entire Content in a Single Clock Cycle.

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Key Terms

• LMP◦ Largest Matching Prefix◦ Used by Router in IP Networking

• Fabricated Technology◦ Process of Manufacturing

• IPv6◦ 128bit address, 64 bit for netwrok, 64 for host ID◦ Its Is Hexadecimal

• Packet Classification◦ Identification Packets for QOS◦ Packet Can be Classified by

Source and Destination PortAddress and Protocol Types

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Key Terms

• Routing Table◦ It Chose the best path.◦ Destination◦ Next HOP◦ Interface◦ Metric◦ Routes

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Thanks To All of You

• Name: Sunawar Khan Ahsan

• Class: MSCS-F14

• Subject: Advance Computer Networks

• Course Coordinator: Mr. Ghani

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Ip address lookup Bit Shuffle Trie

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