Io's and Interrupts

8/9/2019 Io's and Interrupts

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Book reading : Supplementary !!!

Topics covered in this lecture are from thesetexts.

!omp. Or". # Arc$itecture%&t$ edition%'tallin"s

or interrupts ()ele*ant to slides only

)ead !$apter Top le*el *iew of !omputerunctions%'ection + (su,part Interrupts

or Input / Output ()ele*ant to slides only

)ead !$apter Input / Output %section -%+

'ection % ()ele*ant details related to slidesonly


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Input/output :I/O


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Input/output Pro,lems

0$y I/1s not directly connected

to system ,us2 Wide variety of peripherals

Delivering dierent amounts of data

t dierent speeds n dierent formats

ll slowerthan "#$ and %&

'eed () modules


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Input/Output 3odule

nterface to "#$ and &emory

nterface to one or more peripherals


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I/O 3odule 'tructure : Dia"ram


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I/O 3odule unction

() &odule functioning could +e explained

+y processor communication. !ommand decodin"

Data

'tatus reportin"

Address )eco"nition

!ommand decodin" : () module acceptscommands from processor on "ontrol +us,

0ike read or -rite data.

Data :Data is exchanged +et-een processor

and () module over data +us


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I/O 3odule unction


+y processor communication. "ommand decoding

Data

Status reporting

ddress %ecognition

'tatus )eportin" : () module are much

slo-er than "#$ and memory, they had tosend STT$S signals to report their progress.1or 2xample : B$S3 or %2D3 signal to report() status to processor


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I/O 3odule unction


+y processor communication. "ommand decoding

Data

Status reporting

ddress %ecognition

Address )eco"nition : () module mustreceive multiple re4uests from processor thus

() module must recogni5e and decode eachaddress.1or 2xample : fter decoding () -ill identify,send control and data signal to selectedperipheral.


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I/O 3odule unction

"ontrol 6 Timing

"#$ "ommunication

Device "ommunication Data Buering

2rror Detection


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I/O 'teps

"#$ checks () module device status

() module returns status f ready, "#$ re4uests data transfer

() module gets data from device

() module transfers data to "#$

7ariations for output

Direct "#$ ccess

Direct &emory ccess


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!P6 7iewpoint

ssue read command

Do ot$er work "heck for interrupt at end of each

instruction cycle

f interrupted:8

Save context registers/

#rocess interrupt 1etch data 6 store

I f i I/O #


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Interfacin" I/O # processors :


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9+!A


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Interrupts

I t t


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Interrupts

&echanism +y -hich other modules e.g. ()/

may interrupt normal se4uence of processing #rogram

e.g. over9o-, division +y 5ero

Timer

enerated +y internal processor timer

$sed in pre8emptive multi8tasking

()

from () controller

*ard-are failure

e.g. memory parity error


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Interrupts

P l ! t l


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Pro"ram low !ontrol

'imple Interrupt Processin"


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'imple Interrupt Processin"

I t t ! l


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Interrupt !ycle

dded to instruction cycle

#rocessor checks for interrupt ndicated +y an interrupt signal

f no interrupt, fetch next instruction f interrupt pending:

Suspend execution of current program

Save context

Set #" to start address of interrupt handler routine #rocess interrupt

%estore context and continue interrupted program


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Interrupts


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() Wait


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Interrupts :

3ultiple Interrupts


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3ultiple Interrupts

Disa,le interrupts

#rocessor -ill ignore further interrupts -hilstprocessing one interrupt

nterrupts remain pending and are checkedafter ;rst interrupt has +een processed

nterrupts handled in se4uence as they occur De;ne priorities

0o- priority interrupts can +e interrupted +yhigher priority interrupts

When higher priority interrupt has +eenprocessed, processor returns to previousinterrupt


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Io's and Interrupts

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