Inverse modeling of two-dimensional MOSFET dopant profile via capacitance of the source/drain gated...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 7, JULY 2000 1385

Inverse Modeling of Two-Dimensional MOSFETDopant Profile via Capacitance of the Source/Drain

Gated DiodeC. Y. T. Chiang, Student Member, IEEE, Y. T. Yeow, Senior Member, IEEE, and R. Ghodsi, Member, IEEE

Abstract—This paper proposes and demonstrates a newapproach to two-dimensional (2-D) dopant profile extraction forMOSFET’s by treating the source/drain-to-substrate junction asa gated diode. The small-signal capacitance of the diode measuredas a function of gate and source/drain bias is used as the targetto be matched in an inverse modeling process. It is shown thatthis capacitance allows both the substrate dopant profile in thechannel region and the source/drain-to-substrate profile parallelto the surface to be evaluated with a single set of measurementdata. Experimental results for n-MOSFET’s with drawn channellength =1 m and 0.265 m are presented. Comparison ofother electrical measurement with simulation data based on theextracted profile is also given.

Index Terms—MOSFET’s, semiconductor device doping, semi-conductor device measurements, semiconductor device modeling.

I. INTRODUCTION

T HE dopant concentration profile of modern MOSFET’s,particularly ones exhibiting short-channel effects, has

major influence on the electrical characteristics of the device.The profile is the result of a large number of individual fabrica-tion processes and has to be determined from the final device.While many physico-chemical analysis techniques are nowavailable for dopant profile extraction (see [1] and referencestherein), they normally require extra chemical processing of thedevice and data calibration with respect to a reference for in-terpretation of the measured quantity. Dopant profile extractionbased on the electrical measurement of small-signal capaci-tance is a well-established method but only for one-dimensional(1-D) structures [2]. With the advances of numerical devicesimulation and increase in computation power and speed, theinverse modeling method [3] to obtain two-dimensional (2-D)dopant profile is becoming a viable alternative approach. Inthis method one or more measured electrical quantities of adevice are chosen as the target data; numerical simulation isthen carried out with an initial dopant profile for the device tocalculate the corresponding electrical quantities. The assumedprofile is then adjusted iteratively to obtain an optimal matchof simulation data to their experimental target. The adjustedprofile is then considered to be an accurate description of theactual profile of the device under test. For the extraction of

Manuscript received July 9, 1999; revised January 24, 2000. The review ofthis paper was arranged by Editor D. P. Verret.

C. Y. T. Chiang and Y. T. Yeow are with the Department of Computer Scienceand Electrical Engineering, University of Queensland, Brisbane, Qld, Australia4072 (e-mail: [email protected]).

R. Ghodsi is with Cypress Semiconductor, San Jose, CA 95134 USA.Publisher Item Identifier S 0018-9383(00)05197-2.

MOSFET 2-D dopant profile, Khalilet al.applied this methodto a combination of gate-to-source/drain capacitanceand drain/source-to-substrate junction [4]–[6] and Leeet al. [7] used current–voltage (I–V) data in the subthresholdregion in their inverse modeling. In both cases, a separatemeasurement on a MOS capacitor is used to first obtain thesubstrate profile in the channel region.

In this paper, we present an inverse modeling process for ex-tracting the complete 2-D profile of MOSFET’s using only thecapacitance of the drain/source-to-substrate junction .We treat the junction as a gated diode under the control of gatebias and junction reverse bias. With channel in accumulation,the measured capacitance includes the depletion capacitanceof the inner sidewall junction and is therefore a function thesource/drain-to-substrate junction profile in a direction parallelto the surface. By sweeping the junction reverse bias andthe channel to different levels of accumulation, we cause thedepletion region of this sidewall junction to sweep to varyingextent on both sides of the junction. By biasing the channelinto inversion, the measured capacitance includes the inversionlayer-to-substrate capacitance which is dependent on the sub-strate dopant profile in channel region [8]. Thus, by measuringthis capacitance over a suitable range of gate and source/drainbias, we would have captured the contributions to the measuredcapacitance from the dopant concentration of whole activeregion of the transistor, i.e., where the field-effect action ofthe gate is active. In comparison, the gate-to-source/draincapacitance referred to in previous paragraph is more a functionof the channel potential distribution along the surface arisingfrom a given source/drain reverse bias. Its dependence on thesurface dopant profile is through the fact that the dopant profileinfluences the channel potential distribution. This capacitanceis also insensitive to the dopant profile away from the surface,hence a separate extraction based on the capacitance–voltage(C–V) data of a MOS capacitor is needed to arrive at thesubstrate dopant profile in the channel region [4]–[6]. The sameapplies to the subthresholdI–V method [7].

The nature of the gated diode is such that the contributions tothe measured capacitance from the bottom and the outer side-wall junctions can be determined and subtracted from the mea-sured data. Only the capacitance contributions from the innersidewall junction and inversion layer-to-substrate junction areused as the target data in the inverse modeling process. This im-plies that the simulation work does not have to model the lengthof the experimental source and drain junctions or the outer side-wall of these junctions.

0018–9383/00$10.00 © 2000 IEEE

1386 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 7, JULY 2000

Fig. 1. Device bias forC measurement and components ofC(contributions from the source junction are not shown):C —inversionlayer-to-substrate capacitance,C —inner sidewall junction capacitance,C —bottom junction capacitance, andC —outer sidewall junctioncapacitance.

II. BASIS OFINVERSEMODELING

Fig. 1 shows the dc bias connection used in our measurement:the source/drain connected together is reverse biased with re-spect to the substrate and the gate is also biased with respect tothe substrate and goes from accumulation to inversion. The dia-gram also shows the various components of the source/drain-to-substrate capacitance

inversion layer-to-substrate capacitance ;drain/source-to-substrate inner sidewall capacitance ;drain/source-to-substrate bottom capacitance ;drain/source-to-substrate outer sidewall .

In general

As we vary the gate bias, the carrier type and concentration inthe channel region changes, and hence also the capacitances ofthe first two components which are associated with the channelregion.

Fig. 2 shows the measured as a function of gate-to-sub-strate bias and source/drain-to substrate reverse biasfor an n-channel LDD MOSFET ( m m, gateoxide nm). For a given gate bias, the measured capaci-tance decreases with increasing junction reverse bias due to theincrease of the depletion widths of the individual components.It can also be seen that at V, corresponding to a de-pleted surface in the transistor channel, the capacitance shows aminimum for all ’s. As the channel goes into accumulation( V) the inner sidewall capacitance comes into ex-istence and the measured capacitance increases due to reductionof the depletion width of this sidewall junction with increasingdegree of accumulation. In inversion ( V) the increasein the measured capacitance is due to the introduction of the in-version layer-to-substrate capacitance which very rapidlysaturates to a level corresponding a fixed substrate depletionwidth (at the given source/drain reverse bias). andare functions of the channel region substrate and source/drainjunction dopant profiles to be extracted as well as functions ofthe gate-to-substrate bias and the source/drain-to-substratebias . Their sum, is chosen as the target

Fig. 2. Three-dimensional plot of the measuredC as a function ofV andV for n-channel MOSFET with 1�m drawn channel length.

experimental data in our inverse modeling. Based on the knowl-edge of the fabrication processes of the devices under test, wehave modeled our device thus: source/drain junction by two 2-DGaussian profiles to account for LDD structure, the channelas two 1-D Gaussian profiles to account for threshold adjustand punch-through implants, and the substrate as a constantdopant concentration. The parameters of the Gaussian profilesare tabulated in Table I. The 2-D device simulator MEDICI [9]is used to obtain the simulated and hence also the simulated

for an initial set of parameter values. Taking themeasured as the target function, the values of allthese parameters are then adjusted simultaneously to ensure thesimulated matches the target function to withina preset level at a chosen number of bias points (see below). Anoptimization iteration based on the Levenberg–Marquardt algo-rithm [10] was used to adjust the parameters to achieve the fitbetween measured and simulation data. The optimization itera-tion was carried out within the device simulator.

When the gate bias is such that the channel region is depleted,both the above components disappear: because the inver-sion layer is absent, because the substrate next to the side-wall is completely depleted. Detailed examination of this rawmeasured as a function of in Fig. 2 reveals that thiscapacitance has a very “flat” minimum. This supports the argu-ment that at the minimum capacitance point there are no contri-butions from the -dependent components and .This applies for the complete range of , giving rise to theminimum capacitance line seen in Fig. 2. This minimum capac-itance line therefore represents the remaining capacitance com-ponents, i.e., which is a function of source/drainbias but not the gate bias. They are not of interest in our extrac-tion process and are removed from the measured capacitance be-fore applying inverse modeling. This is achieved by subtractingthe minimum capacitance line from all other measured data toleave behind as a function of and . Theresults are shown in Fig. 3.

The dopant profile extraction process starts by building up asuitable dopant profile model for the MOSFET with a number

CHIANG et al.: INVERSE MODELING OF TWO-DIMENSIONAL MOSFET DOPANT PROFILE 1387

Fig. 3. (C + C ) as a function ofV andV obtained from data inFig. 2 by subtracting the minimum measuredC atV = 0 V.

Fig. 4. Instrumentation for measurement ofC .

of analytical profiles reflecting the various fabrication processesinvolved. Each analytical profile has its own set of adjustable pa-rameters. A numerical device simulation program is then usedto evaluate the gated diode capacitance for the assumed profile.The best representation of the actual profile is obtained by ad-justing the parameters to produce the best fit of the simulatedcapacitance to the measured data. For matching purposes, theexperimental capacitance is reduced to per unit width quantityfor compatibility with results of 2-D simulator. Similar subtrac-tion process described in the treatment of experimental capaci-tance is used to remove the contributions of inthe simulation data. As mentioned before, by so doing we re-moved the necessity to simulate the actual length of the sourceand drain junctions and their outer sidewalls.

III. M EASUREMENT

Fig. 4 shows the instrumentation used to obtain the results inFig. 2. The HP4284A LCR meter was used to measure the ca-pacitance and to apply the reverse bias between the source/drainand the substrate . Measurement signal was 50 mV at 100kHz injected into the substrate and detected at the grounded

TABLE IDESCRIPTION OF ANALYTICAL PROFILES

USED IN INVERSEMODELING FOR1-�m DEVICE

Fig. 5. Comparison of measured and simulation(C + C ) per unitwidth as a function ofV with V as a parameter for the 1�m device.Lines are experimental data, “�” and “ ” are simulation data, and “�” areexperimental points chosen as target data for inverse modeling.

source and drain junctions. HP 4145A parameter analyzer wasused to provide the necessary gate-to-source/drain bias. Coaxialprobes and careful zeroing of the LCR meter are adopted to min-imize stray capacitance. Each data point is averaged over fivereadings to reduce measurement noise. With these precautions,the measurement is found to be repeatable and accurate to within1 fF.

IV. RESULTS AND DISCUSSION

The minimum capacitance line in the raw measured data inFig. 2 was subtracted from all other data points to give theplot of as a function of gate and source/drainbias in Fig. 3. From Fig. 3, 20 data points spread over gatebias corresponding to inversion ( V) and accumulation( V V) and for between 0 and 6 V were


Fig. 6. Three-dimensional plot of the extracted dopant profile for the 1�mdevice based on measured data in Fig. 3.

Fig. 7. Comparison of initial guess (dashed line) and extracted (solid line)dopant profile along the surface in the source-drain direction for the 1�mdevice.

selected as target experimental data for use in inverse modeling.Our analytical profile models and associated adjust parametersare described in Table I. The initial guess of each parameter wasset to the middle of range set and the simulation capacitance

was calculated for the same bias range used in measure-ment. Device gate length was set to the same drawn length, i.e.,1 m. Other device parameters such as gate material and workfunction difference, which would affect the threshold voltage,were selected to reflect the experimental device. To optimizethe parameters of the analytical models obtained, the simulatorwas programmed to run until the RMS error for the used 20 data

Fig. 8. Comparison of initial guess (dashed line) and extracted (solid line)substrate dopant profile in the middle of the channel for the 1�m device.

Fig. 9. Three-dimensional plot of the measuredC as a function ofV andV for n-channel MOSFET with 0.265�m drawn channel length.

is less than 5%. Where necessary the range limits for the param-eters were reset to ensure that the optimization process does notpush a parameter to its range limit.

Fig. 5 is the comparison of the experimental and simula-tion obtained after optimization—experimentaldata as lines and simulation as points (open circles). The 20data points used as target experimental data in the optimizationprocess are shown as filled circles. Within the 20 points chosenagreement is better than 5%. It can be seen that agreement else-where is just as good. Fig. 6 is the 3-D plot of the optimizedprofile. Figs. 7 and 8 are the surface dopant profile and the sub-strate dopant profile in the middle of the channel—dashed linesrepresent the initial guess profiles and full line the final profiles.We also briefly investigated the effects of changes in some as-sumed device parameters on extracted profiles: 5% change in


Fig. 10. Comparison of measured and simulation(C + C ) per unitwidth as a function ofV with V as a parameter for 0.265�m device. Linesare experimental data, “�” and “ ” are simulation data. “�” are experimentalpoints chosen as target data for inverse modeling.

Fig. 11. Three-dimensional plot of the extracted dopant profile for the 0.265�m device based on measured data in Fig. 10.

gate oxide thickness or gate length leads to a maximum of 10%change in the dopant concentration at the critical locations.

We repeated the same sequence of measurement, simulationand inverse modeling for another n-channel device from a dif-ferent process with drawn m m and gateoxide nm. The 3-D plot of the raw measured capaci-tance data is shown in Fig. 9. This device uses a retrograde welland is modeled as follows: source/drain junction by two 2-DGaussian profiles to account for LDD structure, the channel astwo 1-D Gaussian profiles to account for threshold adjust andretrograde well. Comparison of the measured and the post op-timization simulation is given in Fig. 10. The

Fig. 12. Comparison of initial guess (dashed line) and extracted (solid line)dopant profile along the surface in the source-drain direction for the 0.265�mdevice.

Fig. 13. Comparison of initial guess (dashed line) and extracted (solid line)substrate dopant profile in the middle of the channel for the 0.265�m device.

extracted profile for this device is shown in Fig. 11. Figs. 12 and13 are the surface dopant profile and the substrate dopant profilein the middle of the channel.

We have carried out several independent assessment of theextracted profiles by comparing other measured electrical datawith their simulation counterparts obtained using the extractedprofiles. Fig. 14 shows the - characteristics. It is knownthat simulationI–Vdata are sensitive to the mobility model used,particularly on the modeling of transverse field dependence. Inthis figure we included the simulationI–V data for two mo-bility models. They account for dopant concentration depen-dence and longitudinal field dependence in the same way buthave different surface-field dependence: one (SRFMOB2 in [9])in which the only the inversion carriers are affected by the trans-verse field and the other (PRPMOB in [9]) in which carriers atevery position is affected the transverse field. All parametersof the mobility models assume the default values given in [9].For , the transverse field is only a weak function ofthe substrate dopant concentration. The observed discrepancyin saturation drain current between experimental and either set


Fig. 14. (a) Comparison of measured and simulation per unit widthI -Vcharacteristics for the 1�m device. Simulation uses the extracted profile of Fig.6. Lines are experimental, and “�” and “�” are simulation based on the mobilitymodels SRFMOB2 and PRPMOB, respectively (see text for details of models).(b) As in (a) but for 0.265�m device.

of simulation is an artifact of transverse field modeling. How-ever, as seen from the linear to saturation operation transitionand the slope of the saturation current, pinch-off and channellength modulation effect appear to be same for the experimentaland two simulation data sets. This is an indication that experi-mental and simulation longitudinal field distributions and hencealso the LDD dopant profiles are in agreement.

With subthreshold current measured at mV andV, the current level and subthreshold slope are known to be

strongly dependent on the lateral dopant profile and channellength and less on carrier mobility [7]. Fig. 15 shows the mea-sured and simulation subthreshold current based on the sametwo mobility models. The excellent agreement is, we believe, astrong indication of the accuracy of the extracted dopant profile.

Comparison is also made between the measured and simu-lation gate-to-drain capacitance, again using the same twomobility models for simulation work. This is shown in Fig. 16.It is seen that at V, the agreement is good for the whole

Fig. 15. (a) Comparison of measured and simulation per unit widthsubthresholdI -V characteristics for the 1�m device forV = 50 mV and2 V. Simulation uses the extracted profile of Fig. 6. Lines are experimental,“�”, “ ” and “�”, and “�” are simulation based on the the mobility modelsSRFMOB2 and PRPMOB, respectively. (see text for details of models). (b) Asin (a) but for 0.265�m device.

range of . The agreement for is particularly signif-icant. As indicated previously, the capacitance with an accumu-lated or depleted channel is a reflection of the dc potential distri-bution across the drain-channel junction at the surface and henceof the dopant profile across the junction parallel to the surface.For V, drain current is flowing, the channel potentialdistribution and hence measured capacitance is now affected byinversion layer mobility. The differences between experimentaland simulation data are again attributed to the mobility modelsused in simulation [11]. In the case of the 0.265m device, theeffect of source resistance has lead to the at V and

V to be larger than that at V and V.

V. CONCLUSION

We have demonstrated a method for the extraction ofMOSFET 2-D dopant profile based on measurement and sim-ulation of the source/drain-to-substrate capacitance. Becausethe bias of the transistor is such that there is no dc drain current


Fig. 16. (a) Comparison of measured and simulation per unit widthC -Vcharacteristics for the 1�m device. Simulation uses the extracted profile of Fig.6. Lines are experimental, and “�” and “�” are simulation based on the mobilitymodels SRFMOB2 and PRPMOB, respectively (see text for details of models).(b) As in (a) but for 0.265�m device.

flowing in the device, the simulation results and hence thedopant profile arrived at is independent of carrier transportmodel assumed in the simulation [11]. While the measuredcapacitance is the usual depletion or space charge capacitance,our procedure of using a 2-D simulation program avoided theusual assumption of abrupt space charge model associated withdopant profile extraction.

The adopted analytical profiles described in this paper haveprovided excellent match between the experimental and simula-tion capacitance data. We attribute this to the fact that these pro-files are based on what are expected from the individual dopingprocesses involved in the production of the devices tested. Ad-ditional functions could be added to account for other dopingprocesses that are used in device fabrication. There is no proofof uniqueness of the profile extracted via inverse modeling, butwe believe that starting from process-based analytical modelswould ensure that the results are close to the actual profile.

The use of predetermined analytical models with adjustableparameters makes the inverse modeling process relativelysimple and fast. However common with other inverse modeling

schemes, the extracted dopant concentration at each point inthe device is influenced by all the target experimental datapoints. This implies that the dopant concentration at a particularlocation could be determined from measured capacitancesat bias for which this location is electrical neutral and thus,according to device physics, not contributing to the measuredcapacitances. It is therefore essential that the spread of theexperimental capacitances chosen as target data in terms ofthe bias voltages should "probe" the locations where dopantconcentration profile information is critical, i.e., the biasvoltages of target data should cause the depletion region edgeto sweep through these locations. However, this may not bepossible in practice due the upper limits of bias voltages thatcan be applied. From the understanding of the nature of thegated diode it can be said that capacitance data from an invertedsurface should be used to extract substrate dopant concentrationover the channel region and those from an accumulated surfaceused to extract the surface junction profile in the source-draindirection.

Finally, it should be stated that parameter optimization for theassumed dopant profiles requires the set of semiconductor equa-tions, including elements of the small-signal equivalent circuit,to be solved repeatedly as values of the parameters are changed.In order to reduce computation time, we are currently lookinginto the approach of solving only the Poisson’s equation. Thisis justified on the ground that the measurement being simulatedonly has junctions in reverse bias. The current densities shouldbe sufficiently low and can be ignored without significantly al-tering the accuracy of carriers and potential distributions.

ACKNOWLEDGMENT

The authors acknowledge the programming advice providedby B. Swaminath of TMA, Palo Alto.

REFERENCES

[1] A. C. Diebold, M. R. Kump, J. J. Kopanski, and D. G. Seiler, “Char-acterization of two-dimensional dopant profiles: Status and review,”J.Vac. Sci. Technol. B, vol. 14, pp. 196–201, 1996.

[2] D. Schroder, Semiconductor Material and Device Characteriza-tion. New York: Wiley, 1990.

[3] G. J. L. Ouwerling, “Physical parameter extraction by inverse devicemodeling: Application to one- and two-dimensional doping profiling,”Solid-State Electron., vol. 33, pp. 757–771, 1990.

[4] N. Khalil, J. Faricelli, D. Bell, and S. Selberherr, “A novel method forextracting the two-dimensional doping profile of a sub-half micronMOSFET,” in IEEE Symp. VLSI Technology 1994 Dig. Tech. Papers,1994, pp. 131–132.

[5] , “The extraction of two-dimensional MOS transistor doping viainverse modeling,”IEEE Electron. Device Lett., vol. 16, pp. 17–19, Jan.1995.

[6] N. Khalil, J. Faricelli, and C.-L. Huang, “Two-dimensional dopant pro-filing of submicron metal-oxide-semiconductor field-effect transistorusing nonlinear least squares inverse modeling,”J. Vac. Sci. Technol. B,vol. 14, pp. 224–230, 1996.

[7] Z. K. Lee, M. B. McIlrath, and D. A. Antoniadis, “Inverse modelingof MOSFET’s using I-V characteristics in the subthreshold region,” inIEDM. Tech. Dig., 1997, pp. 683–686.

[8] C. Y. T. Chiang, C. T. C. Hsu, Y. T. Yeow, and R. Ghodsi, “Measurementof MOSFET substrate dopant profile via inversion layer-to-substratecapacitance,”IEEE Trans. Electron. Devices, vol. 45, pp. 1732–1736,1998.

[9] MEDICI: Two-Dimensional Device Simulation Program. Palo Alto,CA: TMA Assoc., 1994.

[10] B. Swaminath, private communication.


[11] Y. T. Yeow, “Measurement and numerical modeling of short channelMOSFET gate capacitances,”IEEE Trans. Electron. Devices, vol.ED-34, pp. 2510–2520, 1987.

C. Y. T. Chiang (S’96) received the B.E. degree in electrical and electronicsengineering (with honors) from the University of Queensland, Brisbane, Qld.,Australia, in 1994. Since 1995, he has been a Ph.D. student in the Departmentof Computer Science and Electrical Engineering, University of Queensland.

His current research interests include extraction of 2-D dopant concentrationprofile on MOSFET.

Y. T. Yeow (M’76–SM’91) received the B.E. degree from the University ofCanterbury, New Zealand, the M.Sc. degree from the University of Manchester,U.K., and the Ph.D. degree from the University of Southampton, U.K.

R. Ghodsi (S’91–M’95) received the B.E. degree and the Ph.D. degree in elec-trical engineering from the University of Queensland, Brisbane, Qld, Australia,in 1990 and 1995, respectively.

From January 1995 to April 1997, he worked on device design and modelingat Quality Semiconductor, Sydney. Australia. In April 1997, he joined the R&DDepartment, Cypress Semiconductor, San Jose, CA, where he currently leadsthe quarter micron transistor module development integration. His research in-terests include device characterization, modeling, and reliability.

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