Introduction to VLSI DesignIntroduction to VLSI DesignIntroduction to VLSI DesignIntroduction to VLSI Design

Typical Design Flow High Level Design Low Level Designg

S. Choomchuay, Ph.D.Intro. to VLSI Design S. Choomchuay //KMITL 1

y,

R l f ChiR l f ChiRole of ChipsRole of Chips

IdIdea

Circuit DesignCircuit DesignApplicationsApplications

gg

FabricationFabrication

Intro. to VLSI Design S. Choomchuay //KMITL 2

VLSI Design ChallengeVLSI Design ChallengeVLSI Design ChallengeVLSI Design Challenge

I l Increasing productivity yield Shorter design cycle with more product feature Reduce NRE (Non Recursive Engineering Cost) Reduce NRE (Non-Recursive Engineering Cost) Design reuse enable Increase flexibility to design changesy g g Faster exploitation of alternative architecture Faster exploitation of alternative libraries

B & E i d i di i & ifi i Better & Easier design auditing & verification

Intro. to VLSI Design S. Choomchuay //KMITL 3

Development HistoryDevelopment HistoryDevelopment HistoryDevelopment History

SiliconGermaniumSemiconductorVacuum tube

SiliconGermanium

Discrete Small IC LSI VLSI

Metal Base PCB Chip

10-50 / 6"x9" 10-50 /2x2 mm 10000-100000/1x1 cm

Y1906 1930 1951 19751961 1969Intro. to VLSI Design S. Choomchuay //KMITL 4

Year1906 1930 1951 19751961 1969

IC Design & FabricationIC Design & FabricationIC Design & FabricationIC Design & Fabrication

circuit designDesign ToolsSim Toolscircuit design

&simulation

Layout (pattern)Design & synthesis

Sim. Tools

Design Tools

Fabrication

Design ToolsSim. Tools

Mask Set

ProcessAssembly

&Material &Equipments

IC Chips&Packaging

Equipmentsp

Intro. to VLSI Design S. Choomchuay //KMITL 5

Digital Circuit ConceptDigital Circuit ConceptDigital Circuit ConceptDigital Circuit Concept

S l V ltSwitch 1

Supply Voltage

Switch 2 Control

u

r

r

e

n

t

Result

C

Switch 3 Switch 4

Result

SwitchSwitch

Intro. to VLSI Design S. Choomchuay //KMITL 6

Switch & TechnologySwitch & TechnologySwitch & TechnologySwitch & Technology

Bipolar

Speed = ?Dissipation = ?Dissipation = ?

Mi dMi dMOSMOS

MixedMixed(BiCMOS)(BiCMOS)

Intro. to VLSI Design S. Choomchuay //KMITL 7

IC ProcessIC ProcessIC ProcessIC ProcessWafers

Mask Set

Protectivecover

SelectivePatterning

ImplantDope

Wafers

cover Patterning Dope

STEPS ?STEPS ?

Front End

Di i B di M ldiDicing Bonding Molding

B k E dIntro. to VLSI Design S. Choomchuay //KMITL 8

Back End

IC FabricationIC FabricationIC FabricationIC Fabrication3"- 8"

IC

Silicon WaferIC

PROCESSWater

Clean RoomWater

Air T t tCVDAir

E i

Treatment ImplanterStepperE-Beam

Environment Machines&

Tools

Furnace

Intro. to VLSI Design S. Choomchuay //KMITL 9

Tools

Process Keyword (1)Process Keyword (1)y ( )y ( )

O id tiO id tiOxidationOxidation

SiSi SiSi SiSi

siosio22SiSi SiSi SiSi

- Thermal-CVD

ImplantationImplantation

A liIntro. to VLSI Design S. Choomchuay //KMITL 10

Annealing

Process Keyword (2)Process Keyword (2)y ( )y ( )

Ph t lith hPh t lith hPhotolithographyPhotolithographyUV light, Electron Beam

PhotoresisPhotoresisSiOSiO22

MASK

SiPatterning

Developed

Etching &Strip off

Intro. to VLSI Design S. Choomchuay //KMITL 11

p

Behavioural Level of AbstractionBehavioural Level of AbstractionBehavioural Level of AbstractionBehavioural Level of Abstraction

SystemConceptConceptAlgorithm

ArchitectureArchitectureRTLGateGate

TransistorRTL = Register Transfer Level

Intro. to VLSI Design S. Choomchuay //KMITL 12

RTL = Register Transfer Level

VLSI D i D iVLSI D i D iVLSI Design DomainVLSI Design Domain

Abstract Structure Physical

Design DomainLevel ofAbstraction

ArchitectureDesignAlgorithm

System StructuralSynthesis

RTL LevelSynthesisStructural

DesignLogic

g

RTLSynthesis

Logic LevelSynthesisVerification

gDesign

LayoutDesign (Syn)

Logic

GateVerification

V ifi tig

Verification

Intro. to VLSI Design S. Choomchuay //KMITL 13

VLSI Low Level DesignVLSI Low Level DesignVLSI Low Level DesignVLSI Low Level DesignTypical Design FlowSpec

DesignHigh Level

p

SimulationMaskSets

High LevelModel

i l

Logic Simulation

Logic LevelModel

LogicSynthesis

Simulation

Place & RoutePLD,FPGA

Intro. to VLSI Design S. Choomchuay //KMITL 14Cell Library

VLSI Low Level DesignVLSI Low Level DesignVLSI Low Level DesignVLSI Low Level DesignCell Library Design

LogicDesign

DRC

SimulationLayoutDesign

Extraction

SimulationLogic Level

Model

SimulationCircuitDesign

MasksDeviceDevice Level Model

Intro. to VLSI Design S. Choomchuay //KMITL 15

Top Down DesignTop Down Design

System Level

Board Level

Chip LevelRTL

S th iC p eve Synthesis

Layout Synthesis

Intro. to VLSI Design S. Choomchuay //KMITL 16

HDL Synthesis ToolsHDL Synthesis ToolsVHDL

1980 VSHIC D D P j 1980 VSHIC, DoD Project 1983 IBM and TI joint project 1987 DoD and IEEE1076 Standards 1993 Revise of IEEE1076 1996 Extend to 1076.3 and 1076.4

Verilog 1981 CAE software launched by Dateway Design Auto.

(founded by Phil Mooreby) 1983 Release of Verilog HDL 1987 Extended to Verilog XLg 1989 Verylog XL is widely used 1990 Cadence bought Gateway 1995 Verilog --> IEEE1364

Intro. to VLSI Design S. Choomchuay //KMITL 17

1995 Verilog IEEE1364

Synthesis OptimisationSynthesis Optimisation

VHDL/VerilogVHDL/VerilogCriteria

Synthesis(Translation)

Area&

TimingAnalysis

Optimisationmodule

Constraints Analysis

Netlist

Intro. to VLSI Design S. Choomchuay //KMITL 18

Synthesis ConstrainsSynthesis ConstrainsSynthesis ConstrainsSynthesis Constrains

Global Circuit SpecificationGlobal Library process factor Operating voltage

Circuit Specification Area- max areaOperating voltage

Operating temperature Timing- fan-in, fan-out- I/p & o/p loading cap.p p g p- Max.clock frequency

Power- max powermax. power

Testability- Full or partial scan

Boundary scan- Boundary scan

Intro. to VLSI Design S. Choomchuay //KMITL 19

Layout DesignLayout DesignLayout DesignLayout DesignCircuit Level Design

Static Complement MOSStatic Complement MOS- Conventional Circuit

Dynamic LogicDynamic Logic- Clock CMOS- Domino Logic

Intro. to VLSI Design S. Choomchuay //KMITL 20

Layout DesignLayout DesignLayout DesignLayout DesignConventional static gate

(Complementary)CC

A B NMOS chain implements the functionY

NMOS chain implements the function PMOS chain is a complementaryarrangement of N-Chain

A

B

C

g Output is taken at the center

B CBAY += )(Intro. to VLSI Design S. Choomchuay //KMITL 21

Layout DesignLayout DesignLayout DesignLayout DesignActual MOS Devices

Gate (Control)

(N)(N)

Silicon(P)

= ? micronGate

Intro. to VLSI Design S. Choomchuay //KMITL 22

Layout DesignLayout DesignLayout DesignLayout DesignMOS Parameters

WW

Tox

Silicon(P)

(N)(N)

L2)( VVKIW/L defines MOS current

K = Process Transconductance

2)( TGSD VVKI =)]([2

1LW

OXCK =

Intro. to VLSI Design S. Choomchuay //KMITL 23

Layout DesignLayout Design W Channel WidthL Channel LengthMOS Device Model

S DG

L Channel LengthAD, AS Drain,Source AreaPD,PS Drain,Source Periphery

S DG

(N)(N)W

Substrate (P)

( )( )

v AS AD

Sub

vG

Cgs CgdCgsub

L

SubvS vDggsub

iD

Intro. to VLSI Design S. Choomchuay //KMITL 24vSub

Actual MOS DeviceActual MOS DeviceActual MOS DeviceActual MOS DeviceInverter, X-section

I/P

GND VddO/P

p pn np nP Well

N-Type Substrate

Intro. to VLSI Design S. Choomchuay //KMITL 25

Actual MOS DeviceActual MOS DeviceActual MOS DeviceActual MOS DeviceInverter, X-section

Vdd

p

n

I/P O/P

p

S

u

b

s

t

r

a

t

e

n

N

-

T

y

p

e

S

W

e

l

l

GND

n

p

P

InverterCircuit

ActualX-Section

LayoutDesign

Intro. to VLSI Design S. Choomchuay //KMITL 26

Circuit X-Section Design

LL--Edit, Tricky bitsEdit, Tricky bitsLL Edit, Tricky bitsEdit, Tricky bitsNOR 2-input (N well)

Only one active, We have to say N-active or P-active Poly Contact or Active Contact (both to metal) Substrate ties Substrate ties Port names need for extraction (simulation)( ) DRC needs

Intro. to VLSI Design S. Choomchuay //KMITL 27

Low Level Design, DRCLow Level Design, DRCLow Level Design, DRCLow Level Design, DRCWhat does it say?

Minimum features size(Layers & wire)2x2

Minimum spacing between2 objects

Define in base & micron Define in base & micronbase

2

Intro. to VLSI Design S. Choomchuay //KMITL 28

Low Level DesignLow Level DesignLow Level DesignLow Level DesignStick Diagram

Color stick objects represent layer and routing

Intro. to VLSI Design S. Choomchuay //KMITL 29

Low Level DesignLow Level DesignLayer design guide

LayerLayer RR CC CommentsCommentsMetal Low Low Power distributionMetal Low Low Power distribution

Global SignalLong wiringg g

Polysilicon Low Moderate High IR dropModerate RC productModerate RC product

Diffusion Moderate High High CapacitanceModerate IR dropModerate IR drop

Intro. to VLSI Design S. Choomchuay //KMITL 30

Low Level DesignLow Level DesignMOS as RC

WA

B

t

L

B

LLLR )(WWtA

R

pn

sAB

1;1

)(

==

===r

SubG tWLC )(0=

NMOSLWnq

R

pqnq

nAB

pp

n

)(1 =

OXTWLCg

t)(=

Intro. to VLSI Design S. Choomchuay //KMITL 31

LRAB

Low Level DesignLow Level DesignComplement Logic Switch

PMOSPMOSchain RP

NMOSchain

RnnCg

Intro. to VLSI Design S. Choomchuay //KMITL 32

Low Level DesignLow Level DesignLow Level DesignLow Level DesignSTD Cell Style

All Cells are same height Width can be varied Power rails (left-right)

Signals (top bottom) Signals (top, bottom) Routing channels outside

Intro. to VLSI Design S. Choomchuay //KMITL 33