Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Design Lecture # 2 A Circuit...

Introduction to VLSI Design – Lec01.

Chapter 1 Introduction to VLSI Design Lecture # 2 A Circuit Design Example


A Circuit Design Example• The digital circuit design cycle, we start from

– a logic diagram along with design specifications.

– The logic circuit is first translated into a CMOS circuit and the initial layout is done.

– From the layout, all of the important parasitics are calculated by using a circuit extraction program.

– Once a full circuit description is obtained from the initial layout, we analyze the circuit for DC and transient performance by using the circuit-level simulation program, SPICE,

– Compare the results with the given design specifications.


A Circuit Design Example

• If the initial design fails to meet any one of the specifications, which is the case in this exercise, we devise an improved circuit design to meet the design objective.

• Then the improved design will be implemented into a new layout and the design-analysis cycle will be repeated until all of the design specifications are met.

• The simplified flow of this circuit design procedure is illustrated in Fig. 1.6.


Figure The flow of circuit design procedures.


Example 1.1• design a one-bit binary full-adder circuit

• The design specifications are – Propagation delay times of sum and carryout signals.

– Circuit area

– Dynamic power dissipation

We start our design by considering the Boolean description of the binary adder circuit.


Example 1.1

• The sum-out and carry-out signals can be found as the following two combinational Boolean functions of the three input variables, A, B and C.

• A gate-level realization of these two functions is shown in Fig. 1.7.

• Note that instead of realizing the two functions independently, we use the carry-out signal to generate the sum output, since the output can also be expressed as


• This implementation will ultimately reduce the circuit complexity and, hence, save chip area.

• Also, we identify two separate sub-networks consisting of several gates (highlighted with dashed boxes) which will be utilized for the transistor-level realization of the full-adder circuit.

Example 1.1


• For translating the gate-level design into a transistor-level circuit description, we note that both the sum-out and the carry-out functions are represented by nested AND-OR-NOR structures in Fig. 1.7.

• Each such combined structure (complex logic gate) can be realized in CMOS as follows:

• the AND terms are implemented by series-connected nMOS transistors, and the OR terms are implemented by parallel-connected nMOS transistors.

• The input variables are applied to the gates of the nMOS (and the complementary pMOS) transistors.

• Thus, the nMOS net may consist of nested series-parallel, connections of nMOS transistors between the output node and the ground.

Example 1.1


• The resulting transistor-level design of the CMOS full-adder circuit is shown in Fig. 1.8.

• Note that the circuit contains a total of 14 nMOS and 14 pMOS transistors, together with the two CMOS inverters which are used to generate the outputs.


• In this specific example, it can also be shown that the dual (pMOS) network is actually equivalent to the nMOS network for both the sum_out and the carry-out functions, which leads to a fully symmetric circuit topology.

• The alternate circuit diagram obtained by applying this principle of symmetry in shown in Fig. 1.9.


• Note that the Boolean functions realized by the circuits shown in Fig. 1.8 and Fig. 1.9 are identical;

• the symmetric circuit topology shown in Fig. 1.9 significantly simplifies the layout.

• This initial sizing of transistors, which is obviously not an optimum solution, may be changed later depending on the performance characteristics of the adder circuit.

• Next, the initial layout of the full-adder circuit is generated.

• Here we use a regular, gate-matrix layout style in order to simplify the overall geometry and the signal routing.

• The initial layout using minimum-size transistors is shown in Fig. 1.10.


Note that in this initial adder cell layout, all nMOS and pMOS transistors are placed in two parallel rows, between the horizontal power supply and the ground lines (metal).


• The regular gate-matrix layout style used in this example also has the inherent advantage of being easily adaptable to computer-aided design (CAD).

• The designer must confirm, using an automatic design rule checker (DRC) tool, that none of the physical layout design rules are violated in this adder layout.

• This is usually done concurrently during the graphical entry of the layout.

• The next step is to extract the parasitic capacitances and resistances from the initial layout, and then to use a detailed

circuit simulation tool (e.g. SPICE) to estimate the dynamic performance of the adder circuit.

• Thus, we are now in the design verification stage of the design-flow diagram shown in Fig. 1.6.


• The parasitic extraction tool reads in the physical layout file, analyzes the various mask layers to identify transistors, interconnects and contacts, calculates the parasitic capacitances and the parasitic resistances of these structures, and finally prepares a SPICE input file that accurately describes the circuit (see Chapter 4).

• The extracted circuit file is now simulated using SPICE in order to determine its dynamic performance.

• The three input waveforms (A, B and C) are chosen so that all of the eight possible input combinations are applied consecutively to the full-adder circuit.


• Figure 1.11 shows the simulated input and output waveforms.

• Unfortunately, the simulation results show that the circuit does not meet all of the design specifications.


• Hence, the resizing of transistors is strictly an iterative process which involves several cycles of consecutive layout modification, circuit extraction, and simulation.


• Hence, the resizing of dimensions, showing the signal propagation delay during one of the worst-case transitions.

• we resize the nMOS and pMOS transistors in the full-adder circuit to meet the requirements, we can also reorganize the whole layout in order to achieve a more compact placement, to increase silicon area utilization, and to reduce the interconnection parasitics within the cell.

• The resulting cell layout is shown in Fig. 1.12.


• The full-adder circuit designed in this example can now be used as the basic building block of an 8-bit binary adder

• The simplest such adder can be constructed by a cascade-connection of eight full adders

• Hence, this cascade-connected adder configuration is called the carry ripple adder (Fig. 1. 15).


• Figure 1.16 shows the mask layout of a 4-bit-section of the carry ripple adder circuit

• Such structures are routinely used in circuits where a large number of arithmetic operations are required, such as arithmetic-logic units (ALUs) and digital signal processing (DSP) circuits.


• The overall performance of the multi-bit adder can be further increased by various measures

• The simulated input and output waveforms of the 8-bit binary adder circuit are shown in Fig. 1.17 for a series of sample input vectors.

• It can be seen that the sum bit of the last adder stage is typically generated last, and the overall delay can be as much as 7 ns.


• This example has shown us that the design of CMOS digital integrated circuits involves a wide range of issues, from Boolean logic to gate-level design, to transistor level design, to physical layout design, and to parasitics extraction followed by detailed circuit simulation for design tuning and performance verification.

• In essence, the final output of integrated circuit design is the mask data from which the actual circuit is fabricated.

• It is important to design the layout and, hence, the mask set such that the fabricated integrated circuits meet test specifications with a high yield.

• To achieve such a goal, designers perform extensive simulations using computer models extracted from the layout data and iterate the design until simulated results meet the specifications with sufficient margins.

Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Design Lecture # 2 A Circuit...

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