Introduction to VLSI Design

ByN.Nagaraju Assistant ProfessorDept.of ECE

Acronym of VLSI

V -> VeryL -> LargeS -> ScaleI -> Integration

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Introduction

Electronic device

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Introduction

Electronic device PCB

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Introduction

Electronic device PCB Integrated circuit

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IntroductionElectronic device PCB Integrated circuit

Integrated circuit - core

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IntroductionElectronic device PCB Integrated circuit

InterconnectionIntegrated circuit - core

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IntroductionElectronic device PCB Integrated circuit

InterconnectionIntegrated circuit - core Transistor

Wire Bonding

lead frame gold wire

bonding pad

connecting pin

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Why doing IC design?

IC Design - maximum freedom of adjusting parameters of the

electronic circuit to meet the specification

A pplication

S pecific

I tegrated

C ircuit

Large integration density Scaling Low power Low cost Most of modern electronics is fabricated by CMOS

High speed – low noise applications High power consumption Low density integration Typical applications: TTL logic, OpAmps,

discrete components Widely used in the past

Bipolar technology CMOS technology

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Why Make ICs Integration improves

Physical Size, Speed, Power consumption, Reliability

Integration reduce manufacturing costs Very Large Scale Integration (VLSI)

design/manufacturing of extremely small, complex circuitry using semiconductor material

integrated circuit (IC) may contain millions of transistors, each a few m in size

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A Brief History Invention of the Transistor

Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

1947: first point contact transistor (3 terminal devices) William.B.Shockley, John Bardeen and

Walter.H.Brattain at Bell Labs

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A Brief History, contd.. 1958: First integrated circuit

Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor

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A simple oscillator IC with five integrated components (resistors, capacitors, distributed capacitors and transistors)

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1959 - Planar technology invented

Kilby's invention had a serious drawback, the individual circuit elements were connected together with gold wires making the circuit difficult to scale up to any complexity.

By late 1958 Jean Hoerni at Fairchild had developed a structure with N and P junctions formed in silicon. Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions.

In 1959, Robert Noyce also of Fairchild had the idea to evaporate a thin metal layer over the circuits created by Hoerni's process.

The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Planar technology set the stage for complex integrated circuits and is the process used today. 

Planar technology IC

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IC Fabrication Technology: History (cont.)

1960 - Epitaxial deposition developed Bell Labs developed the technique of Epitaxial Deposition whereby a single crystal layer of material is deposited on a crystalline substrate. Epitaxial deposition is widely used in bipolar and sub-micron CMOS fabrication.  

1960 - First MOSFET fabricated Kahng at Bell Labs fabricates the first MOSFET.

1961 - First commercial ICs Fairchild and Texas Instruments both introduce commercial ICs.

1962 - Transistor-Transistor Logic invented 1962 - Semiconductor industry surpasses $1-billion in sales

1963 - First MOS IC RCA produces the first PMOS IC.

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1963 - CMOS invented Frank Wanlass at Fairchild Semiconductor originated and published the idea of

complementary-MOS (CMOS).

It occurred to Wanlass that a complementary circuit of NMOS and PMOS would draw very little current. Initially Wanlass tried to make a monolithic solution, but eventually he was forced to prove the concept with discrete devices.

Enhancement mode NMOS transistors were not yet available and so Wanlass was used a depletion mode device biased to the off-state.

Amazingly CMOS shrank standby power by six orders of magnitude over equivalent bipolar or PMOS logic gates.

On June 18, 1963 Wanlass applied for a patent. On December 5th 1967 Wanlass was issued U.S. Patent for "Low Stand-By Power complementary Field Effect Circuitry".

CMOS forms the basis of the vast majority of all high density ICs manufactured today.

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Microprocessor invented 1971- Intel 4004

The combination of the Busicom (Japanese calculator company) and Intel the first 4-bit microprocessor was in production. required roughly 2,300 transistors to implement, used a silicon gate PMOS

process with 10µm linewidths, had a 108KHz clock speed. In 1974 Intel introduced the 8080, the first commercially successful

microprocessor.

1972 - Intel 8008

The 8008 was the 8 bit successor to the 4004 and was used in the Mark-8 computer, one of the first home computers.

The 8008 had 3,500 transistors, a 200kHz clock speed

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Pentium processor invented1993 - Intel Pentium I

The Pentium is the first processor from Intel capable of executing more than 1 instruction per clock cycle. The Pentium was manufactured in a silicon gate BiCMOS process with 0.8µm linewidth, required 18 mask layers and had 1 polysilicon layer and 3 metal layers, the Pentium had 3.1 million transistors, a 60 to 66MHz clock speed and a 264mm2 die size.

1994 - 64Mbit DRAM The 64Mbit DRAM was produced on a CMOS process with 3 to 5 polysilicon layers, 2 to 3 metal layers and 0.35µm minimum features. The resulting product had a 1.5µm2 memory cell size.

1997 - Intel Pentium IIThe Pentium II was manufactured in a silicon gate CMOS process with 0.35µm linewidth, required 16 mask layers and had 1 polysilicon layer and 4 metal layers, the Pentium II had 7.5 million transistors, a 233 to 300MHz clock speed and a 209mm2 die size.

1998 - 256Mbit DRAM The 256Mbit DRAM was produced on a CMOS process with 4 to 5 polysilicon layers, 2 to 3 metal layers and 0.25µm minimum features.The product had a die size of approximately 204mm2.

1999 - Intel Pentium IIIThe Pentium III returned to a more standard PGA package and integrated the cache on chip. The Pentium III was manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium III had 28 million transistors, a 500 to 900MHz clock speed and a 140mm2 die size.

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VLSI Trends: Moore’s Law In 1965, Gordon Moore predicted that

transistors would continue to shrink, allowing: Doubled transistor density every 18-24 months Doubled performance every 18-24 months

History has proven Moore right

Gordon MooreIntel Co-Founder and Chairmain Emeritus

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Moore’s Law

1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 18-24 months

Year

Transistors

40048008

8080

8086

80286Intel386

Intel486Pentium

Pentium ProPentium II

Pentium IIIPentium 4

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

1970 1975 1980 1985 1990 1995 2000

Integration Levels

SSI: 10 gates

MSI: 1000 gates

LSI: 10,000 gates

VLSI: > 10k gates

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Microprocessor trends

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IC Evolution SSI – Small Scale Integration (early 1970s)

contained 1 – 10 logic gates, Flipflops MSI – Medium Scale Integration

logic functions, counters, Multiplexer LSI – Large Scale Integration

first microprocessors on the chip, ROM, RAM VLSI – Very Large Scale Integration

now offers 64-bit microprocessors, complete with cache memory, floating-point arithmetic unit(s), etc.

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IC Evolution Bipolar technology

TTL (transistor-transistor logic) ECL (emitter-coupled logic)

MOS (Metal-oxide-silicon) initially difficult to manufacture nMOS (n-channel MOS) technology developed in 1970s

required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market.

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IC Evolution aluminum gates for replaced by polysilicon by early

1980 CMOS (Complementary MOS): n-channel and p-

channel MOS transistors => lower power consumption, simplified fabrication process

Bi-CMOS - hybrid Bipolar and CMOS (for high speed)

GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF)

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Performance of Available Technologies

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VLSI Technology - MOS Transistors

Key feature:transistor length L

p+ p+

n substrate

channel

Source Drain

p transistor

G

S

D

SB

Polysilicon GateSiO2Insulator L

W

G

substrate connectedto VDD

Polysilicon GateSiO2Insulator

n+ n+

p substrate

channel

Source Drain

n transistor

G

S

D

SB

LW

G

S

D

substrate connectedto GND

2002: L=130nm2003: L=90nm2005: L=65nm2013: L=22nm2017: L=?

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Microprocessor Trends (Log Scale)

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DRAM Memory Trends (Log Scale)

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Intel 4004 Introduction date:

November 15, 1971 Clock speed: 108 KHz Number of transistors: 2,300

(10 microns) Bus width: 4 bits Addressable memory: 640

bytes Typical use:

calculator, first microcomputer chip, arithmetic manipulation

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Gallery - Pentium Processors

Pentium® III28M transistors / 733MHz-1Gz / 13-26W

L=0.25µm shrunk to L=0.18µm

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Gallery – Pentium Processors

Pentium® 442M transistors / 1.3-1.8GHz / 49-55W

L=0.18µm

Pentium® 4 “Northwood”55M transistors / 2-2.5GHz

L=0.13µm

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Pentium 4 0.18-micron process technology

(2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz) Introduction date: August 27, 2001

(2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz)

Level Two cache: 256 KB Advanced Transfer Cache (Integrated)

System Bus Speed: 400 MHz Transistors: 42 Million Typical Use: Desktops and entry-

level workstations 0.13-micron process technology

(2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 512 KB Advanced Transistors: 55 Million

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The wafer processing which is performed in a Wafer Fab area.

wafer fabrication is a series of 16-24 loops, each putting down a layer on the device. Each loop comprises some or all of the major steps of photolithography, etch, strip, diffusion, ion implantation, deposition, and chemical vapor deposition.

At each stage, various inspections and measurements performed to monitor the process and equipment. It has the cleanest environment in the world - many times cleaner than the best hospital operating theater.

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Test, Assembly and Packaging, where the finished wafer is split up into individual die (chips) which are then assembled into packages which can be handled in the final applications.

Full functional electrical test is performed at both wafer and package level to ensure outgoing quality.

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