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![Page 1: Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.](https://reader038.fdocuments.net/reader038/viewer/2022110207/56649d345503460f94a0b3ae/html5/thumbnails/1.jpg)
Introduction to VHDL
(Lecture #5)
ECE 331 – Digital System Design
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
![Page 2: Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.](https://reader038.fdocuments.net/reader038/viewer/2022110207/56649d345503460f94a0b3ae/html5/thumbnails/2.jpg)
Spring 2011 ECE 331 - Digital Systems Design 2
The Design ProcessDesign conception
VHDLSchematic capture
DESIGN ENTRY
Design correct?
Functional simulation
No
Yes
No
Synthesis
Physical design
Chip configuration
TimingRequirements met?
Timing simulation
Yes
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Spring 2011 ECE 331 - Digital Systems Design 3
Introduction to VHDL What is VHDL?
Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
VHDL is a formal language for specifying the behavior and structure of a digital circuit.
Verilog is another, equally popular, hardware description language (HDL).
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Spring 2011 ECE 331 - Digital Systems Design 4
Hardware Description Languages
Both VHDL and Verilog are hardware description languages.
They describe hardware! They are not software programming
languages. This is an important, but difficult, concept to
understand.
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Spring 2011 ECE 331 - Digital Systems Design 5
VHDL Designs
A VHDL design is composed of two parts: Entity Architecture
The entity statement defines the interface to the circuit (i.e. inputs and outputs).
The architecture statement describes the implementation of the circuit.
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Spring 2011 ECE 331 - Digital Systems Design 6
The Entity Statement
Defines the input and output of the design.
entity entity-name is port(port-name-A: mode type;port-name-B: mode type;port-name-C: mode type;… );
end [entity][entity-name];
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Spring 2011 ECE 331 - Digital Systems Design 7
Ports
Each I/O signal in the entity statement is referred to as a port.
A port is analogous to a pin on a schematic. Similar to variables in a HLL, a port is a data
object. Can be assigned values. Can be used in expressions.
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Spring 2011 ECE 331 - Digital Systems Design 8
Mode
The mode describes the direction in which data is transferred through a port.
There are 4 different modes:
Mode Description
in Data only flows into the entity (input)
out Data only flows out of the entity (output)
inout Data flows into or out of the entity (bidirectional)
buffer Used for internal feedback
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Spring 2011 ECE 331 - Digital Systems Design 9
Type
VHDL is a strongly typed language. Data objects of different types cannot be
assigned to one another without the use of a type-conversion function.
There are two broad categories of data types: scalar
stores a single value composite
stores multiple values
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Spring 2011 ECE 331 - Digital Systems Design 10
Types
The VHDL data types include:
bitbooleanintegercharacterstd_ulogicstd_logicbit_vectorstringstd_ulogic_vectorstd_logic_vector
scalar
composite
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Spring 2011 ECE 331 - Digital Systems Design 11
Types
The most useful types for synthesis and simulation, provided by the IEEE std_logic_1164 package, are:
std_logic std_ulogic std_logic_vector std_ulogic_vector
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Spring 2011 ECE 331 - Digital Systems Design 12
IEEE Standard Logic Types
Use of two-valued logic (bit and bit_vector) is generally not sufficient to simulate digital systems.
In addition to 0 and 1, Z (high-impedance), X (unknown), and U (uninitialized) are often used in digital system simulation.
The IEEE standard 1164 defines the std_logic type that has nine values:
0, 1, Z, X, U, W, L, H, -
Use std_logic and std_logic_vector in your designs.
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Spring 2011 ECE 331 - Digital Systems Design 13
The Architecture Statement
Describes the implementation of the design. Specifies the function of the design.
architecture architecture-name of entity-name is[declarations]
beginarchitecture body
end [architecture][architecture-name];
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Spring 2011 ECE 331 - Digital Systems Design 14
The Architecture Statement
One or more architecture statements may be associated with an entity statement.
Only one may be referenced at a time. Declarations
Signals and components. Architecture body
Statements that describe the functionality of the design (i.e. the circuit).
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Spring 2011 ECE 331 - Digital Systems Design 15
Architecture Body
Several different models, or styles, may be used in the architecture body, including:
Behavioral Dataflow Algorithmic
Structural These models allow you to describe the
design at different levels of abstraction. Algorithms → Gates
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Spring 2011 ECE 331 - Digital Systems Design 16
Behavioral Model
Specify a set of statements to model the function, or behavior, of the design.
Dataflow: uses concurrent statements
Algorithmic: uses sequential statements
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Spring 2011 ECE 331 - Digital Systems Design 17
Structural Model
Specify a set of statements to instantiate and interconnect the components necessary for the design.
Components are defined separately. Signals are used to interconnect components. Results in a hierarchical design.
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Spring 2011 ECE 331 - Digital Systems Design 18
Components
A component is a predefined element used in an hierarchical design.
Component declaration
component component-name port( port-name-A: mode type;
port-name-B: mode type;… );
end component;
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Spring 2011 ECE 331 - Digital Systems Design 19
Components
Component instantiation
label: component-name port map( port-name-A => signal-name-A,
port-name-B => signal-name-B,… );
The above mapping of port names to signal names is known as named association.
Positional association may also be used.
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Spring 2011 ECE 331 - Digital Systems Design 20
Signals
A signal is used to interconnect components in an hierarchical design.
Signal declaration
signal signal-name: type;
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Spring 2011 ECE 331 - Digital Systems Design 21
Statements Concurrent statements
All are executed at the same time. The order is unimportant.
Sequential statements Executed in the order in which they are listed. The order is very important.
The Process statement Sequential statements must be enclosed
within a process statement.
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Spring 2011 ECE 331 - Digital Systems Design 22
Statements
signal assignment conditional signal assignment selected signal assignment signal assignment if-then-else case for loop
Concurrent
Sequential
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Spring 2011 ECE 331 - Digital Systems Design 23
The Process Statement
The process statement is used to define an algorithm.
The process, or algorithm, is composed of a set of sequential statements.
The sequential statements and their order define the algorithm.
All process statements execute concurrently. A process statement has a sensitivity list.
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Spring 2011 ECE 331 - Digital Systems Design 24
Operators
Logical and, or, nand, nor, xor, xnor
Relational =, /=, <, <=, >, >=
Shift sll, srl, sla, sra, rol, ror
Addition / Subtraction +, -, & (concatenate)
Multiplication / Division *, /, mod, rem
Unary +, -
Miscellaneous not, abs, ** (exponent)
Assignment <=
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Spring 2011 ECE 331 - Digital Systems Design 25
Synthesis
A design can be synthesized using any of the architecture models.
However, one model may be more optimal than another, depending on the criteria and constraints of the design.
Regardless of the model used, a netlist is generated in the synthesis process.
The netlist is then “programmed” into a PLD to realize the design.
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Spring 2011 ECE 331 - Digital Systems Design 26
Basic Conventions
VHDL is case insensitive. It is a free-format language.
Allows spacing for readability All statements must end with a semicolon. Comments start with “--” and continue to the
end of the line.
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Spring 2011 ECE 331 - Digital Systems Design 27
Basic Conventions
All names and labels should start with a letter. They should contain only alphanumeric
characters and the underscore. Should not have 2 consecutive underscores. Should not end with an underscore.
All names and labels should be unique within a given entity and architecture.
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Spring 2011 ECE 331 - Digital Systems Design 28
Basic Conventions
Filename should match entity name. Only one entity per file. There may be more than one architecture for
each entity. However, only one architecture may be
associated with an entity at any point in time.
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Spring 2011 ECE 331 - Digital Systems Design 29
A simple logic circuit
Example
F
A
B
C
BC
AB
A
C
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Spring 2011 ECE 331 - Digital Systems Design 30
Signal Assignment
signal-name <= expression [after delay];
Can be a signal or a port.
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Spring 2011 ECE 331 - Digital Systems Design 31
Conditional Signal Assignment
signal-name <= expression1 when condition1else expression2 when condition2else expression3 when condition3… ;
[after delay] can be included after each of the expressions
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Spring 2011 ECE 331 - Digital Systems Design 32
Selected Signal Assignment
with expression selectsignal-name <= expression1 when choice1,
expression2 when choice2,...expressionN when others;
[after delay] can be included after each of the expressions
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Spring 2011 ECE 331 - Digital Systems Design 33
Example: A simple logic circuit
F
A
B
C
BC
AB
A
C
Entity
Architecture
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Spring 2011 ECE 331 - Digital Systems Design 34
Example: Entity
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Spring 2011 ECE 331 - Digital Systems Design 35
Example: Architecture #1
BehavioralModel
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Spring 2011 ECE 331 - Digital Systems Design 36
Example: Architecture #2
BehavioralModel
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Spring 2011 ECE 331 - Digital Systems Design 37
Example: Architecture #3
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Spring 2011 ECE 331 - Digital Systems Design 38
Example: Architecture #3 (cont.)
StructuralModel
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Spring 2011 ECE 331 - Digital Systems Design 39
Arithmetic Operations on Standard Logic Vectors
The basic IEEE standards do not define arithmetic operations for bit_vectors or std_logic_vectors.
The package IEEE.Std_logic_unsigned defines arithmetic operations on std_logic_vectors.
The arithmetic operators (+, −, and *) and comparison operators (<, <=, =, /=, >=, >) defined in this package treat std_logic_vectors as unsigned binary numbers.
These operators are referred to as overloaded operations. This means that the compiler will automatically use the proper definition of the operator depending on its context.
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Spring 2011 ECE 331 - Digital Systems Design 40
Questions?