Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI...
Transcript of Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI...
![Page 1: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/1.jpg)
Introduction to the PCI Interface
Meeta Srivastav
4th March, 2005
![Page 2: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/2.jpg)
2
Talk layout
BUS standardsPCI Local BusPCI protocolSpecial CasesElectrical and Mechanical SpecificationsOther Topics
![Page 3: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/3.jpg)
3
Inside a Computer
What is a BUS?Components – Processor, Memory etcPeripheralsInterconnection
MotivationData flowSpeed
![Page 4: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/4.jpg)
4
Local Bus
A set of parallel conductors, which allow devices attached to it to communicate with the CPU. The bus consists of three main parts:
Control lines, Address lines , Data lines
![Page 5: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/5.jpg)
5
BUS ProtocolsRequirements of a BUS standard
Electrical, Mechanical requirementsProtocol requirements
Common BUS standardsISA and EISA MCA (Micro Channel Bus)VESA Local BUS (Video Electronic Standard Associations) – 1-2 devices can be connected.PCI Local BUS
![Page 6: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/6.jpg)
6
ISA (Industry Std Arch.)Has a clock speed limit of 8 MHz
Has a word length of 8 or 16 bits (8 or 16 data lines)
Requires two clock ticks to transfer data (16 bit transfers)
Very slow for high performance disk accesses and high performance video cards
![Page 7: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/7.jpg)
7
EISA (Enhanced Std Arch)
Has a clock speed of 8.33 MHzMaximum of a 32-bit wide word length(32 data lines)Can support lots of devices Supports older devices which have Slower or Smaller word lengths(ISA)Transfers data every clock tick.
![Page 8: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/8.jpg)
8
MCA (Micro-channel Bus)
Has a clock speed of 10 MHz Has a 32 bit word length (32 data lines)Transfers data every clock tick.
![Page 9: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/9.jpg)
9
VESA (Video Electronic Std Arch.)
Has a clock speed limit of 33 MHz.Limited to a 32-Bit wide word length (32 data lines).Cannot take advantage of the Pentium’s 64 bit architecture. Limited support for Burst Transfers, thereby limiting the achievable thruput.Restricted on the number of devices which can be connected ( 1 or 2 devices).
![Page 10: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/10.jpg)
10
PCI Local Bus
Bus Width – 32 or 64 bitsOperating frequency – 0-66 MHzCan support many more devices then VESA64 bit extension for Pentium proc.Greater Variety of Expansion cards available.Multiplexed Address and DataPCI SIG (Special Interest Group)
![Page 11: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/11.jpg)
11
PCI Local Bus Revisions
1.0 – 1992.2.0 – connector and expansion board specification2.1 – 66MHz operation2.2 – protocol, electrical and mechanical specs
![Page 12: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/12.jpg)
12
PCI General Block Diagram
![Page 13: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/13.jpg)
13
PCI Local Bus Features Performance –
Burst Transfer at 528 MBps peak (64 bit- 66 MHz)Fully concurrent with Processor-Memory subsystemAccess time is as fast as 60ns.Hidden central arbitration.
Low cost – multiplexed, no glue logicLow Pin count – 47 pin for target; 49 pin as initiator.Ease of Use – full auto configurationFlexibility – processor independent, accommodates other protocolsGreen Machine ‘CMOS drivers -> low power
![Page 14: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/14.jpg)
14
PCI devices and PCI cores
Every device on the PCI bus is eitherPCI compliant – has the same signals as the PCI busConnected via a PCI core – this piece of hardware does the interfacing
Common devicesAudio/Video cardsLAN cardsSCSI controllers
![Page 15: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/15.jpg)
15
PCI Core – 9656BA
![Page 16: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/16.jpg)
16
PCI Interface Signals
![Page 17: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/17.jpg)
17
PCI System Signals
CLK : clean signal derived from the clock generator (33MHz , 66MHz)RST# : Active Low Asynchronous resetPAR : Parity Signal to ensure the parity across the AD bus and C/BE.
![Page 18: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/18.jpg)
18
PCI Bus Protocol –Signal Definition
AD – Multiplexed address and data linesC/BE# - Command and Byte EnablesFRAME# - Master indicating start/end of
transferIRDY# - Master (initiator) readyTRDY# - Target readyDEVSEL# - Target device selectedREQ# - Request for busGNT# - Bus Grant
![Page 19: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/19.jpg)
19
PCI control signals contd.
STOP# [I/0]: Target asserts to stop the transaction in Progress.IDSEL [I]: Used as chip selectLOCK# [I/0] : During semaphore currently accessed target locked by initiator DEVSEL# [I/0] :Asserted by target when the target asserts has decoded its address. (if by 6 clk not asserted => master abort.
![Page 20: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/20.jpg)
20
PCI Configuration Register
Device IDVendor IDStatus / Command regBase Address [0,1,2,3,4,5]Maximum LatencyMinimum GNTSubsystem ID, Subsystem Vendor ID
![Page 21: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/21.jpg)
21
PCI Command Types [C/BE]
0000 -> INTR ack0010 -> I/O Read0011 -> I/O Write0110 -> Memory Read0111 -> Memory Write1010 -> Configuration read1011 -> Configuration write
![Page 22: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/22.jpg)
22
JTAG boundary scan
Test Access PortTest ClockTest Data inTest Data outTest Mode selectTest Reset
IEEE standard 1149.1 compliant
![Page 23: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/23.jpg)
23
Interrupts
Asynchronous events4 interrupt lines for multi-functional devices.Interrupt lines goes to the interrupt controller to execute the ISR
![Page 24: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/24.jpg)
24
PCI Bus Protocol –Transfer mechanism
Configuration read/writeIO read/writeBurst
Basic form of data transferIncludes one address phaseOne or more data phase
![Page 25: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/25.jpg)
25
Burst Transfer Mechanism
Assert REQ#GNT# grantedWait for current transaction to endAssert FRAME#Transfer data when both TRDY# and IRDY# are assertedDe-assert FRAME# during last data phase
![Page 26: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/26.jpg)
26
Timing Diagram for a basic Read operation
![Page 27: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/27.jpg)
27
Various read transaction
Single cycle Read Burst data readRead with no wait statesByte Enables can be changed for every data cycleData Cycle with NO byte enables.
![Page 28: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/28.jpg)
28
Basic Write Operation
![Page 29: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/29.jpg)
29
Transaction termination
Last data phase completes when!FRAME and TRDY (normal - master)!FRAME and STOP (target termination) !FRAME and Device Select Timer expires (Master abort)!DEVSEL and STOP (Target abort)
![Page 30: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/30.jpg)
30
Multiple bus
PCI to PCI bridgeConcept of LOCKAll on one level
![Page 31: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/31.jpg)
31
Thank you
![Page 32: Introduction to the PCI Interface - CSE, IIT Bombaycs330/pci.pdfcontroller to execute the ISR 24 PCI Bus Protocol – Transfer mechanism Configuration read/write IO read/write Burst](https://reader030.fdocuments.net/reader030/viewer/2022040303/5e8fe2187744b84026414dae/html5/thumbnails/32.jpg)
32
Books for reference
PCI System Architecture Tom Shanley and Don Anderson..Mindshare