Introduction to Silicon Protection Array Devices.

26
Introduction to Silicon Protection Array Devices

Transcript of Introduction to Silicon Protection Array Devices.

Page 1: Introduction to Silicon Protection Array Devices.

Introduction to Silicon Protection

Array Devices

Page 2: Introduction to Silicon Protection Array Devices.

2

Version01_100407

Outline

ESD Protection– Test Pulse Waveforms

– Compare w/ Lightning

Key Parameters– VRWM or VR

– VBR

– VC

– Capacitance

– VESD

– IP or IPP

Configurations– Grounded TVS Diode Arrays (SP03)

– TVS Rail Clamp Diode Arrays (SP3, SP4)

– TVS Arrays (SP1, SP05)

– SCR Array Rail Clamps (SP7)

– EMI Filter Arrays (SP6) PC Board Layout Issues

– Close to the input

– Avoiding stub traces

– Paralleling channels

Package Options– Micro Packages

– MSOP Packages

– Power Packages

Page 3: Introduction to Silicon Protection Array Devices.

3

Version01_100407

ElectroStatic Discharge Protection

ESD is one of four major threats to electronic equipment.

Protecting equipment against ESD is a $500M market

Lightning

AC Power Contact

Sustained Overload

Page 4: Introduction to Silicon Protection Array Devices.

4

Version01_100407

ESD is FAST!!

AC Power Contact tests are measured in milliseconds 1000 milliseconds = 1 second

Lightning pulses are measured in microseconds 1000 microseconds = 1 millisecond

ESD pulses are measured in nanoseconds 1000 nanoseconds = 1 microsecond

An object traveling at the speed of light can go:• Around Earth more than 7 times in one second• 186 miles or 300 km in one millisecond• 1000 feet or 300 m in one microsecond• 1 foot or 30 cm in one nanosecond

Page 5: Introduction to Silicon Protection Array Devices.

5

Version01_100407

30 600 (nS)

ESD Test WaveformsIEC 61000-4-2

Lightning test waveforms usually peak at 100A – 500A.

Compared to lightning protectors, ESD protectors are:• Faster• Smaller• Less robust

Page 6: Introduction to Silicon Protection Array Devices.

6

Version01_100407

Outline

ESD Protection– Test Pulse Waveforms

– Compare w/ Lightning

Key Parameters– VRWM or VR

– VBR

– VC

– Capacitance

– VESD

– IP or IPP

Configurations– Grounded TVS Diode Arrays (SP03)

– TVS Rail Clamp Diode Arrays (SP3, SP4)

– TVS Arrays (SP1, SP05)

– SCR Array Rail Clamps (SP7)

– EMI Filter Arrays (SP6) PC Board Layout Issues

– Close to the input

– Avoiding stub traces

– Paralleling channels

Package Options– Micro Packages

– MSOP Packages

– Power Packages

Page 7: Introduction to Silicon Protection Array Devices.

7

Version01_100407

Key Parameters: VRWM or VR

The Reverse Standoff Voltage or VRWM is the maximum voltage that can be applied to the ESD protector without activating the device.

Page 8: Introduction to Silicon Protection Array Devices.

8

Version01_100407

Key Parameters: VBR

The Breakdown Voltage or VBR is the voltage at which the device will begin to break down and begin to protect.

Page 9: Introduction to Silicon Protection Array Devices.

9

Version01_100407

Key Parameters: VC

The Clamp Voltage or VC is the maximum voltage that will appear across the device during the specified surge event.

Page 10: Introduction to Silicon Protection Array Devices.

10

Version01_100407

Key Parameters: Capacitance

Capacitance adversely affects high data rate signals. Lower capacitance s always better.

Capacitance may be specified at various bias voltages or between various pins.

Page 11: Introduction to Silicon Protection Array Devices.

11

Version01_100407

Key Parameters: VESD

VESD is a measure of the robustness of the device. It is the maximum test voltage that can be sustained without damaging the device. The test conditions are specified.

Page 12: Introduction to Silicon Protection Array Devices.

12

Version01_100407

Key Parameters: IP

The Peak Current or IP (or sometimes Ipp) is the maximum peak current that can be applied to the ESD protector without damaging the device. The surge waveform conditions are always specified. Sometimes, several surge waveforms are specified:

Page 13: Introduction to Silicon Protection Array Devices.

13

Version01_100407

Outline

ESD Protection– Test Pulse Waveforms

– Compare w/ Lightning

Key Parameters– VRWM or VR

– VBR

– VC

– Capacitance

– VESD

– IP or IPP

Configurations– Grounded TVS Diode Arrays (SP03)

– TVS Rail Clamp Diode Arrays (SP3, SP4)

– TVS Arrays (SP1, SP05)

– SCR Array Rail Clamps (SP7)

– EMI Filter Arrays (SP6) PC Board Layout Issues

– Close to the input

– Avoiding stub traces

– Paralleling channels

Package Options– Micro Packages

– MSOP Packages

– Power Packages

Page 14: Introduction to Silicon Protection Array Devices.

14

Version01_100407

Grounded TVS Diode Arrays (SP03)

Capacitance Range: 8pF-16pF (typical)

ESD Range: ±20-30kV (contact discharge)

Lightning Range: 100-150A

Applications: Broadband Protection (i.e. 10/100/1000 Base T Ethernet)

Page 15: Introduction to Silicon Protection Array Devices.

15

Version01_100407

TVS Rail Clamp Diode Arrays (SP3, SP4)

Capacitance Range: 0.65pF-2pF (typical)

ESD Level: ±20-30kV (contact discharge)

Lightning Range: 2.5-10A

Applications: HDMI, USB2.0/3.0 and tertiary Ethernet protection

Page 16: Introduction to Silicon Protection Array Devices.

16

Version01_100407

TVS Arrays (SP1, SP05)

Capacitance Range: 3.5pF-30pF (typical)

ESD Level: ±8-30kV (contact discharge)

Lightning Range: 2-8A

Applications: Keypads, audio lines, and general low-speed bus protection

Page 17: Introduction to Silicon Protection Array Devices.

17

Version01_100407

SCR Array Rail Clamps (SP7)

Capacitance Range: 3pF-5pF (typical)

ESD Level: ±4-8kV (contact discharge)

Lightning Range: 3-14A

Applications: uP Logic Inputs and general low-speed bus protection

Page 18: Introduction to Silicon Protection Array Devices.

18

Version01_100407

EMI Filter Arrays (SP6)

EMI Filter Arrays not only provide ESD protection, but also serve as low-pass filters to get rid of unwanted high-frequency signals (i.e. cellular band from 800MHz-2GHz).

Capacitance Range: 10pF-25pF (typical single Cd)

ESD Level: ±15-30kV (contact discharge)

Applications: Keypad and display interfaces for portable/mobile devices

Page 19: Introduction to Silicon Protection Array Devices.

19

Version01_100407

Outline

ESD Protection– Test Pulse Waveforms

– Compare w/ Lightning

Key Parameters– VRWM or VR

– VBR

– VC

– Capacitance

– VESD

– IP or IPP

Configurations– Grounded TVS Diode Arrays (SP03)

– TVS Rail Clamp Diode Arrays (SP3, SP4)

– TVS Arrays (SP1, SP05)

– SCR Array Rail Clamps (SP7)

– EMI Filter Arrays (SP6) PC Board Layout Issues

– Close to the input

– Avoiding stub traces

– Paralleling channels

Package Options– Micro Packages

– MSOP Packages

– Power Packages

Page 20: Introduction to Silicon Protection Array Devices.

20

Version01_100407

PC Board Layout Considerations

Minimize D1 – Place protection near entry connector Maximize D2 – For best coordination with on-chip ESD protection Minimize D3 – Stub traces should be avoided

D1 D2

I/O Line

D3

Signal Ground

Pro

tect

ed

IC

ESDEntry Point

S.P.A.Some tips on getting the most from the ESD protection device you have selected:

Page 21: Introduction to Silicon Protection Array Devices.

21

Version01_100407

Combining Protection Channels

It is possible to combine protection channels to achieve higher surge capability:

For example, a customer loves the SOT553 package of the SP3003-02XTG, but needs a bit more VESD capability. You could use an SP3003-04XTG and combine the four channels into two. (As a bonus, the package becomes stub-less through-line!)

Of course the capacitance will double, but this may be acceptable.

A further benefit is the clamping voltage for a particular test waveform will be lower when channels are combined.

Page 22: Introduction to Silicon Protection Array Devices.

22

Version01_100407

Outline

ESD Protection

– Test Pulse Waveforms

– Compare w/ Lightning Key Parameters

– VRWM

– VBR

– VC

– Capacitance

– VESD

– IP

Configurations– Grounded TVS Diode Arrays (SP03)

– TVS Rail Clamp Diode Arrays (SP3, SP4)

– TVS Arrays (SP1, SP05)

– SCR Array Rail Clamps (SP7)

– EMI Filter Arrays (SP6) PC Board Layout Issues

– Close to the input

– Avoiding stub traces

– Paralleling channels

Package Options– Micro Packages

– MSOP Packages

– Power Packages

Page 23: Introduction to Silicon Protection Array Devices.

23

Version01_100407

SC70 SOT5x3 SOT23 SOT143 SOD723 uDFN

Available in SeriesSP1, SP3, SP05, SP4, SP6

Micro Packages

Page 24: Introduction to Silicon Protection Array Devices.

24

Version01_100407

MSOP Packages

Available in Series SP05, SP3

Page 25: Introduction to Silicon Protection Array Devices.

25

Version01_100407

Power Packages

Available in Series:  SP7, SP03 

SP03

PDIP-8

SOIC-16

PDIP-16

SOIC-8

Page 26: Introduction to Silicon Protection Array Devices.

26

Version01_100407

Thank You!