Introduction to Routers and Switches
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Transcript of Introduction to Routers and Switches
Basic Architectural Componentsof an IP Router
Control Plane
Datapath”per-packet processingSwitching
ForwardingTable
Routing Table
Routing Protocols
Per-packet processing in an IP Router
1. Accept packet arriving on an incoming link.
2. Lookup packet destination address in the forwarding table, to identify outgoing port(s).
3. Manipulate packet header: e.g., decrement TTL, update header checksum.
4. Send packet to the outgoing port(s).
5. Buffer packet in the queue.
6. Transmit packet onto outgoing link.
General Switch Model
Cross-bar
InputBuffer
Control
OutputPorts
Input Receiver Transmiter
Ports
Routing, Scheduling
OutputBuffer
Interconnect
IP Switch Model
2. Interconnect 3. EgressForwardin
gTable
ForwardingDecision
1. Ingress
Forwarding
Table
ForwardingDecision
Forwarding
Table
ForwardingDecision
Forwarding Engine
header
payload
Packet
Router
Destination Address
Outgoing Port
Dest-network PortForwarding Table
Routing Lookup Data Structure
65.0.0.0/8
128.9.0.0/16
149.12.0.0/19
3
1
7
The Search Operation is not a Direct Lookup
(Incoming port, label)
Ad
dre
ss
MemoryD
ata
(Outgoing port, label)
IP addresses: 32 bits long 4G entries
The Search Operation is also not an Exact Match Search
• Hashing • Balanced binary search trees
Exact match search: search for a key in a collection of keys of the same length.
Relatively well studied data structures:
0 224 232-1
128.9.0.0/16
65.0.0.0
142.12.0.0/19
65.0.0.0/8
65.255.255.255
Example Forwarding Table
Destination IP Prefix Outgoing Port
65.0.0.0/8 3
128.9.0.0/16 1
142.12.0.0/19 7
IP prefix: 0-32 bits
Prefix length
128.9.16.14
Prefixes can Overlap
128.9.16.0/21 128.9.172.0/21
128.9.176.0/24
Routing lookup: Find the longest matching prefix (the most specific route) among all prefixes that match the destination address.
0 232-1
128.9.0.0/16142.12.0.0/1965.0.0.0/8
128.9.16.14
Longest matching prefix
8
32
24
Prefixes
Pre
fix L
en
gth
128.9.0.0/16142.12.0.0/19
65.0.0.0/8
Difficulty of Longest Prefix Match
128.9.16.14
128.9.172.0/21
128.9.176.0/24
128.9.16.0/21
Lookup Rate Required
12540.0OC768c2002-03
31.2510.0OC192c2000-01
7.812.5OC48c1999-00
1.940.622OC12c1998-99
40B packets (Mpps)
Line-rate (Gbps)
LineYear
DRAM: 50-80 ns, SRAM: 5-10 ns
31.25 Mpps 33 ns
0
10000
20000
30000
40000
50000
60000
70000
80000
90000
100000
Size of the Forwarding Table
Source: http://www.telstra.net/ops/bgptable.html
95 96 97 98 99 00Year
Num
ber
of
Pre
fixes
10,000/year
Internal Interconnects
Io
I1
I2
I3
Io I1 I2 I3
O0
Oi
O2
O3
RAMphase
O0
Oi
O2
O3
DoutDin
Io
I1
I2
I3
addr
1. Multiplexers 2. Tri-State Devices
3. Shared Memory
InterconnectsTwo basic techniques
Input Queueing Output Queueing
Usually a non-blockingswitch fabric (e.g. crossbar)
Usually a fast bus
Shared Memory Bandwidth
SharedMemory
200 byte bus
5ns SRAM
1
2
N
• 5ns per memory operation• Two memory operations per packet• Therefore, up to 160Gb/s• In practice, closer to 80Gb/s
Input buffered swtich
• Independent routing logic per input– FSM
• Scheduler logic arbitrates each output– priority, FIFO, random
• Head-of-line blocking problem
Cross-bar
OutputPorts
Input Ports
Scheduling
R0
R1
R2
R3
Internconnect
(Virtual) Output Buffered Switch
• How would you build a shared pool?
Control
OutputPorts
Input Ports
OutputPorts
OutputPorts
OutputPorts
R0
R1
R2
R3
N buffers per input
Output scheduling
• n independent arbitration problems?– static priority, random, round-robin
• simplifications due to routing algorithm?• general case is max bipartite matching
Cross-bar
OutputPorts
R0
R1
R2
R3
O0
O1
O2
InputBuffers