Introduction to HDL-based design...
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1 Logic Synthesis TSRI 楊智喬 Email: [email protected] Outline Introduction to Cell-based Design Flow Logic Synthesis Introduction to Logic Synthesis Coding Style for Synthesis Static Timing Analysis Synopsys Design Compiler SDF and Gate-Level Simulation 2
Transcript of Introduction to HDL-based design...
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Logic Synthesis
TSRI 楊智喬
Email: [email protected]
Outline
Introduction to Cell-based Design Flow
Logic Synthesis
Introduction to Logic Synthesis
Coding Style for Synthesis
Static Timing Analysis
Synopsys Design Compiler
SDF and Gate-Level Simulation
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Cell-Based Design Flow
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Function Spec. Write Hardware Description Language (HDL) Code
Layout Verification
HDL Verification
Logic/Scan Synthesis
Automatic Physical Design
Layout Merge
Tape Out
Timing Spec. Power Spec. Test Consideration Cost Consideration ...
constraints
Implementation
Verification
Post-layout Gate-level Verification
Pre-layout Gate-level Verification
Implementation
Write HDL Code
Logic/Scan Synthesis
Automatic Physical Design
Layout Merge
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Write HDL Code
A Hardware Description Language (HDL) is a high-level programming language used to model the hardware logic circuit
Provide the abilities to
Model the connectivity of a circuit - structure
Model the functionality of a circuit - behavior
Model at various levels of abstraction
Model the timing information and timing constraints
Express concurrency
Verilog vs. VHDL 5
Logic Synthesis
module top(clk, in1, in2, out); input clk, in1, in2; output out; reg out; always @(posedge clk) begin out = in1 & in2; end endmodule
Q
QSET
CLR
D
in1
in2 out
clk
RTL Gate-level
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Link between a HDL and a netlist
Only a subset of HDL can be used (RTL) as source.
Optimization is based on the given constraints.
Logic Synthesis
HDL Source
Generic Boolean (GTECH)
Translate + Logic Optimization (Technology Independent)
Target Technology
Map + Gate Optimization
residue = 16’h0000; if (high_bits == 2’b10) residue = state_table[index]; else state_table[index] = 16’h0000;
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Scan Synthesis
Design for Testability (DFT)
Scan Synthesis, BIST...
Controllable and Observable
Full scan chain
Enable fast ATPG
Achieve the highest fault coverage
Partial scan chain
Not all flip flops are scanned
For high performance or area-sensitive design
Requires expensive computations (sequential ATPG)
Fault coverage is not predictable
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Automatic Physical Design - Placement
Q
QSET
CLR
D
Cell Abstract
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Automatic Physical Design - Routing
Q
QSET
CLR
D
in2
clk
out
in1
in1 out
n1
n2
n1 n2
Cell Abstract
in2 clk
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Layout Merge
Q
QSET
CLR
D
in2
clk
out
in1
in1
in2 clk
out
n1
n2
n1 n2
Cell Layout
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Automatic Physical Design Design Library Setup
Partitioning / Floorplan
Power Planning
Cell Placement
Clock Tree Synthesis
Routing DFT,
DFM
, D
esi
gn I
nte
grity
...
Physi
cal O
ptim
ization
GDSII Layout
Standalone Physical Optimization Tools
Synthesizer
Iterations... Timing may not be closed.
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Floorplan Design Library Setup
Partitioning / Floorplan
Power Planning
Cell Placement
Clock Tree Synthesis
Routing
GDSII Layout
Core Rows IO Rows
Corner Row
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Power Planning Design Library Setup
Partitioning / Floorplan
Power Planning
Cell Placement
Clock Tree Synthesis
Routing
GDSII Layout
power ring
block ring
stripe
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Cell Placement Design Library Setup
Partitioning / Floorplan
Power Planning
Cell Placement
Clock Tree Synthesis
Routing
GDSII Layout
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Clock Tree Synthesis (CTS) Design Library Setup
Partitioning / Floorplan
Power Planning
Cell Placement
Clock Tree Synthesis
Routing
GDSII Layout
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Routing Design Library Setup
Partitioning / Floorplan
Power Planning
Cell Placement
Clock Tree Synthesis
Routing
GDSII Layout
Follow Pins
Connect Block
Connect Stripe
Connect IO Pad
Connect IO Pad
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Verification (Categorized by Flow) HDL Verification
Function Verification: Simulation, Model Checking, Code Coverage Analysis...
Power Estimation
Pre-layout Gate-level Verification
Function Verification: Simulation, Formal EC...
Timing Verification: Simulation, STA...
Power Analysis
Post-layout Gate-level Verification
The same as pre-layout stage with accurate interconnect parasitic
Layout Verification
Function/Timing/Power Verification: by SPICE-like simulator
Physical Verification
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Verification (Categorized by Type)
Dynamic Verification w/ input stimulus
For Function, Timing, Power...
Simulation, Emulation...
Static Verification w/o input stimulus
For Function, Timing, Power...
Formal Verification, Static Timing Analysis (STA)...
Physical Verification
DRC, ERC, LVS
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Simulation Observe the response by a given stimulus
Advantage: verify timing and function at the same time
Disadvantage: computationally intensive, maybe incomplete (limited coverage)
Also called dynamic timing analysis (DTA)
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Static Timing Analysis Determine the longest and shortest path between
register to register or register to IO boundary
Advantage: Exhaustive timing coverage, Does not require input vectors, More efficient than DTA in memory and CPU resources (Faster operation & Capacity for millions of gates)
Disadvantage: For synchronous logic only, Difficult to learn, Tricky constraints beyond the boundaries of single clock flip-flop design chips, Lack of consistent conventions
IN Q D
QN
Q D
QN
CLK
OUT
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Formal Verification
Model Checking determine if a design obeys behavioral characteristics
defined by the user, typically in the form of assertions or properties
Formal Equivalence Checking (EC) To verify the consistency of a design as it is transformed
from one level of abstraction to another, such as when a RTL design is synthesized into gates
To ensure that some modifies on the circuit will not change the functionality
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Physical Verification – DRC, ERC
DRC checks the layout geometries against fabrication rules.
width check
area check
outside spacing check
inside spacing check
enclosure spacing check
ERC checks for electrical violations such as open circuits, short circuits, or floating devices and nodes.
geom2
geom1
geom1 geom2
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Physical Verification - LVS
t1
GND
VDD
t1i1
t2
i2
z t1i1 z
GND
VDD
i2
nd02d1
U2
inv0d1
U1
i1
i2
t1z
t2
A Y A
B
Y
inv0d1
nd02d1
i1
i2nd02d1
t1
z
inv0d1
U1
U2
A Y
A
BY
BlackBox
BlackBox
LVS Black-box LVS
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Standard Cell Library - Cells
Core cells
random logic
combinational logic: buffers, logic gates, adders, multiplex, ...
sequential logic: flip-flop, latch, scan flip-flop/latch
regular logic
RAM, ROM, data path generator
I/O cells
I/O pads: CMOS I/O, TTL I/O, ...
power pads: I/O, core
special pads: crystal oscillator, clock buffer, corner, filler, ...
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Standard Cell Library - Creation Pre-design
target for specific process
layout parameters
equal cell height
minimum routing (pin) grid
on grid pin location
same power line location/width
W/L values for transistors
Pre-Verify and Pre-characterize
models for design flow
simulation, synthesis, P&R...
A1 A2 Z
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Standard Cell Library - Models Simulation Model
Function, Timing (in the form of HDL)
Synthesis Model
Function, Timing, Power (.lib is the most popular format)
Physical Footprint (Abstract)
Pin, Blockage, Via, PRBoundary (Abutment Box or AB)
Noise Model for SI Analysis
Current Source Model for IR Drop Analysis
Model for DFT (Design for Testability)
APTG, Fault Coverage Analysis
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EDA Tools - Implementation
Logic Synthesis
Synopsys: Design Compiler
Automatic Physical Design
Cadence: Innovus
Synopsys: IC Compiler
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EDA Tools – Verification
HDL Simulator
Cadence: NC-Verilog
DRC/LVS Verification
Mentor: Calibre
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